CN101119010A

CN101119010A - Semiconductor optical device and manufacturing method therefor

Info

Publication number: CN101119010A
Application number: CNA2007101399201A
Authority: CN
Inventors: 志贺俊彦
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2006-08-04
Filing date: 2007-08-03
Publication date: 2008-02-06

Abstract

A LD (Laser Diode) includes: a laminated semiconductor structure including an active layer, a p-cladding layer, a contact layer, etc. that are sequentially on top of one another on an n-GaN substrate; a waveguide ridge including the contact layer and a portion of the p-cladding layer; a first silicon insulating film covering sidewalls of the waveguide ridge and having an opening that exposes a top of the waveguide ridge; an adhesive layer disposed on the first silicon insulating film, but not in the opening, and on the top of the waveguide ridge, wherein the adhesive layer includes a first adhesive film of Ti; and a p-side electrode over the adhesive layer such that the p-side electrode is in contact with the contact layer at the top of the waveguide ridge, through the opening.

Description

Semiconductor optical device and manufacture method thereof

Technical field

The present invention relates to semiconductor optical device (optical device) and manufacture method thereof, particularly relate to the semiconductor optical device and the manufacture method thereof that have been equipped with electrode at wave guide ridge (waveguide ridge) top.

Background technology

In recent years, as realize semiconductor laser luminous from the blue region to the ultraviolet range for the densification of CD is necessary, the prevailing research and development of the nitride-based semiconductor laser device that used nitride-based III-V compound semiconductors such as AlGaInN, and practicability.

Make compound semiconductor crystalline growth and forming on the GaN substrate at such bluish violet LD (following laser diode note is made LD).

In representational compound semiconductor, the III-V compound semiconductor that III family element and V group element are bonded together is arranged, be bonded together by a plurality of III family's atoms or V group atom, can obtain having the mixed crystal compound semiconductor of various ratio of components.As the compound semiconductor that is used in bluish violet LD, GaN, GaPN, GaNAs, InGaN, AlGaN etc. are for example arranged.

The LD of waveguide ridge is provided with electrode layer at the top of wave guide ridge usually.In covering the dielectric film of wave guide ridge, opening is set, carries out this electrode layer and being connected as the contact layer of the superiors of wave guide ridge through this opening at the wave guide ridge top.Usually, this dielectric film for example uses silicon oxide film or silicon nitride film.

The material of employed contact layer in existing red LD is for example among the GaAs etc., because contact resistance is lower, so use as electrode material with Ti always.Because Ti has good close attachment to silicon oxide film or silicon nitride film, so not peeling off of electrode layer is a problem especially.

In addition, employed Etching mask also forms the dielectric film that covers wave guide ridge with the method for moving away from when being applied in the formation wave guide ridge, and opening also forms with identical operation.In moving away from method, owing to cave in along the surface formation of contact layer at bonding part with contact layer with the Etching mask of contact layer bonding, so the part at the dielectric film of moving away from back covering wave guide ridge is also residual in the part of this depression, have only this residual dielectric film partly to cover the surface of contact layer, thereby electrode layer is long-pending littler than all surfaces of contact layer with the contact area of contact layer.

The material of employed contact layer in existing red LD, for example among the GaAs etc. because contact resistance is lower, thus with the contact area of moving away from the method generation reduce contact resistance is increased greatly, the rising of the operating voltage of LD be there is no big influence.

Yet, under the situation of bluish violet LD, the material that is used in contact layer is GaN etc., because the contact resistance of material is higher, the contact resistance of Ti and GaN is higher, so can not use Ti as electrode material,, can't obtain good close attachment to silicon oxide film or silicon nitride film though used Ni, Pt, Au etc.

Therefore, peel off between electrode layer and dielectric film sometimes, electrode layer and contact layer are peeled off or the like thus, and reliability is reduced.

Also according to circumstances because of the minimizing of the contact area of electrode and contact layer, improved the contact resistance of electrode and contact layer, the result can improve the operating voltage of bluish violet LD.

To this, can prevent that the known example of the semiconductor Laser device of peeling off of pad electrode or electrode is as follows thereby disclose the close attachment raising that makes dielectric film and pad electrode or electrode.

In nitride semiconductor Laser device, disclose as follows.

(Indium-Tin-Oxides: film tin indium oxide) forms the p electrode 230 of Ni class thereon to form ITO on the dielectric film 220 imbedding that spine is imbedded.Owing to ITO film 260 is arranged imbedding to be situated between on the interface of dielectric film 220 and p electrode 230, so that both close attachment become is good.P electrode 230 has by evaporation or sputter makes Ni film 231, Au film 232 and the ITO film 260 Ni/Au/ITO structure of film forming successively, perhaps makes Ni film and the ITO film Ni/ITO structure of film forming successively by evaporation or sputter.Then, the p pad electrode has by evaporation or sputter makes ITO film 251, Pt film 252 and the Au film 253 ITO/Pt/Au structure of film forming successively, (for example, with reference to patent documentation 1 [0055]～[0057] section and Fig. 3) is situated between on the interface of p electrode 230 and p pad electrode 250 ITO film 233,251 arranged.

In another known example, the p pad electrode that cleavage fissure is good, caking property is good when forming the resonance face by cleavage (cleave) is disclosed in nitride semiconductor Laser device.This p pad electrode is made of metallic the 1st thin layer and metallic the 2nd thin layer, wherein, the 1st thin layer covers whole p electrode with the length identical with the bar length of ridged shape and forms, and the 2nd thin layer forms with the length shorter than bar length on the 1st thin layer.The material of the 1st thin layer is made Ni, Ti, Cr, W and Pt by note, and the 2nd thin layer is made Au and Al (for example, with reference to patent documentation 2 [0007], [0016]～[0021] section, Fig. 1 and Fig. 2) by note.

In another known example, disclose in the ridge type semiconductor laser, form SiO in the mode that covers ridge ₂Dielectric film is being removed SiO selectively ₂Dielectric film and form Ti/Pt/Au anode electrode (for example, with reference to patent documentation 3 [0041], [0042] section and Fig. 2) on the contact layer that exposes.

[patent documentation 1] Japan Patent Publication Laid-Open 2005-354049 communique

[patent documentation 2] Japan Patent Publication Laid-Open 2000-22272 communique

[patent documentation 3] Japan Patent Publication Laid-Open 2005-166998 communique

Spine at the conventional semiconductor laser, on the interface of imbedding dielectric film and p electrode, be situated between and the ITO film arranged to improve both close attachment, but, has the Ni/Au/ITO structure as the p electrode in order to improve and to have the close attachment (adhesion) of the p pad electrode of ITO/Pt/Au structure.

The control difficulty of the ratio of component of ITO is difficult to obtain the ITO that rate of finished products is high and have stability characteristic (quality), often can't stably guarantee low contact resistance.

Thereby, being difficult to stably make the device of characteristic unanimity with high finished product rate, contact resistance can uprise in addition, and the result has improved the operating voltage of bluish violet LD.

Summary of the invention

The present invention carries out in order to address the above problem, its the 1st purpose is, by constituting the semiconductor optical device of peeling off and can suppress the rising of contact resistance that can prevent metal electrode layer, a kind of reliability height, semiconductor optical device that operating voltage is low are provided, its the 2nd purpose is, a kind of manufacture method that is used for coming with simple operation fabrication reliability height, semiconductor optical device that operating voltage is low is provided.

Semiconductor optical device of the present invention possesses: substrate; Semiconductor stacked structure is included in the 2nd semiconductor layer of the 1st semiconductor layer, active layer and the 2nd conduction type of the 1st conduction type that stacks gradually on this substrate; Wave guide ridge is formed by a part of semiconductor layer of the 2nd semiconductor layer that comprises this semiconductor stacked structure; The 1st dielectric film has peristome accordingly with the top of this wave guide ridge, covers the sidewall of wave guide ridge; The close attachment layer is provided on the 1st dielectric film with getting rid of peristome, and comprises the 1st close attachment film that any the nitride by any metal of Ti, TiW, Nb, Ta, Cr, Mo or these metals forms; And metal electrode layer, be provided on this close attachment layer, and through the peristome close attachment on the 2nd semiconductor layer at the top of wave guide ridge.

In semiconductor optical device of the present invention, metal electrode layer through the peristome close attachment on the 2nd semiconductor layer at wave guide ridge top, and the part of this metal electrode layer through with the 1st dielectric film securely the close attachment layer of close attachment be cemented in securely on the 1st dielectric film.Therefore, can prevent peeling off of metal electrode film, and because the contact resistance of metal electrode layer is low, so can make the operating voltage of semiconductor optical device keep very lowly.

Description of drawings

Fig. 1 is the profile of the semiconductor LD of one embodiment of the present invention.

Fig. 2 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Fig. 3 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Fig. 4 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Fig. 5 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Fig. 6 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Fig. 7 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Fig. 8 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Fig. 9 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Figure 10 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Figure 11 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Figure 12 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Figure 13 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

Figure 14 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression second half conductor LD of the present invention.

Figure 15 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression second half conductor LD of the present invention.

Figure 16 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression second half conductor LD of the present invention.

Figure 17 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression another semiconductor LD of the present invention.

Figure 18 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression another semiconductor LD of the present invention.

Embodiment

In the following embodiments,, be that example describes for example, but be not limited to bluish violet LD with bluish violet LD as semiconductor optical device, be applied to red LD etc. all semiconductor optical devices also can receive same effect.Therefore, each material that forms semiconductor stacked structure is not limited to nitride-based semiconductor, also comprises InP class material or GaAs class material.In addition, substrate is not limited to the GaN substrate, for insulated substrates such as other semiconductor substrate such as InP, GaAs, Si, SiC or sapphire substrate also can.

Execution mode 1

Fig. 1 is the profile of the semiconductor LD of one embodiment of the present invention.Have again, in each figure, part that identical symbolic representation is identical or suitable part.

In Fig. 1, this LD10 is the bluish violet LD of waveguide ridge, n type GaN substrate 12 (below, " n type " note is made " n-", and with " p type " note work " p-", particularly will be not doping not unadulterated situation note is made " i-") an interarea be to form the resilient coating 14 that forms by n-GaN on the Ga face, on this resilient coating 14, form for example 1n-covering 16 of conduct the 1st semiconductor layer that forms by n-AlGaN, 2n-covering 18, with 3n-covering (cladding layer) 20, on this 3n-covering 20, stack gradually n side-light guides (light guiding) layer 22 that forms by n-GaN, the n side SCH that forms by InGaN (Separate Confinement Heterostructure: separate limitation formula heterostructure) layer 24 and active layer 26.

P-covering 34 that on this active layer 26, stacks gradually p sidelight conducting shell 32 that the p side sch layer 28 that is formed by InGaN, the electronics that is formed by p-AlGaN stop (barrier) layer 30, formed by p-GaN, forms by p-AlGaN and the contact layer 36 that forms by p-GaN.As the 2nd semiconductor layer, in the present embodiment, comprise p-covering 34 and contact layer 36.But the 2nd semiconductor layer is also all irrelevant more than 1 layer or 3 layers according to circumstances.

In the present embodiment, semiconductor stacked structure 37 for example comprises: resilient coating 14,1n-covering 16,2n-covering 18,3n-covering 20, n sidelight conducting shell 22, n side sch layer 24, active layer 26, p side sch layer 28, electronic barrier layer 30, p sidelight conducting shell 32, p-covering 34 and contact layer 36.

By forming the raceway groove 38 as recess in contact layer 36 and p-covering 34, thereby the part of the p-covering 34 of the contact layer 36 and the upper surface side of joining with contact layer 36 forms wave guide ridge 40.

The middle body that wave guide ridge 40 is provided in the Width of the cleaved facets that becomes the resonator of LD10 end face extends between the both ends of the surface that become the resonator end face.This wave guide ridge 40 in the size of its long side direction, be that resonator length is 1000 μ m, with the ridge width of the direction of its long side direction quadrature for number μ m～tens of μ m, for example be 1.5 μ m in the present embodiment.

In addition, the width of raceway groove is 10 μ m in the present embodiment.For example is electrode pad pedestal (platform) 42 through raceway groove 38 in the platform shape portion that two outsides of wave guide ridge 40 form.

In addition, the height of wave guide ridge 40, the height of promptly starting at from the bottom surface of raceway groove 38 for example are 0.5 μ m.

Comprising the two sides of raceway groove 38 of sidewall of the sidewall of wave guide ridge 40 and electrode pad pedestal 42 and the 1st silicon insulating film 44 that the bottom surface is used as the 1st dielectric film covers.The 1st silicon insulating film 44 for example is the SiO of 200nm by thickness ₂Film forms.

On the 1st silicon insulating film 44, cover the 1st silicon insulating film 44 ground on the two sides and bottom surface of the raceway groove 38 of the sidewall of sidewall that comprises wave guide ridge 40 and electrode pad pedestal 42, set close attachment layer 45.

Close attachment layer 45 comprises: close attachment on the 1st silicon insulating film 44 configuration thickness be 30nm be the 2nd close attachment film 45b of 40nm as the 1st close attachment film 45a of Ti film and the bed thickness that on the 1st close attachment film 45a, forms as the Au film.

As the 1st close attachment film 45a, except that Ti, also can form by any nitride of any metal of TiW, Nb, Ta, Cr and Mo or these metals, the 2nd close attachment film 45b is formed by the metal that contains Au.

Have, the 1st silicon insulating film 44 and close attachment layer 45 do not form at the upper surface of contact layer 36 again, and the peristome 44a that the 1st silicon insulating film 44 and close attachment layer 45 are had makes the entire upper surface of contact layer 36 expose (expose).

At the upper surface of contact layer 36, configuration is joined with contact layer 36 and the p lateral electrode 46 as metal electrode layer that is electrically connected.P lateral electrode 46 usefulness vacuum vapour depositions have: from the AuGa/Pt/Au structure that the Au film of platinum (Pt) film of the AuGa film of tight adhesion layer 45 sides by stacking gradually bed thickness 60nm, bed thickness 30nm and bed thickness 80nm forms, perhaps have the Au/Pt/Au structure that forms from the Au film of platinum (Pt) film of the Au film of tight adhesion layer 45 sides by stacking gradually bed thickness 60nm, bed thickness 30nm and bed thickness 80nm.

The upper surface close attachment of this p lateral electrode 46 and contact layer 36, its part are also extended on the close attachment layer 45 that forms on the part of the sidewall of wave guide ridge 40 and raceway groove 38 bottoms.

The 1st close attachment film 45a and the SiO that constitutes by above-mentioned material ₂The close attachment of the 1st silicon insulating film 44 of film is good, in addition, because the close attachment of the 1st close attachment film 45a and the 2nd close attachment film 45b is also good, so close attachment layer 45 and the 1st silicon insulating film 44 close attachment securely.

Because p lateral electrode 46 is the structure from the AuGa film/Pt film/Au film of lower layer side, thus the 2nd close attachment film 45b (Au film) of close attachment layer 45 and p lateral electrode 46, because of the metal film of same Au class join so close attachment securely.Thereby p lateral electrode 46 is difficult to cause peeling off of p lateral electrode 46 through close attachment layer 45 and the 1st silicon insulating film 44 close attachment securely.Therefore, the reliability of LD10 increases.

And then, because p lateral electrode 46 is made of the such metal film of AuGa film/Pt film/Au film, so resistance value is low and can reduce contact resistance with contact layer 36.Thereby, can suppress the rising of the operating voltage of semiconductor LD10.

In addition, close attachment layer 45 is that film forming can stably be carried out by evaporation or sputter by an element or two metal material or its nitride that element constitutes.Therefore, close attachment layer 45 can stably form compared with the ITO film, can guarantee high reliability.

Have, though in the present embodiment, close attachment layer 45 is by constituting as the 1st close attachment film 45a of Ti film with as the 2nd close attachment film 45b of Au film again, only is made of the 1st close attachment film 45a that also it doesn't matter.

In addition, on close attachment layer 45 surface on electrode pad pedestal 42 sides on the upper surface that is disposed at electrode pad pedestal 42 and in the raceway groove 38 and the part of raceway groove 38 bottoms, for example set by SiO ₂The 2nd silicon insulating film 48 that forms.

On the surface of p lateral electrode 46, set pad electrode 50 with p lateral electrode 46 close attachment.This electrode pad 50 is provided on p lateral electrode the 46, the 1st silicon insulating film 44 and the 2nd silicon insulating film 48 of raceway groove 38 inside of both sides, and then extends on the 2nd silicon insulating film 48 that is provided in electrode pad pedestal 42 upper surfaces.Pad electrode 50 stacks gradually Ti, Pt and Au from lower layer side and is configured.

At the back side of n-GaN substrate 12, set with vacuum vapour deposition by stacking gradually the n lateral electrode 52 that Ti and Au film form.

In this LD10,, mix silicon (Si) as n type impurity; As p type impurity, mix magnesium (Mg).

The bed thickness of n-GaN substrate 12 is about 500-700nm.In addition, the bed thickness of resilient coating 14 is about 1 μ m.The bed thickness of 1n-covering 16 is about 400nm, for example by n-Al _0.07Ga _0.93N forms, and the bed thickness of 2n-covering 18 is about 1000nm, for example by n-Al _0.045Ga _0.955N forms, and the bed thickness of 3n-covering 20 is about 300nm, for example by n-Al _0.015Ga _0.985The N layer forms.

The bed thickness of n sidelight conducting shell 22 for example is 80nm.The thickness of n side sch layer 24 is 30nm, by i-In _0.02Ga _0.98N forms.

Active layer 26 has the double quantum well structure that is made of following each layer: join with n side sch layer 24 and set by i-In _0.12Ga _0.88The bed thickness that N constitutes be 5nm trap layer 26a, on trap layer 26a, set by i-In _0.02Ga _0.98The bed thickness that N constitutes be the barrier layer 26b of 8nm and on the 26b of this barrier layer, set by i-In _0.12Ga _0.88The bed thickness that N constitutes is the trap layer 26c of 5nm.

On the trap layer 26c of active layer 26, join with it and the thickness of the p side sch layer 28 that sets is 30nm, by i-In _0.02Ga _0.98N forms.

The bed thickness of electronic barrier layer 30 is about 20nm, by p-Al _0.2Ga _0.8N forms.The bed thickness of p sidelight conducting shell 32 is 100nm, and the bed thickness of p-covering 34 is about 500nm, by p-Al _0.07Ga _0.93N forms, and the bed thickness of contact layer 36 is 20nm.

The manufacture method of LD10 then, is described.

Fig. 2～Figure 13 is that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of expression semiconductor LD of the present invention.

In this manufacturing process, because n-GaN substrate 12 and each layer until p sidelight conducting shell 32 that stacks gradually thereon do not have special the variation in manufacturing process, so from each figure, dispense, for than a part that comprises p sidelight conducting shell 32 at interior layer each layer on upper strata more, show its section.

At first, by heat cleaning etc. the surface is being carried out on the GaN substrate 12 that cleans for example under 1000 ℃ growth temperature, forming n-GaN layer in advance as resilient coating 14 with organometallic chemistry vapor growth method (below, be called mocvd method).

Then, form n-Al successively as 1n-covering 16 _0.07Ga _0.93The N layer, as the n-Al of 2n-covering 18 _0.045Ga _0.955The N layer, as the n-Al of the 3rd n-covering 20 _0.015Ga _0.985The N layer, as the i-In of n sidelight conducting shell 22 _0.02Ga _0.98The N layer, as the i-In of n side sch layer 24 _0.02Ga _0.98The N layer, and form the i-In that constitutes active layer 26 thereon successively as trap layer 26a _0.12Ga _0.88The N layer, as the i-In of barrier layer 26b _0.02Ga _0.98N layer and as the i-In of trap layer 26c _0.12Ga _0.88N.

Then, on active layer 26, stack gradually i-In as p side sch layer 28 _0.02Ga _0.98The N layer, as the p-Al of electronic barrier layer 30 _0.2Ga _0.8The N layer, as the p-Al of p sidelight conducting shell 32 _0.2Ga _0.8N layer 70, as the p-Al of p-covering 34 _0.07Ga _0.93N layer 72 and as the p-GaN layer 74 of contact layer 36 forms the wafer with such semiconductor stacked structure 37.

Fig. 2 shows the result of this operation.

Then, with reference to Fig. 3, on whole of the wafer that crystal growth has finished, the coating resist, utilize the photomechanical process operation, keep resist at the part 76a corresponding with the shape of wave guide ridge 40, form the resist of having removed the part 76b corresponding with the shape of raceway groove 38, as the resist figure 76 of the 1st resist figure.This result is Fig. 3.In the present embodiment, the width of the part 76a corresponding with the shape of wave guide ridge 40 is 1.5 μ m, and the width of the part 76b corresponding with the shape of raceway groove 38 is 10 μ m.

Then, with reference to Fig. 4, be mask with resist figure 76, utilize RIE (Reactive IonEtching: reactive ion etching), etching p-GaN layer 74 and the p-Al that joins with this p-GaN74 _0.07Ga _0.93The part of the upper surface side of N layer 72 keeps p-Al _0.07Ga _0.93The part of N layer 72 forms the raceway groove 38 as the bottom.The etching depth a of this moment is a=500nm (0.5 μ m) in the present embodiment.By formation raceway groove 38, thereby form wave guide ridge 40 and electrode pad pedestal 42.Fig. 4 shows the result of this operation.

Then, with reference to Fig. 5, remove employed resist figure 76 in formerly the etching with organic solvent etc.The degree of depth of the raceway groove 38 of this moment, be that the height of wave guide ridge 40 equals etching depth a, be 500nm (0.5 μ m).In addition, in this operation, also become the part of electrode pad pedestal 42.Fig. 5 shows the result of this operation.

Then, with reference to Fig. 6, use CVD method, vacuum vapour deposition or sputtering method etc. on whole of wafer, for example forming thickness is the SiO that becomes the 1st silicon insulating film 44 of conduct the 1st dielectric film of 0.2 μ m ₂Film 78.And then, use and SiO ₂Film 78 same film build methods cover SiO ₂Film 78, forming by thickness is the Ti film of conduct the 1st close attachment film 45a of 30nm and the close attachment layer 45 that Au film that the bed thickness that forms on this Ti film is conduct the 2nd close attachment film 45b of 40nm constitutes.

Have again, in following figure, also to Ti film and Au film are described as the situation of close attachment layer 45 altogether.

SiO ₂The surface of the upper surface of film 78 and close attachment layer 45 covering wave guide ridge 40, the inside of raceway groove 38 and the upper surface of electrode pad pedestal 42.Fig. 6 shows the result of this operation.

Then,, on whole of wafer, apply photoresist, form resist film 80, make that the thickness b of the resist film in the raceway groove 38 is thicker than the thickness c of the resist film at the top of the top of wave guide ridge 40 and electrode pad pedestal 42 with reference to Fig. 7.For example, form resist film 80, make about b=0.8 μ m, c=0.4 μ m.

In Fig. 7, record, the surface depression of the resist film 80 at the top of the surface ratio wave guide ridge 40 of the resist film 80 on the raceway groove 38 and the top of electrode pad pedestal 42, as long as but the surface of resist film evenly is formed flatly, nature can satisfy b＞c.

But, as Fig. 7 describes, even the surface of the resist film 80 at the top of the surface ratio wave guide ridge 40 of the resist film 80 on the raceway groove 38 and the top of electrode pad pedestal 42 depression, as long as satisfy b＞c, how all irrelevant the shape on the surface of resist film 80 is.

Usually apply photoresist with spin-coating method.That is,, make the wafer rotation, can form the thickness of homogeneous by the resist that on wafer, instils.

Then, revolution and rotational time when viscosity by making photoresist and dropped amount, wafer rotation are suitable value, the thickness of may command resist film.

As shown in Figure 7, form under the situation of step difference or recess on the surface of wafer, outstanding part, promptly at this moment in top and the top thin of electrode pad pedestal 42 and the part of depression of wave guide ridge 40, thicken at the position of raceway groove 38 at this moment, its thickness extent is subjected to the viscosity influence of photoresist.

Under the situation of as shown in Figure 7 wafer, at the top of bottom that makes raceway groove 38 and wave guide ridge 40 or the SiO at the top of electrode pad pedestal 42 ₂Under the situation that the thickness of film 78 equates, if viscosity is little, then the relation of the thickness c of the resist film 80 at the top of the top of the thickness b of the etching depth a of raceway groove 38, the resist film 80 in the raceway groove 38 and wave guide ridge 40 or electrode pad pedestal 42 approaches b=c+a.This means the surface general planar equably that can make resist film 80.

In addition, on the surface of resist film 80 and anisotropically general planar, under the situation of the surface of the position of raceway groove 38 resist depression, increase as the viscosity of photoresist, then approach b=c.This means the top of the thickness of the resist film 80 on the raceway groove 38 and wave guide ridge 40 or electrode pad pedestal 42 the top resist film 80 thickness about equally.

In addition, on the surface of resist film 80 and anisotropically general planar, under the situation of the surface of the position of raceway groove 38 resist depression, as long as the viscosity of resist is not too low, b＞c then, promptly the thickness of the resist film 80 at the top of the top of the Film Thickness Ratio wave guide ridge 40 of the resist film 80 of raceway groove 38 parts or electrode pad pedestal 42 is thick.

Like this, revolution when viscosity by suitably setting resist and wafer rotation, the pass of thickness c of resist film 80 that can set the top of the top of the thickness b of resist film 80 of raceway groove 38 parts and wave guide ridge 40 or electrode pad pedestal 42 is desirable relation, i.e. b＞c.Fig. 7 shows the result of this operation.

Then, with reference to Fig. 8, remove resist equably from the surface of resist film 80, the resist film 80 that keeps raceway groove 38 on one side, remove on one side the resist film 80 at the top of the top of wave guide ridge 40 and electrode pad pedestal 42 fully, form the resist figure 82 that the top of the top that makes wave guide ridge 40 and electrode pad pedestal 42 exposes.

For example, by means of having used O ₂The dry etching of plasma, expose fully regulation the thickness part, be the close attachment layer 45 at the top of the top of wave guide ridge 40 and electrode pad pedestal 42, and in raceway groove 38 surface etch of resist film 80 be than the upper surface of p-GaN layer 74 residual high degree, for example be the amount of 400nm in the present embodiment.

For resist film 80, the thickness of the resist film 80 on raceway groove 38 forms about 800nm, and in addition, the thickness of the resist film 80 at the top of the top of wave guide ridge 40 and electrode pad pedestal 42 forms about 400nm.Therefore, if remove the resist of 400nm by etching from the surface of resist film 80, then the resist film 80 at the top of the top of wave guide ridge 40 and electrode pad pedestal 42 is removed, and the upper surface of close attachment layer 45 is exposed, and the surface of the resist film on the raceway groove 38 80 is formed on and compares SiO ₂Half high position of the thickness of film 78, this residual resist film becomes the resist figure 82 as the 2nd resist figure.

The stopping of etching under the situation of carrying out etching from the surface of resist film 80 equably correctly carries out as following.

By means of having used O ₂The control of the etch amount of the dry etching of plasma when removing resist film can be carried out as follows.

By means of having used O ₂The dry etching of plasma when removing resist film, O ₂Oxygen in the plasma and the carbon in the photoresist react and the CO that generates is excited in plasma, send the exciting light that wavelength is 451nm.On one side this excites light intensity from the visual observation of etching chamber, Yi Bian carry out dry etching.

If carry out dry etching, remove the resist at the top of the top of wave guide ridge 40 and electrode pad pedestal 42, to reduce the surface area as the resist film 80 of etching object, then the light intensity that excites of wavelength 451nm reduces.

As long as the reduction of this luminous intensity of observation stops period with what determine etching.Thereby, can control stopping of etching with good precision.

Certainly, actually, because the thickness of the resist film 80 at the top of the height of wave guide ridge 40, the top of wave guide ridge 40 and electrode pad pedestal 42 and the etching speed of photoresist etc. are distribution in wafer face, so on whole of wafer,, stop again etc. after the certain hour etching that much less also must consider also will continue to stipulate from the moment of the reduction that detects luminous intensity for the resist film 80 at the top of the top of removing wave guide ridge 40 reliably and electrode pad pedestal 42.

In addition, as another etching stopping detection method constantly, the method below also having.

That is, in dry etching,, make light, the incident of for example laser of single wavelength from the position in opposite directions of wafer, and make it in the top of wave guide ridge 40 and the top reflection of electrode pad pedestal 42 towards the top of wave guide ridge 40 and the top of electrode pad pedestal 42.

This catoptrical luminous intensity changes with the remaining thickness of the resist film 80 at the top of top that is present in wave guide ridge 40 and electrode pad pedestal 42.By this catoptrical luminous intensity of observation, can control the remaining thickness of resist film 80 at the top of the top that is present in wave guide ridge 40 and electrode pad pedestal 42, become for 0 the moment at this remaining thickness, can send the instruction of etching stopping.

No matter use which kind of method in these methods, owing to can detect the etch amount of resist film 80 on one side with good precision, on one side carry out etching, so removed the resist figure 82 of resist film 80 at the top of the top of wave guide ridge 40 and electrode pad pedestal 42 resist film in having can be formed in raceway groove 38 residual the time.Fig. 8 shows the result of this operation.

Then, with reference to Fig. 9, be mask with resist figure 82, the close attachment layer 45 that exposes of etching equably from the surface remains in the formed close attachment layer 45 in side and bottom and the SiO of raceway groove 38 ₂ Film 78 is removed fully at the top of wave guide ridge 40 and the formed close attachment layer 45 in top and the SiO of electrode pad pedestal 42 simultaneously ₂Film 78.At the top of wave guide ridge 40 at close attachment layer 45 and SiO ₂Form peristome 44a on the film 78 reliably.

The etching of this moment can be used dry etching or wet etchings such as reactive ion etching method.

The etching of close attachment layer 45, in the present embodiment, the 1st close attachment film 45a is formed by Ti, and the 2nd close attachment film 45b is formed by Au in addition.Thereby the 1st close attachment film 45a uses CF under the situation of dry etching ₄The gas that gas etc. are fluorine-containing, under the situation of wet etching with buffered hydrofluoric acid etc.In addition, the 2nd close attachment film 45b uses Ar gas under the situation of dry etching, is that etching agent carries out etching with the chloroazotic acid under the situation of wet etching.

In addition, SiO ₂Use CF under the situation that is etched in dry etching of film 78 ₄Fluorine-containing gas such as gas is to SiO ₂Film 78 carries out, and is that etching agent carries out with buffered hydrofluoric acid etc. under the situation of wet etching.

At close attachment layer 45 and SiO ₂Under the situation of the etching of film 78, also can come the etch amount of precise control in the following method.

For example, in the etching end of close attachment layer 45, use CF ₄Fluorine-containing gas such as gas is to SiO ₂Film 78 carries out under the situation of dry etching, by SiO ₂Si in the film 78 and the F in the etching gas produce SiF ₂, by observing from SiF ₂The light intensity of the about 390nm of wavelength that sends, thus according to the variation may observe of luminous intensity at the top of wave guide ridge 40 and the formed SiO in top of electrode pad pedestal 42 ₂ Film 78 has disappeared, is confirming can to stop etching after this light intensity reduces.

In addition, finish in the etching of close attachment layer 45, with buffered hydrofluoric acid etc. to SiO ₂Film 78 carries out under the situation of wet etching, at the top of wave guide ridge 40 and the formed SiO in top of electrode pad pedestal 42 ₂ Film 78 from the laser of the incident of the position in opposite directions single wavelength of wafer surface, by observation station's intensity of light reflected, can be measured at the top of wave guide ridge 40 and the remaining SiO in top of electrode pad pedestal 42 ₂The thickness of film 78.Confirming this measured SiO ₂The remaining thickness of film 78 has been can stop etching after 0.

Fig. 9 shows the result of this operation.

Then, with reference to Figure 10,, remove resist figure 82 by means of the wet etching that has used organic solvent.Figure 10 shows the result of this operation.

Then, with reference to Figure 11, form p lateral electrode 46 at the top of wave guide ridge 40.

At first, on whole of wafer, apply resist, the superiors that form wave guide ridge 40 by the photomechanical process operation are the upper surface of p-GaN layer 74, resist figure (not shown) behind a part of opening of the sidewall of wave guide ridge 40 and raceway groove 38 bottoms, on this resist figure, for example stack gradually the AuGa film of bed thickness 60nm with vacuum vapour deposition, the Au film of the platinum of bed thickness 30nm (Pt) film and bed thickness 80nm, perhaps stack gradually the Au film of bed thickness 60nm, the Au film of the platinum of bed thickness 30nm (Pt) film and bed thickness 80nm, behind the metal electrode layer that has formed film forming like this, by remove resist film with (1ift off) method of moving away from and on this resist film formed metal electrode layer, form p lateral electrode 46.

Because the upper surface of the p-GaN layer 74 at the top of wave guide ridge 40 is not by SiO ₂Film 78 mulched grounds expose entire upper surface by peristome 44a, so the contact area of this p lateral electrode 46 and p-GaN layer 74 can not reduce when forming peristome 44a.

Thereby, can prevent that contact resistance from increasing with the minimizing of p lateral electrode 46 with the contact area of p-GaN layer 74.

In addition, because the 1st close attachment film 45a and SiO of close attachment layer 45 ₂The close attachment of film 78 is good, and the close attachment of the 1st close attachment film 45a and the 2nd close attachment film 45b is also good in addition, so close attachment layer 45 and SiO ₂Film 78 is close attachment securely.And then, because p lateral electrode 46 has from the structure of lower layer side for AuGa film/Pt film/Au film, join so the 2nd close attachment film 45b (Au film) of close attachment layer 45 and p lateral electrode 46 are metal films of same Au class, thereby close attachment together securely.

Thereby, p lateral electrode 46 through close attachment layer 45 securely with SiO ₂Film 78 close attachment are difficult to cause peeling off of p lateral electrode 46.And then, because p lateral electrode 46 has by the so film formed structure of metal of AuGa film/Pt film/Au film, so resistance value is low and can reduce contact resistance with p-GaN layer 74.

Figure 11 shows the result of this operation.

Then, with reference to Figure 12, form the 2nd silicon insulating film 48.

At first, on whole of wafer, apply resist, being formed on the part of removing on the p lateral electrode 46, being the resist figure (not shown) that electrode pad pedestal 42 sides and the part of raceway groove 38 bottoms in electrode pad pedestal 42 upper surfaces and the raceway groove 38 has opening by the photomechanical process operation, is the SiO of 100nm with vacuum vapour deposition formation thickness for example on whole of wafer ₂Film, with the method for moving away from remove formed resist film on the p lateral electrode 46 and on this resist film formed SiO ₂Film, thus form by SiO ₂Formed the 2nd silicon insulating film 48 of film.

Figure 12 shows the result of this operation.

At last, with reference to Figure 13, on p lateral electrode 46, raceway groove 38 and the 2nd silicon insulating film 48,, form pad electrode 50 with the stacked metal film that constitutes by Ti, Pt and Au of vacuum vapour deposition.

Variation 1

Figure 14～16th represents that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of second half conductor LD of the present invention.

Among each manufacturing process of the semiconductor LD that formerly illustrated, the operation of Fig. 1 to Fig. 6 also is identical in this variation.The operation of use Figure 14～Figure 16 replaces the operation of previously described Fig. 7 and Fig. 8.

Formerly in the operation of Fig. 6, the surface of the upper surface of wave guide ridge 40, raceway groove 38 inside and the upper surface of electrode pad pedestal 42 are by SiO ₂Film 78 covers, and then covers SiO ₂It is the Ti film of conduct the 1st close attachment film 45a of 30nm and the close attachment layer 45 that Au film that the bed thickness that forms on this Ti film is conduct the 2nd close attachment film 45b of 40nm constitutes that film 78 ground have formed by thickness, then with reference to Figure 14, coating is the photoresist of main component with phenolic resins on whole of wafer, form resist film 90, this resist film 90 with the raceway groove 38 of wave guide ridge 40 adjacency in, there is the roughly the same height of upper surface with the close attachment layer 45 at wave guide ridge 40 tops on the surface of resist film 90.

In the present embodiment, the bed thickness d of the resist film 90 on the raceway groove 38, promptly be 500nm (0.5 μ m) from height d on surface to the surface of resist film 90 of the close attachment layer 45 that the bottom disposed of raceway groove 38.

At this moment, the formation method of having controlled the resist film 80 among manufacture method and the Fig. 7 that illustrated of resist film 90 of bed thickness d of the resist film 90 on the raceway groove 38 exactly similarly, revolution when viscosity by suitably setting resist and wafer rotation can be set at desirable value with the thickness d of the resist film 90 in raceway groove 38 parts.Figure 14 shows the result of this operation.

Then, with reference to Figure 15, to resist film 90 photomechanical process operation, the residual resist film 90 of a part on the close attachment layer 45 of the bottom surface of raceway groove 38, in raceway groove 38, between the close attachment layer 45 on the sidewall of resist film 90 and wave guide ridge 40 and between the close attachment layer 45 on the sidewall of resist film 90 and electrode pad pedestal 42, set the interval e of regulation and isolate, and form the resist figure 92 that the surface of close attachment layer 45 at the top of the top that makes wave guide ridge 40 and electrode pad pedestal 42 exposes equably.Figure 15 shows the result of this operation.

Then, with reference to Figure 16, by wafer is heat-treated, for example in atmosphere, keep 140 ℃ temperature to heat 10 minutes, make the photoresist liquidation, in raceway groove 38, by make between the close attachment layer 45 on the sidewall of resist film 90 and wave guide ridge 40 and the interval e of the regulation between the close attachment layer 45 on the sidewall of resist film 90 and electrode pad pedestal 42 disappear, promptly by make on the sidewall in resist film and the raceway groove 38 close attachment layer 45 close attachment together, thereby be formed on the resist figure 82 that the top of the top that makes wave guide ridge 40 when keeping resist film in the raceway groove 38 and electrode pad pedestal 42 exposes.

The height and position f on the resist film surface that is disposed in the raceway groove 38 of resist figure 82 is set to surperficial low than the close attachment layer 45 at wave guide ridge 40 tops and electrode pad pedestal 42 tops, than the high residual degree of upper surface of the p-GaN layer 74 at wave guide ridge 40 tops and electrode pad pedestal 42 tops.In the present embodiment, be set at f=400nm.

Then, for this reason, the heat treated front and back in this operation, do not have under the situation of change in volume at the supposition resist film, the sectional area of supposing the resist figure 92 in the section of Figure 15 and Figure 16 equates with the sectional area of resist figure 82, must setting interval e, so that obtain desirable f value.

Have again, in Figure 15, the interval e of resist figure 92 is set in the both sides of the resist film in the raceway groove 38, if but set at interval e so that obtain desirable f value, even then the interval is arranged on that one-sided also it doesn't matter.Figure 16 shows the result of this operation.

The later operation of the later operation of this operation and the Fig. 9 that had before illustrated is identical.

Variation 2

Figure 17～18th represents that figure cuts open in the office of semiconductor LD of each manufacturing process of the manufacture method of second half conductor LD of the present invention.

Among each manufacturing process of the semiconductor LD that formerly illustrated, the operation of Fig. 1 to Fig. 4 also is identical in this variation.The operation of use Figure 17～Figure 18 replaces the operation of previously described Fig. 5 to Figure 10.

Formerly below the operation of Fig. 4, still be retained in employed resist figure 76 in the previous etching, use CVD method, vacuum vapour deposition or sputtering method etc. on whole of wafer, for example forming thickness is the SiO that becomes the 1st silicon insulating film 44 of conduct the 1st dielectric film of 0.2 μ m ₂Film 78.And then, utilize and SiO ₂Film 78 same manufacture methods cover SiO ₂Film 78, forming by thickness is the Ti film of conduct the 1st close attachment film 45a of 30nm and the close attachment layer 45 that Au film that the bed thickness that forms on this Ti film is conduct the 2nd close attachment film 45b of 40nm constitutes.SiO ₂ Film 78 and close attachment layer 45 cover resist film on the upper surface of wave guide ridge 40, on the surface of the inside of raceway groove 38 and the resist film of the upper surface of electrode pad pedestal 42.Figure 17 shows the result of this operation.

Then, remove resist figure 76 by the wet etching that has used organic solvent etc.This moment is residual Si O on the surface of the inside of raceway groove 38 ₂ Film 78 and close attachment layer 45, but on the upper surface of wave guide ridge 40 and electrode pad pedestal 42 on the formed SiO of resist film upper surface ₂Film 78 and close attachment layer 45 are removed with resist film, are exposed to formed p-GaN layer 74 on wave guide ridge 40 and the electrode pad pedestal 42.

Figure 18 shows its result.The later operation of the later operation of this operation and the Figure 11 that had before illustrated is identical.

In the LD10 of present embodiment 1, comprise on the side and bottom surface of raceway groove 38 of sidewall of wave guide ridge 40, cover the 1st silicon insulating film 44 ground and set close attachment layer 45.Close attachment layer 45 by close attachment on the 1st silicon insulating film 44 and by constituting of being set as the 1st close attachment film 45a of Ti film and the 2nd close attachment film 45b that on the 1st close attachment film 45a, forms as the Au film.

Configuration is joined with contact layer 36 and the p lateral electrode 46 that is electrically connected through peristome 44a on the upper surface of contact layer 36.The part of this p lateral electrode 46 extends to the upper surface of close attachment layer 45 and is configured.

Therefore, p lateral electrode 46 is difficult to cause peeling off of p lateral electrode 46 through close attachment layer 45 and the 1st silicon insulating film 44 close attachment securely.Therefore, improved the reliability of LD10.

And then, because p lateral electrode 46 has the structure that is made of the such metal film of Au film/Pt film/Au film, so resistance value is low and can reduce contact resistance with contact layer 36.Therefore, can suppress the rising of operating voltage.

In addition, close attachment layer 45 is that film forming can stably be carried out with evaporation or sputter by one or two metal material or its nitride that element constitutes.Therefore, the close attachment layer is compared and can stably be formed with the ITO film, can guarantee high reliability.

And then, can constitute the semiconductor LD that operating voltage is low, reliability is high.

In the manufacture method of the LD10 of present embodiment 1, by forming raceway groove 38 on the wafer of semiconductor layer, thereby form wave guide ridge 40 and electrode pad pedestal 42 stacked, on whole of wafer, form SiO ₂Film 78 and by the close attachment layer 45 that constitutes as the 1st close attachment film 45a of Ti film and the 2nd close attachment film 45b that on the 1st close attachment film 45a, forms as the Au film.

Then, on whole of wafer, apply resist, form resist film 80, make the thickness of resist film 80 at top of the top of Film Thickness Ratio wave guide ridge 40 of the resist film on the raceway groove 38 and electrode pad pedestal 42 thick.

Then, remove resist equably from the surface of resist film 80, the resist film 80 of the residual raceway groove 38 in one side, remove on one side the resist film 80 at the top of the top of wave guide ridge 40 and electrode pad pedestal 42, form the resist figure 82 that the top of the top that makes wave guide ridge 40 and electrode pad pedestal 42 exposes.

Then, with resist figure 82 is mask, the close attachment layer 45 that etching exposed equably from the surface remains in the formed close attachment layer 45 in side and bottom of raceway groove 38, removes the close attachment layer 45 and the SiO that form at the top of the top of wave guide ridge 40 and electrode pad pedestal 42 simultaneously ₂ Film 78 is at the top of wave guide ridge 40, at close attachment layer 45 and SiO ₂Form peristome 44a on the film 78 reliably.

Then, after having removed resist figure 82, form p lateral electrode 46 at the top of wave guide ridge 40.

In the manufacture method of this LD, p lateral electrode 46 is difficult to cause peeling off of p lateral electrode 46 through close attachment layer 45 and the 1st silicon insulating film 44 close attachment securely.The semiconductor layer that contacts with p lateral electrode 46 is the p-GaN layer 74 that becomes contact layer 36 at this moment, and its upper surface is by close attachment layer 45 and SiO ₂The peristome 44a of film 78 exposes reliably, does not have SiO on the upper surface of p-GaN layer 74 ₂ Film 78 is residual.Therefore, because p lateral electrode 46 can not reduce with the contact area of contact layer 36, p lateral electrode 46 has the structure that is made of the such metal film of Au film/Pt film/Au film in addition, so that available simple operation produces resistance value is low and can reduce and the contact resistance of contact layer 36, can suppress the semiconductor optical device of the rising of operating voltage simultaneously.

In addition, close attachment layer 45 is that film forming can stably be carried out with evaporation or sputter by one or two metal material or its nitride that element constitutes.The semiconductor LD10 that therefore, can have stable properties with good rate of finished products manufacturing.And then, can be with the good rate of finished products manufacturing semiconductor LD10 that operating voltage is low, reliability is high.

And then, by at the stacked raceway groove 38 that forms on the wafer of semiconductor layer, form wave guide ridge 40 and electrode pad pedestal 42, on whole of wafer, form SiO ₂Film 78 and by the close attachment layer 45 that constitutes as the 1st close attachment film 45a of Ti film and the 2nd close attachment film 45b that on the 1st close attachment film 45a, forms as the Au film.Then, coating is the resist of main component with phenolic resins on whole of wafer, forms resist film 90, makes the upper surface of the close attachment layer 45 at the surface of the resist film 90 on the raceway groove 38 and wave guide ridge 40 tops have roughly the same height.Then, to resist film 90 photomechanical process operation, form following such resist figure 92: the residual resist film 90 of a part on the close attachment layer 45 of the bottom surface of raceway groove 38, between the close attachment layer 45 on the interior sidewall of the resist film 90 in the interval e isolation channel 30 of regulation and raceway groove 30, and close attachment layer 45 surface at the top of the top of wave guide ridge 40 and electrode pad pedestal 42 are exposed equably.Then,, photoresist is flowed, make close attachment layer 45 close attachment on raceway groove 30 interior resist films 90 and raceway groove 30 madial walls, form resist figure 82 by wafer is heat-treated.

In this manufacture method, p lateral electrode 46 is difficult to cause peeling off of p lateral electrode 46 through close attachment layer 45 and the 1st silicon insulating film 44 close attachment securely.The semiconductor layer that contacts with p lateral electrode 46 is the p-GaN layer 74 that becomes contact layer 36 at this moment, and its upper surface is by close attachment layer 45 and SiO ₂The peristome 44a of film 78 exposes reliably, does not have SiO on the upper surface of p-GaN layer 74 ₂ Film 78 is residual.Therefore, because p lateral electrode 46 can not reduce with the contact area of contact layer 36, p lateral electrode 46 has the structure that is made of the such metal film of Au film/Pt film/Au film in addition, so that available simple operation produces resistance value is low and can reduce and the contact resistance of contact layer 36, can suppress the semiconductor optical device of the rising of operating voltage simultaneously.

And then, in remaining in the etching that wave guide ridge 40 forms under the state of employed resist figure 76, on whole of wafer, form SiO ₂Film 78 and cover this SiO ₂Film 78 by the close attachment layer 45 that constitutes as the Ti film of the 1st close attachment film 45a and the Au film that on this Ti film, forms, then, remove resist figure 76, residual Si O on the surface of the inside of raceway groove 38 with organic solvent etc. ₂ Film 78 and close attachment layer 45, the formed SiO of resist film upper surface on wave guide ridge 40 and electrode pad pedestal 42 ₂ Film 78 and close attachment layer 45 are removed with resist film, make formed p-GaN layer 74 exposure on wave guide ridge 40 and electrode pad pedestal 42, in this manufacture method, p lateral electrode 46 is through close attachment layer 45 and the 1st silicon insulating film 44 close attachment securely, be difficult to cause peeling off of p lateral electrode 46, because p lateral electrode 46 has the structure that is made of the such metal film of Au film/Pt film/Au film, so that available simple operation produces resistance value is low and can reduce semiconductor optical device with the contact resistance of contact layer 36.

As mentioned above, semiconductor optical device of the present invention comprises: substrate; Semiconductor stacked structure is included in the 2nd semiconductor layer of the 1st semiconductor layer, active layer and the 2nd conduction type of the 1st conduction type that stacks gradually on this substrate; Wave guide ridge is formed by a part of semiconductor layer of the 2nd semiconductor layer that comprises this semiconductor stacked structure; The 1st dielectric film has peristome accordingly with the top of this wave guide ridge, covers the sidewall of wave guide ridge; The close attachment layer is provided on the 1st dielectric film with getting rid of above-mentioned peristome, and comprises the 1st close attachment film that any the nitride by any metal of Ti, TiW, Nb, Ta, Cr, Mo or these metals forms; And metal electrode layer, be configured on this close attachment layer, and through the peristome close attachment on the 2nd semiconductor layer at the top of wave guide ridge, thereby, in semiconductor optical device of the present invention, metal electrode layer through the peristome close attachment on the 2nd semiconductor layer at wave guide ridge top, and the part of this metal electrode layer through with the 1st dielectric film close attachment layer of close attachment securely, close attachment is on the 1st dielectric film securely.Therefore, can prevent peeling off of metal electrode film, and because the contact resistance of metal electrode layer is low, so can make the operating voltage of semiconductor optical device keep very lowly.And then, can constitute the semiconductor LD that operating voltage is low, reliability is high.

In addition, the manufacture method of semiconductor optical device of the present invention comprises following operation: stack gradually the 2nd semiconductor layer of the 1st semiconductor layer, active layer and the 2nd conduction type of the 1st conduction type on semiconductor substrate, to form semiconductor stacked structure; On the surface of this semiconductor stacked structure, apply resist, form the 1st resist figure that has been equipped with bar shaped resist film part with the photomechanical process operation with width corresponding with wave guide ridge; By being mask with the 1st resist figure, remove the part of the upper surface side of the 2nd semiconductor layer with dry etching, be formed on its bottom residual the recess of a part of the 2nd semiconductor layer, thereby form wave guide ridge; After having removed the 1st resist figure, on the surface of the semiconductor stacked structure that comprises recess, form the 1st dielectric film; On the 1st dielectric film, form the close attachment layer comprise the 1st close attachment film that any the nitride by any metal of Ti, TiW, Nb, Ta, Cr, Mo or above-mentioned metal forms; Form the 2nd resist figure, this figure exposes the surface of the close attachment layer of wave guide ridge top formation, and utilize resist film, bury close attachment layer underground with the recess of wave guide ridge adjacency with surface high and lower than the close attachment laminar surface on the wave guide ridge top than the top surface of wave guide ridge; With the 2nd resist figure is mask, removes close attachment layer and the 1st dielectric film by etching, and the 2nd semiconductor layer surface of wave guide ridge is exposed; And after having removed the 2nd resist figure, on the surface of the 2nd semiconductor layer of the wave guide ridge that exposes and close attachment layer, form metal electrode layer, thereby, metal electrode layer is bonded on the 1st dielectric film securely through the close attachment layer, can prevent peeling off of metal electrode film, and peristome by close attachment layer and the 1st dielectric film, the 2nd semiconductor layer is reliably exposed and the contact area of metal electrode layer and the 2nd semiconductor layer can not reduce, the contact resistance of metal electrode layer is low, can suppress simultaneously the rising of operating voltage, such semiconductor optical device can create with simple operation.

In addition, the close attachment layer is that film forming can stably be carried out with evaporation or sputter by one or two metal material or its nitride that element constitutes.The semiconductor optical device that therefore, can have stable properties with good rate of finished products manufacturing.

And then, can be with the good rate of finished products manufacturing semiconductor optical device that operating voltage is low, reliability is high.

And then the manufacture method of semiconductor optical device of the present invention comprises following operation: stack gradually the 2nd semiconductor layer of the 1st semiconductor layer, active layer and the 2nd conduction type of the 1st conduction type on semiconductor substrate, to form semiconductor stacked structure; On the surface of this semiconductor stacked structure, apply resist, form the 1st resist figure that has been equipped with bar shaped resist film part with the photomechanical process operation with width corresponding with wave guide ridge; By being mask with the 1st resist figure, remove the part of the upper surface side of the 2nd semiconductor layer with dry etching, be formed on its bottom residual the recess of a part of the 2nd semiconductor layer, thereby form wave guide ridge; Under the state of residual the 1st resist figure, on the surface of the semiconductor stacked structure that comprises recess, form the 1st dielectric film; On the 1st dielectric film, form the close attachment layer comprise the 1st close attachment film that any the nitride by any metal of Ti, TiW, Nb, Ta, Cr, Mo or above-mentioned metal forms; Remove the 1st resist figure, and remove formed close attachment layer and the 1st dielectric film on this resist figure, the 2nd semiconductor layer surface of wave guide ridge is exposed; And on the surface of the 2nd semiconductor layer of the wave guide ridge that exposes and close attachment layer, form metal electrode layer, thereby, metal electrode layer is bonded on the 1st dielectric film securely through the close attachment layer, can prevent peeling off of metal electrode film, and the contact resistance of metal electrode layer is low, can suppress the rising of operating voltage, such semiconductor optical device can create with simple operation.

As mentioned above, semiconductor optical device of the present invention and manufacture method thereof are suitable for being equipped with at the wave guide ridge top semiconductor optical device and the manufacture method thereof of electrode.

Claims

1. semiconductor optical device is characterized in that possessing:

Substrate;

Semiconductor stacked structure is included in the 2nd semiconductor layer of the 1st semiconductor layer, active layer and the 2nd conduction type of the 1st conduction type that stacks gradually on this substrate;

Wave guide ridge is formed by a part of semiconductor layer of above-mentioned the 2nd semiconductor layer that comprises this semiconductor stacked structure;

The 1st dielectric film has peristome accordingly with the napex of this wave guide ridge, covers the sidewall of wave guide ridge;

The close attachment layer is provided on above-mentioned the 1st dielectric film with getting rid of above-mentioned peristome, and comprises the 1st close attachment film that any the nitride by any metal of Ti, TiW, Nb, Ta, Cr, Mo or above-mentioned metal forms; And

Metal electrode layer is provided on this close attachment layer, and through above-mentioned peristome close attachment on the 2nd semiconductor layer at the top of above-mentioned wave guide ridge.

2. semiconductor optical device as claimed in claim 1 is characterized in that,

The close attachment layer also possesses the 2nd close attachment film that contains Au that is provided on the 1st close attachment film.

3. semiconductor optical device as claimed in claim 1 or 2 is characterized in that,

Substrate is formed by GaN, and the 1st semiconductor layer is formed by AlGaN, and active layer is formed by InGaN, and the 2nd semiconductor layer forms by comprising 1 layer of the GaN layer or multi-lager semiconductor layer.

4. the manufacture method of a semiconductor optical device is characterized in that, comprises following operation:

On semiconductor substrate, stack gradually the 2nd semiconductor layer of the 1st semiconductor layer, active layer and the 2nd conduction type of the 1st conduction type, to form semiconductor stacked structure;

On the surface of this semiconductor stacked structure, apply resist, form the 1st resist figure that has been equipped with bar shaped resist film part with the photomechanical process operation with width corresponding with wave guide ridge;

By being mask with the 1st resist figure, remove the part of the upper surface side of the 2nd semiconductor layer with dry etching, be formed on its bottom residual the recess of a part of the 2nd semiconductor layer, thereby form wave guide ridge;

After having removed the 1st resist figure, on the surface of the semiconductor stacked structure that comprises recess, form the 1st dielectric film;

On the 1st dielectric film, form the close attachment layer comprise the 1st close attachment film that any the nitride by any metal of Ti, TiW, Nb, Ta, Cr, Mo or above-mentioned metal forms;

Form the 2nd resist figure, this figure exposes the surface of the close attachment layer of wave guide ridge top formation, and utilize resist film, bury close attachment layer underground with the recess of wave guide ridge adjacency with surface high and lower than the close attachment laminar surface on the wave guide ridge top than the top surface of wave guide ridge;

With the 2nd resist figure is mask, removes close attachment layer and the 1st dielectric film by etching, and the 2nd semiconductor layer surface of wave guide ridge is exposed; And

After having removed the 2nd resist figure, on the surface of the 2nd semiconductor layer of the wave guide ridge that exposes and close attachment layer, form metal electrode layer.

5. the manufacture method of semiconductor optical device as claimed in claim 4 is characterized in that,

The operation that forms the 2nd resist figure comprises following operation:

On above-mentioned close attachment layer, apply resist, and the thick resist film of thickness of the resist film at the Film Thickness Ratio wave guide ridge top of the resist film of the recess of formation and wave guide ridge adjacency; And

Remove resist equably from the surface of this resist film, in the resist film of the recess of residual and wave guide ridge adjacency, the close attachment layer at wave guide ridge top is exposed.

6. the manufacture method of semiconductor optical device as claimed in claim 4 is characterized in that,

The operation that forms the 2nd resist figure comprises following operation:

Form resist film, this film apply resist with covering close attachment layer on above-mentioned close attachment layer, with the recess of wave guide ridge adjacency, the surface of resist film has the roughly the same height of upper surface with the close attachment layer of wave guide ridge;

Form the resist figure, this figure is by the photomechanical process operation, with the part of the bottom surface of the recess of wave guide ridge adjacency on residual resist film with covering close attachment layer, and the close attachment layer at wave guide ridge top is exposed equably; And

The area coverage of the resist film of the bottom surface of recess is expanded to the whole zone, bottom surface of recess.

7. the manufacture method of semiconductor optical device as claimed in claim 4 is characterized in that,

The operation that forms the close attachment layer also possesses the operation that forms the 2nd close attachment film that contains Au on the 1st close attachment film.

8. the manufacture method of semiconductor optical device as claimed in claim 4 is characterized in that,

Semiconductor substrate is formed by GaN, and the 1st semiconductor layer is formed by AlGaN, and active layer is formed by InGaN, and the 2nd semiconductor layer is formed by the semiconductor layer that comprises the GaN layer.

9. the manufacture method of a semiconductor optical device is characterized in that, comprises following operation:

Under the state of residual the 1st resist figure, on the surface of the semiconductor stacked structure that comprises recess, form the 1st dielectric film;

Remove the 1st resist figure, and remove formed close attachment layer and the 1st dielectric film on this resist figure, the 2nd semiconductor layer surface of wave guide ridge is exposed; And

On the surface of the 2nd semiconductor layer of the wave guide ridge that exposes and close attachment layer, form metal electrode layer.

10. the manufacture method of semiconductor optical device as claimed in claim 9 is characterized in that,

11. the manufacture method of semiconductor optical device as claimed in claim 9 is characterized in that,

12. the manufacture method of a semiconductor optical device is characterized in that, comprises following operation:

On the surface of the semiconductor stacked structure that the 2nd semiconductor layer of the 1st semiconductor layer that has stacked gradually the 1st conduction type on the substrate, active layer and the 2nd conduction type forms, apply resist, form with the photomechanical process operation and be equipped with the 1st resist figure that has with the resist film part of wave guide ridge corresponding shape;

By being mask with the 1st resist figure, utilize etching to remove the part of the upper surface side of the 2nd semiconductor layer, be formed on the recess of the part of its residual the 2nd semiconductor layer in bottom, thereby form wave guide ridge;

Form the 2nd resist figure, this figure exposes the surface of the formed close attachment layer in wave guide ridge top, and utilize resist film, bury close attachment layer underground with the recess of wave guide ridge adjacency with surface high and lower than the close attachment laminar surface on the wave guide ridge top than the top surface of wave guide ridge;

13. the manufacture method of a semiconductor optical device is characterized in that, comprises following operation: