CN101109784A - Testing method for integrated circuit high temperature dynamic aging and testing device thereof - Google Patents
Testing method for integrated circuit high temperature dynamic aging and testing device thereof Download PDFInfo
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- CN101109784A CN101109784A CNA2007101207199A CN200710120719A CN101109784A CN 101109784 A CN101109784 A CN 101109784A CN A2007101207199 A CNA2007101207199 A CN A2007101207199A CN 200710120719 A CN200710120719 A CN 200710120719A CN 101109784 A CN101109784 A CN 101109784A
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- 238000012360 testing method Methods 0.000 title claims abstract description 108
- 230000032683 aging Effects 0.000 title claims abstract description 83
- 238000012795 verification Methods 0.000 claims abstract description 26
- 238000009434 installation Methods 0.000 claims description 18
- 238000010998 test method Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 abstract description 2
- 238000013461 design Methods 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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Abstract
The invention relates to the field of test technology for integrated circuits, in particular to a testing method and device for the dynamic high temperature aging of IC. Wherein, an IC is welded on an aging subboard, which goes through test on function verification and dynamic operation mode; the aging subboard passes the test and on which an IC is welded is inserted in an interfacing socket of a universal aging board; the universal aging board is connected with an aging test system to carry out aging test; function verification test and dynamic operation mode test are carried out on the aging subboard at different time periods depending upon the test standard, so as to prove whether the IC can work normally. The invention is applicable for the universal testing of various different encapsulated products without ordering special aging boards for products of different encapsulating forms, hence the preparation time for test is reduced, test period is dropped, and the test cost is saved.
Description
Technical field
The present invention relates to the technical field of measurement and test of integrated circuit, be specifically related to a kind of integrated circuit high temperature dynamic aging method of testing and proving installation.
Background technology
Present integrated circuit high temperature dynamic aging (HTOL) test needs to select for use different burn-in board to carry out according to the difference encapsulation of chip usually.The major defect of this mode is: (1) at the burn-in board of different packing forms product subscription specific, the cycle of preparation is very long; (2) if product is BGA encapsulation, or the more special QFN of packing forms, to buy 80ea socket so and be used for testing costly, testing cost is high; (3) aging reading a little and terminal point can take a large amount of ATE machine when carrying out functional test the time.At the deficiency of above-mentioned special-purpose burn-in board test mode, a kind of mode that adopts generic disk to carry out burn-in test has also appearred at present.This generic disk is arranged on the Test Application circuit bottom surface of each socket, the product of same package pattern all can cooperate the DUT card to use jointly, and can on the DUT card, make the test peripheral circuit, but, this universal burn-in plate makes the DUT card because must cooperating, cost is higher, the low and difficult acceptance of the simple client of measurement circuit for those production unit costs.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art, under the prerequisite that guarantees test accuracy, a kind of universal integrated circuit high temperature dynamic aging method of testing and proving installation that is applicable to multiple encapsulating products is provided, thereby reduces test period, save testing cost.
Technical scheme of the present invention is as follows: a kind of integrated circuit high temperature dynamic aging method of testing comprises the steps:
(1) integrated circuit is welded on the aging daughter board, and aging daughter board is carried out functional verification test and dynamic operation mode test;
(2) will test the aging daughter board that is welded with integrated circuit that passes through and be plugged on the interface socket of universal burn-in plate, the universal burn-in plate will be inserted in the aging testing system, carry out burn-in test;
(3) according to testing standard, at different time points aging daughter board is carried out functional verification test and dynamic operation mode test, whether still can operate as normal with the proof integrated circuit.
Further, in said integrated circuit high temperature dynamic aging method of testing, testing standard adopts JESD22-A108-C, at 168 hours, 500 hours of test process and 1000 hours test terminal points aging daughter board is carried out functional verification test and dynamic operation mode test respectively.
Aforesaid integrated circuit high temperature dynamic aging method of testing, wherein, when step (2) was carried out burn-in test to integrated circuit, each signal pin of aging daughter board went up and adds a resistance, to interfere with each other between the socket of avoiding parallel connection.
A kind of integrated circuit high temperature dynamic aging proving installation that is applied to said method, comprise universal burn-in plate and the aging daughter board that can be plugged on the universal burn-in plate, the test channel circuit that the universal burn-in plate is provided with several interface sockets parallel with one another and is connected with aging testing system; Aging daughter board is provided with the basic application circuit and the golden finger interface that can guarantee chip operate as normal and dynamic duty, and tested integrated circuit directly is welded on the aging daughter board.
Further, in said integrated circuit high temperature dynamic aging proving installation, also be provided with USB interface and Sensor interface on the aging daughter board.
Aforesaid integrated circuit high temperature dynamic aging proving installation, this device also comprise daughter board functional verification test plate and dynamic operation mode test board, and aging daughter board is connected with the dynamic operation mode test board with the functional verification test plate by golden finger interface respectively.
In said integrated circuit high temperature dynamic aging proving installation, the pin circuit that the functional verification test plate must be provided with when comprising the chip operate as normal that is connected with golden finger interface respectively, and Vbus changes the change-over circuit of the required power supply of chip; In addition, also be provided with ADC interface and Sensor interface on the functional verification test plate.
In said integrated circuit high temperature dynamic aging proving installation, the dynamic operation mode test board comprises input of chip dynamic aging and necessary pin circuit, the 16bit data bus transmitted in both directions chip that is provided with of checking that is connected with golden finger interface respectively, and Vbus changes the change-over circuit of the required power supply of chip; 16bit data bus transmitted in both directions chip connects the ARM9 plate interface.
Integrated circuit high temperature dynamic aging method of testing provided by the present invention and proving installation, be applicable to the universal test of multiple different encapsulating products, do not need to encapsulate according to difference again the burn-in board of the product subscription specific of pattern, thereby reduced the setup time of test, reduce test period, and saved testing cost.
Description of drawings
Fig. 1 is the structural representation of universal burn-in plate.
Fig. 2 is the definition synoptic diagram of universal burn-in plate socket pin.
Fig. 3 is universal burn-in plate one a drive test examination circuit diagram.
The structured flowchart of the aging daughter board in Fig. 4 position.
Fig. 5 is the structured flowchart of functional verification test plate.
Fig. 6 is the structured flowchart of dynamic operation mode test board.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in detail.
Integrated circuit high temperature dynamic aging proving installation provided by the present invention comprises universal burn-in plate and the aging daughter board that can be plugged on the universal burn-in plate.As shown in Figure 1, the test channel circuit that the universal burn-in plate is provided with several interface sockets parallel with one another and is connected with aging testing system, Fig. 2 is seen in the pin definition of interface socket, and aging testing system adopts SIGNALITY-B1120M dynamic aging test macro.The test channel circuit comprises the interface with the aging testing system board, and signal input circuit, and the one line structure as shown in Figure 3.
As shown in Figure 4, aging daughter board is provided with the basic application circuit and the golden finger interface that can guarantee chip operate as normal and dynamic duty, and tested integrated circuit directly is welded on the aging daughter board.Basic application circuit comprises crystal oscillating circuit and chip power filtering circuit, golden finger interface comprise needs give the power supply of chip,, the needed pin of pin, functional verification, the pin of dynamic aging checking needs of required input output signal during the dynamic aging operation, for fear of between the socket of parallel connection, interfere with each other, at the resistance that should add between each signal pin about one 300 ohm, this resistance is place in circuit when burn-in test on the daughter board.The power supply of daughter board, pin consistent with the definition of the pin pin of universal burn-in plate interface socket.Can also be provided with USB interface and Sensor interface on the aging daughter board, these two functional interfaces also can merge setting.
This proving installation also comprises daughter board functional verification test plate and dynamic operation mode test board, and aging daughter board is connected with the dynamic operation mode test board with the functional verification test plate by golden finger interface respectively.As shown in Figure 5, the pin circuit that the functional verification test plate must be provided with when comprising the chip operate as normal that is connected with golden finger interface respectively, and Vbus changes the change-over circuit of the required power supply of chip; In addition, can also be provided with ADC interface and Sensor interface on the functional verification test plate.The different interface circuit of kind design according to chip ADC can design as required on daughter board or functional verification test plate.As shown in Figure 6, the dynamic operation mode test board comprises input of chip dynamic aging and necessary pin circuit, the 16bit data bus transmitted in both directions chip that is provided with of checking that is connected with golden finger interface respectively, and Vbus changes the change-over circuit of the required power supply of chip; 16bit data bus transmitted in both directions chip connects the ARM9 plate interface.
Above-mentioned various circuit structures and interface type be specific design and selection according to actual needs all, and those skilled in the art can realize fully.
Method of testing provided by the present invention adopts the JESD22-A108-C testing standard, and detailed process is as follows:
(1) integrated circuit is welded on the aging daughter board, before burn-in test, adopts the functional verification test plate that the aging daughter board of 80pcs is carried out functional verification test, adopt the dynamic operation mode test board that the aging daughter board of 80pcs is carried out dynamic operation mode operation test;
(2) will be inserted on the interface socket of universal burn-in plate by aging daughter board by the 80pcs of test, and put into aging testing system and pour into the pattern that mixes up in advance, the beginning burn-in test;
(3) respectively the aging daughter board of 80pcs is carried out functional verification test and dynamic operation mode operation test at 168hrs, the 500hrs of burn-in test and 1000hrs test terminal point, prove still can operate as normal behind the chip process burn-in test.
Consider the description of this invention disclosed herein and special embodiment, other embodiment of the present invention are conspicuous for a person skilled in the art.These explanations and embodiment only consider as an example that they all belong to by within the indicated protection scope of the present invention and spirit of claims.
Claims (10)
1. an integrated circuit high temperature dynamic aging method of testing comprises the steps:
(1) integrated circuit is welded on the aging daughter board, and aging daughter board is carried out functional verification test and dynamic operation mode test;
(2) will test the aging daughter board that is welded with integrated circuit that passes through and be plugged on the interface socket of universal burn-in plate, the universal burn-in plate will be inserted in the aging testing system, carry out burn-in test;
(3) according to testing standard, at different time points aging daughter board is carried out functional verification test and dynamic operation mode test, whether still can operate as normal with the proof integrated circuit.
2. integrated circuit high temperature dynamic aging method of testing as claimed in claim 1, it is characterized in that: testing standard adopts JESD22-A108-C, at 168 hours, 500 hours of test process and 1000 hours test terminal points aging daughter board is carried out functional verification test and dynamic operation mode test respectively.
3. integrated circuit high temperature dynamic aging method of testing as claimed in claim 1 or 2, it is characterized in that: when step (2) is carried out burn-in test to integrated circuit, each signal pin of aging daughter board goes up and adds a resistance, to interfere with each other between the socket of avoiding parallel connection.
4. integrated circuit high temperature dynamic aging proving installation, it is characterized in that: this device comprises universal burn-in plate and the aging daughter board that can be plugged on the universal burn-in plate, the test channel circuit that the universal burn-in plate is provided with several interface sockets parallel with one another and is connected with aging testing system; Aging daughter board is provided with the basic application circuit and the golden finger interface that can guarantee chip operate as normal and dynamic duty, and tested integrated circuit directly is welded on the aging daughter board.
5. integrated circuit high temperature dynamic aging proving installation as claimed in claim 4 is characterized in that: be connected with one and be used to avoid the resistance that interferes with each other between socket on each signal pin of aging daughter board golden finger interface.
6. integrated circuit high temperature dynamic aging proving installation as claimed in claim 5 is characterized in that: also be provided with USB interface and Sensor interface on the aging daughter board.
7. as claim 4 or 5 or 6 described integrated circuit high temperature dynamic aging proving installations, it is characterized in that: this device also comprises daughter board functional verification test plate and dynamic operation mode test board, and aging daughter board is connected with the dynamic operation mode test board with the functional verification test plate by golden finger interface respectively.
8. integrated circuit high temperature dynamic aging proving installation as claimed in claim 7, it is characterized in that: the pin circuit that the functional verification test plate must be provided with when comprising the chip operate as normal that is connected with golden finger interface respectively, and Vbus changes the change-over circuit of the required power supply of chip.
9. integrated circuit high temperature dynamic aging proving installation as claimed in claim 8 is characterized in that: also be provided with ADC interface and Sensor interface on the functional verification test plate.
10. integrated circuit high temperature dynamic aging proving installation as claimed in claim 7, it is characterized in that: the dynamic operation mode test board comprises input of chip dynamic aging and necessary pin circuit, the 16bit data bus transmitted in both directions chip that is provided with of checking that is connected with golden finger interface respectively, and Vbus changes the change-over circuit of the required power supply of chip; 16bit data bus transmitted in both directions chip connects the ARM9 plate interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN200710120719A CN100588979C (en) | 2007-08-24 | 2007-08-24 | Testing method for integrated circuit high temperature dynamic aging and testing device thereof |
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| CN200710120719A CN100588979C (en) | 2007-08-24 | 2007-08-24 | Testing method for integrated circuit high temperature dynamic aging and testing device thereof |
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| CN101109784A true CN101109784A (en) | 2008-01-23 |
| CN100588979C CN100588979C (en) | 2010-02-10 |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101738503B (en) * | 2008-11-18 | 2011-10-05 | 中芯国际集成电路制造(上海)有限公司 | Interface device and control method and aging test system thereof |
| CN102081138B (en) * | 2009-12-01 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for wafer-level burn-in test of semiconductor devices |
| CN102043100B (en) * | 2009-10-09 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Aging test system |
| CN103258573A (en) * | 2013-05-22 | 2013-08-21 | 山东华芯微电子科技有限公司 | Aging plate |
| CN106569124A (en) * | 2016-11-09 | 2017-04-19 | 中国空间技术研究院 | Universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays) |
| CN107025156A (en) * | 2017-04-14 | 2017-08-08 | 广东浪潮大数据研究有限公司 | A kind of computer aging method based on Windows systems |
| CN107543574A (en) * | 2017-06-01 | 2018-01-05 | 中国航发湖南动力机械研究所 | Airborne sensor high temperature aging tests automatic tester and operating method |
| CN109342921A (en) * | 2018-10-09 | 2019-02-15 | 天津芯海创科技有限公司 | A kind of ageing testing method and system of high speed exchange chip |
| CN109444725A (en) * | 2019-01-11 | 2019-03-08 | 西安君信电子科技有限责任公司 | A kind of the multifunctional testing plate and test method of integrated circuit test device |
| CN109975691A (en) * | 2019-03-29 | 2019-07-05 | 成都天奥技术发展有限公司 | Integrated circuit universal burn-in experimental rig |
| CN111722079A (en) * | 2020-04-30 | 2020-09-29 | 西安太乙电子有限公司 | Function verification device for integrated circuit aging scheme |
| CN113866612A (en) * | 2021-11-30 | 2021-12-31 | 北京京瀚禹电子工程技术有限公司 | Aging test board and aging test equipment |
| WO2022143037A1 (en) * | 2020-12-31 | 2022-07-07 | 锐石创芯(深圳)科技股份有限公司 | Chip test assembly, chip test system and chip test method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349385C (en) * | 2004-04-16 | 2007-11-14 | 华为技术有限公司 | Verifying device special for integrated circuit function |
| CN101021547A (en) * | 2006-03-30 | 2007-08-22 | 信息产业部电子第五研究所 | Bare chip test and aging screening temporary packaging carrier |
| CN100507586C (en) * | 2006-09-21 | 2009-07-01 | 北京中星微电子有限公司 | Method for evaluating lifespan of integrated circuit chip products |
-
2007
- 2007-08-24 CN CN200710120719A patent/CN100588979C/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101738503B (en) * | 2008-11-18 | 2011-10-05 | 中芯国际集成电路制造(上海)有限公司 | Interface device and control method and aging test system thereof |
| CN102043100B (en) * | 2009-10-09 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Aging test system |
| CN102081138B (en) * | 2009-12-01 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for wafer-level burn-in test of semiconductor devices |
| CN103258573A (en) * | 2013-05-22 | 2013-08-21 | 山东华芯微电子科技有限公司 | Aging plate |
| CN103258573B (en) * | 2013-05-22 | 2016-01-06 | 山东华芯微电子科技有限公司 | A kind of burn-in board |
| CN106569124A (en) * | 2016-11-09 | 2017-04-19 | 中国空间技术研究院 | Universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays) |
| CN107025156A (en) * | 2017-04-14 | 2017-08-08 | 广东浪潮大数据研究有限公司 | A kind of computer aging method based on Windows systems |
| CN107543574B (en) * | 2017-06-01 | 2019-12-06 | 中国航发湖南动力机械研究所 | Automatic detector for high-temperature aging test of airborne sensor and operation method |
| CN107543574A (en) * | 2017-06-01 | 2018-01-05 | 中国航发湖南动力机械研究所 | Airborne sensor high temperature aging tests automatic tester and operating method |
| CN109342921A (en) * | 2018-10-09 | 2019-02-15 | 天津芯海创科技有限公司 | A kind of ageing testing method and system of high speed exchange chip |
| CN109444725A (en) * | 2019-01-11 | 2019-03-08 | 西安君信电子科技有限责任公司 | A kind of the multifunctional testing plate and test method of integrated circuit test device |
| CN109975691A (en) * | 2019-03-29 | 2019-07-05 | 成都天奥技术发展有限公司 | Integrated circuit universal burn-in experimental rig |
| CN111722079A (en) * | 2020-04-30 | 2020-09-29 | 西安太乙电子有限公司 | Function verification device for integrated circuit aging scheme |
| CN111722079B (en) * | 2020-04-30 | 2023-02-24 | 西安太乙电子有限公司 | Function verification device for integrated circuit aging scheme |
| WO2022143037A1 (en) * | 2020-12-31 | 2022-07-07 | 锐石创芯(深圳)科技股份有限公司 | Chip test assembly, chip test system and chip test method |
| CN113866612A (en) * | 2021-11-30 | 2021-12-31 | 北京京瀚禹电子工程技术有限公司 | Aging test board and aging test equipment |
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| CN100588979C (en) | 2010-02-10 |
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