CN103258573B - A kind of burn-in board - Google Patents
A kind of burn-in board Download PDFInfo
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- CN103258573B CN103258573B CN201310192036.XA CN201310192036A CN103258573B CN 103258573 B CN103258573 B CN 103258573B CN 201310192036 A CN201310192036 A CN 201310192036A CN 103258573 B CN103258573 B CN 103258573B
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Abstract
The invention discloses a kind of burn-in board, comprise be provided with plate carry the plate body of bus and array on plate body and coupling be connected to described plate carry bus for holding, support and be electrically connected the slot of SDRAM chip to be aging, wherein plate body side is provided with and carries for described plate the golden finger that bus is connected with board, described burn-in board is used for the aging of many moneys SDRAM chip same period, thus, described bus has the wire harness configured based on the chip that many moneys SDRAM chip pin same period is maximum, based on bus management and control, described in coupling the same period many moneys SDRAM chip the plate of total wiring carry bus wire harness and to be fixed the described golden finger of access, all the other wire harness are for selecting wire harness, corresponding configuration wire jumper, the selection wire harness of the aging SDRAM of current hospitality is mated with the access selected, and hang up the current described selection wire harness do not used.Same burn-in board can be met according to the present invention and can meet the aging of many moneys SDRAM same period by simple adjustment.
Description
Technical field
The present invention relates to a kind of burn-in board, specifically relate to a kind of burn-in board for interior DRAM burn-in test; DRAM is the abbreviation of DynamicRandomAccessMemory, i.e. dynamic RAM.
Background technology
In order to reach satisfied qualification rate, nearly all product all will carry out burn-in test before dispatching from the factory.The same with other products, semiconductor devices all likely breaks down because of a variety of causes at any time, aging is exactly that nationality makes its defect occur in the short period of time by allowing semiconductor devices work under given overload state, avoids re-using and breaks down in early days.Device after aging requires that 100% elimination has the fault produced during this period of time substantially.
The aging curve in serviceable life coming from semiconductor devices, its major failure more appears at its life-span and starts ten/one-phase and last ten/one-phase.Aging is exactly the process of faster devices 10% part before its life-span, forces initial failure to occur as far as possible in the short period of time.
Because the processing procedure of device manufacturer to produced device is clearer, therefore, device aging is more complete in device producer side, producer needs the device detection in the face of flood tide, therefore, in aging, in order to improve the output of product, preferably can do aging to device as much as possible simultaneously.In order to meet this requirement, multiple device can be contained in and a large printed circuit board (PCB) carry out aging, this circuit board is commonly called burn-in board.
At semicon industry, due to the importing of DRAM new product, semiconductor package surveys factory to be needed according to DRAM(DynamicRandomAccessMemory, dynamic RAM) characteristic of product and ball distribution, the in time corresponding DRAM burn-in test carrier degradation plate of customization.
Due to the singularity of burn-in board material, needing to work under the test environment of High Temperature High Pressure, as required more than 3000 hours heatproofs 125 DEG C, so the price is rather stiff of veneer, is also a great expense of new product introduction.
In addition, due to according to SDRAM(SynchronousDynamicRandomAccessMemory, synchronous DRAM) the international JEDEC standard of chip, there is certain difference in different SDRAM chip pin numbers and Signal Matching, so need to use specific burn-in board to carry out burn-in test for different dram chips.
Thus, for different dram chips, need to use different burn-in board, cause the frequent replacing of aging class, cause the restriction of cost control.
While frequent replacing new product burn-in test carrier, also need to carry out reliability demonstration, electrical property checking, material identification to DRAM burn-in test carrier, need to drop into considerable time, the also extra debug time adding charger and maintenance time, greatly reduce work efficiency.
Therefore, in the limited scope of model, general burn-in board can carry out cost control effectively.Need to understand all tested devices in burn-in board here to be all connected in parallel, cause the physical electric performance of large-scale burn-in board can not to compare with the little test platform only testing a device, reason is that capacitive in burn-in board and inductive load can make troubles to test, thus, usually relatively less test can only be carried out in burn-in board, and not all.
Summary of the invention
The present invention is directed to the structure proximity of the SDRAM product same period, propose a kind of burn-in board, the aging of many moneys SDRAM same period can be met to meet same burn-in board by simple adjustment.
General understanding, the development of current SDRAM have passed through DDR1(DoubleDataRate, Double Data Rate synchronous DRAM, writing a Chinese character in simplified form of DDRSDRAM), tetra-periods of DDR2, DDR3, DDR4, within different product period, again because the difference of technique itself creates many moneys product of the same period, according to JEDEC international standard, product of the same period has regularity, ball distribution consistance, test pattern commonality.
In view of this, the present invention is by the following technical solutions:
A kind of burn-in board, comprise be provided with plate carry the plate body of bus and array on plate body and coupling be connected to described plate carry bus for holding, support and be electrically connected the slot of SDRAM chip to be aging, wherein plate body side is provided with and carries for described plate the golden finger that bus is connected with board, described burn-in board is used for the aging of many moneys SDRAM chip same period, thus, described bus has the wire harness configured based on the chip that many moneys SDRAM chip pin same period is maximum, based on bus management and control, described in coupling the same period many moneys SDRAM chip the plate of total wiring carry bus wire harness and to be fixed the described golden finger of access, all the other wire harness are for selecting wire harness, corresponding configuration wire jumper, the selection wire harness of the aging SDRAM of current hospitality is mated with the access selected, and hang up the current described selection wire harness do not used.
As can be seen from said structure, according to the present invention, based on the regularity of same time product, the consistance of ball distribution, there is the different money SDRAM same period of a small amount of difference, by the overall management and control of bus, only need when carrying out different SDRAM and being aging to adjust wire jumper, namely the adjustment realizing a small amount of wire harness function can be used for the aging of another SDRAM, and unlike designing a set of burn-in board for every a SDRAM, and adjustment is also very simple and convenient.
Above-mentioned burn-in board, described plate body is the wiring board based on Fly-by topological structure, and is provided with resistive elements in end side, for impedance matching.
Above-mentioned burn-in board, the impedance matching of channel signal line use resistance for impedance varies with temperature and the resistance of linear change, the resistance of the impedance matching resistor of single-ended signal line is 50 ohm, and the resistance that differential signal line impedance matching uses is 100 ohm.
Above-mentioned burn-in board, the power pins of described socket is serially connected with decoupling capacitor.
Above-mentioned burn-in board, described decoupling capacitor is not less than 0.1 μ F and is not more than 0.2 μ F.
Above-mentioned burn-in board, the wiring number of plies of described plate body is 8 to 10 layers.
Above-mentioned burn-in board, described slot comprises cell body and the upper stitch being arranged on cell body top and is arranged on bottom land for the lower front line be connected with plate body circuit, is provided with a pair clamp button of the spring in the both sides of cell body.
Accompanying drawing explanation
Fig. 1 is the structural representation according to a kind of multi-usage burn-in board of the present invention.
Fig. 2 is the bus management and control schematic diagram of a kind of multi-usage burn-in board application.
Fig. 3 is 512MDRAM chip ball distributed layout figure.
Fig. 4 is 1GDRAM chip ball distributed layout figure.
Fig. 5 is 2GDRAM chip ball distributed layout figure.
Fig. 6 is burn-in board chip fixture sectional view.
Fig. 7 is PIN needle perforation number Local map needed for different dram chip.
Fig. 8 is signal wire connection diagram.
Fig. 9 is single socket base signal connection diagram.
Figure 10 Fly-By topological structure schematic diagram.
Embodiment
With reference to Figure of description 1, burn-in board itself mainly comprises PCB(PrintedCirciutBoard, printed circuit board (PCB)), slot (SOCKET) 11, framework (FRAME) these three parts composition.The row-column arrangement mode giving slot exemplary in Fig. 1, and all do not draw, be the clear of drawing, should be appreciated that the slot 11 in burn-in board is generally ranks array.
Although have community for the ball distribution of same time different process product, along with the increase of chip capacity, required address signal, control signal increase to some extent; Simultaneously different DRAM product (× 4/ × 8/ × 16) institute for complete machine application difference, required outbound data interface also has difference, so also just have nothing in common with each other for burn-in board needed for different dram chip product, by using the unified extensibility meeting address signal and control signal of golden finger signal layout.
Be that example is described to 3 sections of SDRAM of the same period below.
Fig. 3 is 512MDRAM chip ball distribution plan, and the address signal required for it is A0-A12, BA0, BA1, and data line is DQ0-DQ15, CLOCK control clock cable is /RAS ,/CAS ,/WE, CLK, CKE ,/CS, SCAN, I/O.
Fig. 4 is 1GDRAM chip ball distribution plan, and the address signal required for it is A0-A12, BA0-BA2, and data line is DQ0-DQ15, CLOCK control clock cable is /RAS ,/CAS ,/WE, CLK, CKE ,/CS, SCAN, I/O.
Fig. 5 is 2GDRAM chip ball distribution plan, and the address signal required for it is A0-A13, BA0-BA2, and data line is DQ0-DQ15, CLOCK control clock cable is /RAS ,/CAS ,/WE, CLK, CKE ,/CS, SCAN, I/O.
Description for above three sections of SDRAM can show that different dram chip address signal number is different, and corresponding stitch is 31,32,41,42,51,52, and number ratio is less, brings good basis for wire jumper 13 is arranged.
Fig. 6 is single working position on Fig. 1, and namely slot 11, Fig. 7 is then the upward view (omitting front line, pin hole 71 in corresponding diagram) of Fig. 6 slot base.In the process of burn-in test, the chip tin ball 61 in Fig. 6 contacts with upper stitch 64, and upper stitch 64 can be wrapped up in tin bag, simultaneously clamp button of the spring 63 overall fixed chip itself, to facilitate the mounting or dismounting of memory chip.
The signal element that single tin ball is corresponding is connected with the signal wire in burn-in board by lower stitch 62, signal wire is connected with board by golden finger 12 in Fig. 1 again, the address signal that can provide due to board itself is again 16, and the test pattern of different DRAM product is different, and (address wire that 512M needs is A0-A12, BA0, BA1.The address wire that 1GDRAM needs is A0-A12, BA0, BA1.The address wire that 2GDRAM needs is A0-A12, BA0, BA2), 512M is 64:1,1G be 128:1,2G is 128:1.
Way for 512M and 1GDRAM connects BA0-BA2 respectively by A13-A15 exactly, and the front line lacked in increase Fig. 3, so slot 11 is full needle constructions, very to different money SDRAM without the need to adjusting slot 11 stitch, keep the consistance of two kinds of products, but BA2 requires ground connection, so processing mode is according to shown in Fig. 8, BA2 and GND exists with the form of bus management and control.
A13 (52) is added in Fig. 5, 2GT65 increases relative to 512M and 1GT65 difficulty, according to the demand of test pattern, the selection of storage pool (BANK) address there is special demand, now only need BA0 and BA2, and the necessary ground connection of BA1, the signal wire connected mode inapplicable 2GT65 of Fig. 8, in order to the signal line topology of compatible front two product better, and consider the extra A13 address increased, concrete processing mode is: the BA0 that A13 connects remains unchanged, BA1 and A14 adopts the mode of bus management and control, as shown in Figure 2, BA1 and GND wire jumper connects, A14 is connected with the A13 address wire be additionally increased to, A15 is still connected with BA2, but BA2 can not ground connection, to sum up, address wire A13(and 512M, corresponding being connected with BA0 of 1G), A14, the connection corresponding interface of A15 and BANK address is BA0, A13 (the extra address wire that 2G product increases), BA2. now we can according to the needs of 2G product, by the setting of program, burn-in test board sends address by driverboard to test chip, clocking commands, the address signal of A13 and A14 is overturn, actual corresponding signal is that program A14 is connected with chip BA0, program A13 is connected with chip A13, for the single socket of Fig. 6 signal catenation principle as shown in Figure 9, its signal distributions is mated with Fig. 2.
Figure 10 is the Fly-By topological structure that " the JEDEC standard JES79-3C of DDR3SDRAM " specifies, for point-to-point mutual contact mode (DQ, DQS, DM), arranged by the impedance of ODT and carry out impedance matching, but then need multiple spot interconnected for order (Command), address (Address), control (Control) signal, in order to integrality and the synchronism of holding signal, select Figure 10 graph topological structure, reduce the track lengths of signal control line, even do not need short-term, improve the performance of burn-in board test products.
Burn-in board uses 10 laminate designs, is more conducive to the realization of Fly-By topological structure.Impedance matching for channel signal must be continuously constant, and single-ended signal uses 50 ohm to carry out terminal impedance coupling, and differential signal uses 100 ohm to carry out terminal impedance coupling.
Fig. 9 is single socket base signal connection diagram, by carrying out decoupling to semi-conductor chip power vd D and Vref, realize the integrality of Energy control, but in chip ageing test stress process, test macro needs to carry out continuous working line to different semi-conductor chip inside and activates read-write process, more than the frequency 500MHZ refreshed, because the operating power of different product and frequency are had nothing in common with each other, cause semi-conductor chip moment operating voltage, electric current increases degree and has nothing in common with each other, if test macro can not provide operating voltage instantaneously, so chip testing was lost efficacy, bulky capacitor buffering is used at PS1 and PS2 bus place by power calculation, meet moment working line activation reading writing working voltage, bulky capacitor not only can meet the effect of high frequency decoupling, bulky capacitor also has the effect of voltage buffer simultaneously, operating voltage instantaneously can be provided in the moment of high-frequency work, meet the requirement of different semi-conductor chip high-frequency test performance simultaneously.
By the combination of Fig. 2 and Fig. 8, after completing address signal line, data signal line, control signal wire wiring, utilize the mode of bus management and control, bus switch is carried out for same time different DRAM product, but premised on switching point is minimum, the integrality ensured signal quality and consistance, so when testing same time different series product, only need switch bus.
As can be seen from above content, due to a burn-in board can be used, just the aging of multiple SDRAM can be met by simply adjusting, not only save the expense of burn-in board buying, and be more conducive to reducing test machine too frequency division change correction time required for burn-in board, greatly improve the utilization factor of burn-in board and the production efficiency of tester table, thus there is better promotional value.
Claims (6)
1. a burn-in board, comprise be provided with plate carry the plate body of bus and array on plate body and coupling be connected to described plate carry bus for holding, support and be electrically connected the slot of SDRAM chip to be aging, wherein plate body side is provided with and carries for described plate the golden finger that bus is connected with board, it is characterized in that, described burn-in board is used for the aging of many moneys SDRAM chip same period, thus, described bus has the wire harness configured based on the chip that many moneys SDRAM chip pin same period is maximum, based on bus management and control, described in coupling the same period many moneys SDRAM chip the plate of total wiring carry bus wire harness and to be fixed the described golden finger of access, all the other wire harness are for selecting wire harness, corresponding configuration wire jumper, the selection wire harness of the aging SDRAM of current hospitality is mated with the access selected, and hang up the current described selection wire harness do not used,
Described plate body is the wiring board based on Fly-by topological structure, and is provided with resistive elements in end side, for impedance matching.
2. burn-in board according to claim 1, it is characterized in that, the impedance matching of channel signal line use resistance for impedance varies with temperature and the resistance of linear change, the resistance of the impedance matching resistor of single-ended signal line is 50 ohm, and the resistance that differential signal line impedance matching uses is 100 ohm.
3. burn-in board according to claim 1 and 2, is characterized in that, the power pins of described slot is serially connected with decoupling capacitor.
4. burn-in board according to claim 3, is characterized in that, described decoupling capacitor is not less than 0.1 μ F and is not more than 0.2 μ F.
5. burn-in board according to claim 1, is characterized in that, the wiring number of plies of described plate body is 8 to 10 layers.
6. burn-in board according to claim 1, is characterized in that, described slot comprises cell body and the upper stitch being arranged on cell body top and is arranged on bottom land for the lower front line be connected with plate body circuit, is provided with a pair clamp button of the spring in the both sides of cell body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310192036.XA CN103258573B (en) | 2013-05-22 | 2013-05-22 | A kind of burn-in board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310192036.XA CN103258573B (en) | 2013-05-22 | 2013-05-22 | A kind of burn-in board |
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| Publication Number | Publication Date |
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| CN103258573A CN103258573A (en) | 2013-08-21 |
| CN103258573B true CN103258573B (en) | 2016-01-06 |
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| CN201310192036.XA Expired - Fee Related CN103258573B (en) | 2013-05-22 | 2013-05-22 | A kind of burn-in board |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5247248A (en) * | 1991-02-18 | 1993-09-21 | Sharp Kabushiki Kaisha | Burn-in apparatus and method of use thereof |
| CN101109784A (en) * | 2007-08-24 | 2008-01-23 | 北京中星微电子有限公司 | Testing method for integrated circuit high temperature dynamic aging and testing device thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060125504A1 (en) * | 2004-12-10 | 2006-06-15 | Systems On Silicon Manufacturing Company Pte. Ltd. | Printed circuit board for burn-in testing |
| US8203354B2 (en) * | 2009-09-25 | 2012-06-19 | Intersil Americas, Inc. | System for testing electronic components |
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2013
- 2013-05-22 CN CN201310192036.XA patent/CN103258573B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5247248A (en) * | 1991-02-18 | 1993-09-21 | Sharp Kabushiki Kaisha | Burn-in apparatus and method of use thereof |
| CN101109784A (en) * | 2007-08-24 | 2008-01-23 | 北京中星微电子有限公司 | Testing method for integrated circuit high temperature dynamic aging and testing device thereof |
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| CN103258573A (en) | 2013-08-21 |
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Granted publication date: 20160106 Termination date: 20160522 |