CN101064286A - 高性能应力增强mosfet及制造方法 - Google Patents

高性能应力增强mosfet及制造方法 Download PDF

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CN101064286A
CN101064286A CNA200710091566XA CN200710091566A CN101064286A CN 101064286 A CN101064286 A CN 101064286A CN A200710091566X A CNA200710091566X A CN A200710091566XA CN 200710091566 A CN200710091566 A CN 200710091566A CN 101064286 A CN101064286 A CN 101064286A
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pfet
channel region
nfet
stress
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D·奇丹巴尔拉奥
R·A·多纳通
W·K·汉森
K·里姆
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明涉及半导体结构和制造方法，更具体地说，涉及CMOS器件，该器件具有嵌入两个栅极并且还嵌入PFET源极和漏极区域中的应力引起材料，以及不同厚度的PFET和NFET沟道。在一个实施中，该结构通过改变NFET或PFET的顶硅层的厚度，增强了器件性能。

Description

高性能应力增强MOSFET及制造方法
技术领域
本发明一般涉及半导体器件及制造方法，更具体地说，涉及在制造期间，在器件中施加拉伸和压缩应力的半导体器件及制造方法。
背景技术
半导体器件衬底中的机械应力可以调节器件性能。即，已公知半导体器件中的应力能提高半导体器件性能。因此，为了提高半导体器件性能，在n型器件(例如NFET)和/或p型器件(例如PFET)的沟道中产生拉伸应力和/或压缩应力。然而，同样的应力成分，拉伸应力或压缩应力，对n型器件和p型器件的性能有不同的影响。
例如，已公知，当在硅层(或覆层)上形成器件时，在硅衬底顶上弛豫的SiGe层上外延生长该硅层，器件表现出更好的性能。在此系统中，硅覆层经受双轴拉伸应变。当在硅上外延生长时，未弛豫SiGe层具有与硅衬底匹配的晶格常数。通过弛豫(例如通过高温处理)，SiGe的晶格常数接近其本征晶格常数，该晶格常数比硅的晶格常数大。完全弛豫的SiGe层具有接近其本征值的晶格常数。当在其上外延生长硅时，硅层与弛豫SiGe层的更大的晶格常数匹配，这向在其上形成的硅层施加物理双轴应力(例如，膨胀)。向硅层施加的此物理应力对在其上形成的器件有益(例如，CMOS器件)，因为膨胀的硅层提高了n型器件的性能，而SiGe层中更高的Ge含量提高了p型器件的性能。
为了在集成电路(IC)芯片中最优化NFET和PFET的性能，对NFET和PFET应该分别设计和应用应力成分。即，因为对NFET的性能有益的应力类型通常对PFET的性能不利。更具体地说，当器件处于拉伸状态(例如：在平面器件的电流流动方向上)，NFET的操作性能增强，而PFET的操作性能降低。为了有选择地在NFET中产生拉伸应力并且在PFET中产生压缩应力，使用了有差别的工艺和不同的材料组合。
例如，建议用沟槽隔离结构分别在NFET和PFET中形成合适的应力。当使用该方法时，用于NFET器件的隔离区域包括第一隔离材料，该材料在NFET器件的纵向(例如，平行于电流流向)和横向(例如，垂直于电流流向)产生第一类型的机械应力。另外，为PFET提供第一隔离区域和第二隔离区域，并且这些隔离区域的每一个在PFET器件的横向和纵向中提供唯一的机械应力。
可选地，栅极侧壁上的衬里旨在有选择地引起适当的应力，在FET器件的沟道中引起合适的应力(例如，参见Ootsuka等人的IEDM 2000，P.575)。通过提供衬里，以比作为沟槽隔离填充技术的结果提供的应力更近的方式向器件提供合适的应力。
虽然这些方法提供的结构具有向NFET器件施加的拉伸应力和沿PFET器件的纵向施加的压缩应力，但是他们要求附加材料和/或更复杂的工艺，因此导致了更高的成本。另外，在此情况下施加的应力水平典型地为中等水平(即，在100s MPa的量级)。因此，希望提供更成本有效的和更简单的方法用于在NFET和PFET沟道中分别产生大的拉伸和压缩应力。
发明内容
本发明的第一方面，一种制造半导体结构的方法包括：在P型场效应晶体管(PFET)沟道区域和N型场效应晶体管(NFET)沟道区域中，同时形成具有下应力引起材料的分层结构。该方法还包括在PFET沟道区域的下应力引起材料上形成层时，保护NFET沟道区域，以减小在PFET沟道区域中的应力效应。在NFET沟道区域和PFET沟道区域中蚀刻岛，在NFET沟道区域中形成较高的所得应力成分。在PFET沟道区域的蚀刻部分中形成应力引起材料，在PFET沟道区域中形成与NFET沟道区域相反的应力成分。
本发明的另一方面，提供了一种制造半导体结构的方法。该方法包括在NFET区域和PFET区域中的衬底上形成应力引起层并且在NFET区域和PFET区域中的应力引起层上形成顶层。该顶层在NFET区域和PFET区域中的厚度不同。在PFET区域和NFET区域的侧面中蚀刻沟槽。蚀刻后，应力引起层的弹性边弛豫在沟道区域中产生拉伸应力。薄顶层在NFET区域中导致更高的拉伸应力，并且厚顶层在PFET区域中导致很小的拉伸应力。对NFET区域用第一材料并且对PFET区域用第二材料填充沟槽。第二材料在PFET区域中产生压缩应力。
另外，本发明的另一方面，提供了一种半导体结构，该结构包括在如Si层的衬底上形成的PFET和NFET沟道。PFET和NFET器件在沟道区域中具有相同材料的分层结构，在PFET沟道区域中相同材料的顶层厚于NFET沟道区域的顶层。PFET沟道区域和NFET沟道区域的沟槽不同。
附图说明
图1a到1i表示根据本发明形成器件的制造工艺；
图2a示出了根据本发明的NFET器件中的应力位置；
图2b示出了根据本发明的应力作为到NFET器件的栅极中心的纵向距离的函数的曲线图；
图3示出并且比较了根据本发明的平均沟道应力作为应力引起层，例如，假晶SiGe层上的硅层厚度的函数。
具体实施方式
本发明旨在半导体器件和制造方法，其在CMOS的NFET沟道中提供拉伸应力并且在PFET沟道中提供压缩应力。在本发明的实施例中，可以在相同的衬底上使用类似的工艺步骤获得在NFET和PFET沟道中形成的应力，从而降低了用于生产此类器件的整个材料的成本和时间。在实施例中，在形成NFET和PFET的区域中的硅层中形成沟道。然后分开并且有选择地处理该器件的沟道，这样以便一个器件被覆盖时，可以蚀刻并填充另一器件以便获得期望的性能。通过应用这些技术，分别在NFET和PFET的沟道中的覆盖外延生长层中导致拉伸或压缩应力。在一个实施例中，允许PFET的覆盖硅层比NFET相应的层生长的更厚。本发明的此制造工艺导致器件具有提高的沟道性能。
图1a到1i表示根据本发明形成器件的制造工艺。在图1a中，提供包括如绝缘体上硅(SOI)层10等的衬底。还可以在SOI 10上形成可选的掩埋氧化物层(BOX)12，在BOX 12上具有硅层14。图1a还示出了在Si层14上外延生长的假晶SiGe层16，随后具有另一外延硅层18。
在实施例中，层的厚度有不同的范围。例如BOX 12在1200到1600之间，硅层14在10到1000之间，优选厚度为700。另外，SiGe层16可以在50到500，90到500之间，优选400。然而，应该明白，这些层的厚度可以依赖于器件的不同设计参数改变。
在实施中，以常规方式外延生长假晶SiGe层16。Ge含量与Si含量的比率大于0％，本发明的预期范围在20％-30％之间。可以通过任何选择性外延硅形成技术以常规方式沉积假晶SiGe层16上的硅层18，例如可以使用快速热化学气相沉积(RTCVD)或分子束外延(MBE)以外延生长器件优质硅。
图1b示出了由浅沟槽隔离(STI)20形成的分离沟道(或器件区域)。通过包括光刻和蚀刻步骤的常规构图工艺形成绝缘沟槽20。例如，对掩埋氧化物使用衬垫氧化，衬垫氮化物沉积，基于光刻的构图，叠层的反应离子蚀刻(RIE)的标准技术，来构图叠层14，16，18以形成STI 20。然后，可以使用例如衬里沉积、填充沉积和化学机械抛光，来形成STI 20。STI形成工艺在技术上已公知。
图1c示出了对PFET叠层的Si层16的修改。在此工艺中，在NFET区域上设置掩模22。在PFET区域的Si层18上有选择地生长外延Si，结果生成无缝新Si层24。新形成的层24与NFET区域中的顶层Si层16相比允许其厚度不同。优选，Si层24比NFET区域的Si层16厚，对于Si层24具有在200到600的厚度范围，在NFET Si层18和PFET Si层24层之间具有至少100的差别。
图1d到1i示出栅极结构的制造工艺，包括分别用于NFET和PFET沟道的源极和漏极(S/D)区域。参考图1d，通过包括光刻和蚀刻步骤的常规构图工艺在NFET和PFET区域两者中构图SiN覆盖的(28)多晶硅栅极26。通过实例，在该结构上形成由SiN 28保护层覆盖的多晶硅层。应用光刻工艺，该工艺需要在SiN覆盖的多晶硅层上应用光致抗蚀剂，向辐射图形曝光光致抗蚀剂，并且利用常规的抗蚀剂显影剂显影图形。在光刻步骤之后，可以使用如RIE、等离子体蚀刻、离子束蚀刻或激光烧蚀的常规蚀刻工艺，以将图形转移到NFET区域和PFET区域的有源区域以形成多晶硅栅极26。然后形成用作蚀刻停止材料的侧壁隔离物30。同样以常规形式形成覆层28和多晶硅侧壁隔离物30。在此工艺中，在该结构上沉积牺牲体材料。在一个实施例中，牺牲材料是形成SiN元件28和30的氮化物材料(例如Si3N4)。可以以常规方式形成层28，30，例如通过使用硅烷源的化学气相沉积(CVD)。适合用于形成氮化物层的其它技术包括LPCVD，和常压CVD(APCVD)。分别覆盖NFET和PFET区域中的下层16和24的多晶硅栅极26及其两个侧壁隔离物30的尺寸在400到1000的范围内，因为隔离物的优选尺寸为100，所以剩下的栅极26的尺寸在200到800的范围内，NFET和PFET区域两者都优选400。应该明白，这适用于围绕标称值中心的栅极长度(技术上的最小尺寸)。例如，对于65nm技术，400是合理的栅极长度。
参考图1e，在NFET沟道中制备S/D沟槽前在PFET区域上设置硬掩模22。向下蚀刻NFET中邻近由层16，18，28，30形成的叠层的区域，希望直到硅层14，即使有些过度蚀刻也是可以接受的。此蚀刻在SiGe层边缘引起弹性驰豫，结果在上硅层上形成拉伸应变。
图1f示出了在由SiGe和Si层形成的栅极岛之间的S/D沟槽中，选择生长外延硅32后的器件。以上述尺度看，最终的栅极岛导致500到1000之间的纵向尺寸，优选800。在NFET区域的栅极岛中的假晶SiGe层16向在沟道区域中的外延生长硅18上施加拉伸应力，导致提高的NFET器件性能。
图1g，类似于图1d，示出了PFET区域S/D的制备。在此工艺步骤中，在NFET区域上设置保护硬掩模22，并且向下蚀刻邻近由层16，24，26，28，30形成的叠层的S/D沟槽，希望直到硅层14。由于SiGe层上的上硅层比NFET区域的硅层厚，因此在PFET区域的硅沟道上施加的拉伸应力较小。
图1h示出了PFET器件的已填充S/D沟槽。相对于NFET区域，这些沟槽由外延生长的SiGe 34填充，在一个实施例中，与层24基本齐平。这些元件的纵向尺度类似于上述用于NFET区域的尺度。由层16和24形成的PFET栅极岛具有500到1000之间的最终尺寸，优选800。SiGe材料34在PFET器件的硅沟道上引起压缩应力，结果提高了PFET器件的性能。
图1i示出已制造的CMOS器件。eSiGe材料34相对于沟槽中硅和锗的总量的比率可以在高于0％的任何锗之间变化。
图2a示出了根据本发明的NFET器件中的应力位置。如图2a所示，拉伸应力存在于NFET沟道中，未驰豫SiGe区域处在压缩下。更具体地说，在本发明的结构中，SiGe层16的晶格结构与下硅层14的晶格结构匹配。这导致SiGe层16和周围的区域处在压缩应力下。在蚀刻S/D沟槽(或阱)后，SiGe层的边缘将进行弹性弛豫，导致沟道中硅层18上的拉伸应力。
图2b示出了应力作为到NFET器件栅极中心的纵向距离的函数曲线。对于锗含量为20％，并且Si层18的厚度为200的器件，本发明提供300MPa范围内的拉伸应力。在一个实施例中，在Si层18中纵向应力成分(从源极到漏极的电流流动方向上的应力)的优选范围优选大于100MPa。图2b还显示拉伸应力横向延伸到外延生长的硅元件32中，并且高于100MPa的拉伸应力向上到达元件32中的150处，并且在从栅极边缘的250处达到弛豫(没有引起应力)。
图3示出了位于上面的硅层18和24的纵向上的应力曲线。如此曲线所示，SiGe层的Ge含量的范围从20％到30％。NFET中的上层硅层的厚度范围从约200到400。值得注意，在高达200的Si层中获得了高应力(高于200MPa)，其范围依赖于层16中Ge的含量在约275MPa到415MPa之间，然后，当硅层变为400厚时，弛豫为基本无应变区域。因此，对于在PFET中的SiGe层上的硅层优选为400或更厚。
因此，在本发明的结构中，在NFET沟道中形成拉伸应力并且在PFET沟道中形成压缩应力。通过引入这样的应力，可以获得器件的高性能。另外，用本发明的工艺，可以减少制造成本从而导致高效益。
虽然以实施例的方式描述了本发明，本领域的技术人员将认识到实践本发明可以在附加权利要求的精神和范围内进行修改。例如，本发明可以容易地应用到体衬底上。

Claims (20)

1.一种制造半导体结构的方法：
在P型场效应晶体管(PFET)沟道区域和N型场效应晶体管(NFET)沟道区域中，同时形成具有下应力引起材料的分层结构；
在所述PFET沟道区域的下应力引起材料上形成层时，保护所述NFET沟道区域；以及
在所述NFET沟道区域和所述PFET沟道区域中蚀刻岛，在所述NFET沟道区域中形成较高的所得应力成分；以及
在所述PFET沟道区域的蚀刻部分中形成应力引起材料，在所述PFET沟道区域中形成与所述NFET沟道区域相反的应力成分。
2.根据权利要求1的方法，其中具有下应力引起材料的所述分层结构包括Si顶层，SiGe底层，其中所述Si顶层对于所述NFET或所述PFET沟道区域具有不同的厚度。
3.根据权利要求1的方法，其中所述PFET沟道区域厚于所述NFET沟道区域。
4.根据权利要求2的方法，其中所述PFET沟道区域具有厚于所述NFET沟道区域的顶层。
5.根据权利要求1的方法，其中具有下应力引起材料的所述分层结构包括Si顶层和SiGe底层，其中在所述PFET沟道区域中的所述Si顶层厚于在所述NFET沟道区域中的所述Si顶层。
6.根据权利要求5的方法，其中所述SiGe的锗含量约为20％到30％。
7.根据权利要求5的方法，其中在所述PFET沟道区域中所述Si顶层的厚度约为400。
8.根据权利要求1的方法，其中在所述PFET沟道区域的蚀刻部分中形成所述应力引起材料之前，在所述PFET沟道区域中的所述Si层的厚度基本上减小了在所述PFET沟道区域中的拉伸应力。
9.根据权利要求8的方法，其中在所述PFET沟道区域的蚀刻部分中的所述应力引起材料在所述PFET沟道区域中产生压缩应力。
10.根据权利要求1的方法，其中在保护所述NFET沟道区域时提供所述PFET沟道区域的所述蚀刻和形成步骤。
11.一种制造半导体结构的方法：
在NFET区域和PFET区域中的衬底上形成应力引起层；
在所述NFET区域和所述PFET区域中的所述应力引起层上形成顶层，所述顶层在所述NFET区域和所述PFET区域中的厚度不同；
在所述PFET区域和所述NFET区域的侧面中蚀刻沟槽，所述沟槽的所述蚀刻在所述NFET区域中产生拉伸应力并且在所述PFET区域中产生减小的拉伸应力；以及
对所述NFET区域用第一材料并且对所述PFET区域用第二材料填充所述沟槽，所述第二材料在所述PFET区域中形成压缩应力。
12.根据权利要求11的方法，其中通过在所述PFET区域上沉积或生长更多的材料，在所述PFET区域中形成较厚的顶层，同时保护所述NFET区域，形成所述PFET区域的所述顶层。
13.根据权利要求12的方法，其中在所述PFET区域中的所述较厚的顶层与在所述NFET区域中的所述顶层的材料相同，在所述PFET区域中所述沟槽的蚀刻后，所述PFET区域中的较厚的层基本上减少了所述沟道中由所述应力引起层产生的应力。
14.根据权利要求11的方法，其中所述应力引起材料和所述第二材料是硅锗合成物。
15.根据权利要求14的方法，其中所述顶层和所述第一材料是硅。
16.根据权利要求11的方法，其中所述顶层的厚度在50到500的范围内变化。
17.根据权利要求11的方法，其中所述第二材料是硅锗合成物。
18.一种半导体结构，包括PFET器件和NFET器件，所述PFET器件和所述NFET器件在沟道区域中具有相同材料的分层结构，在所述PFET沟道区域中所述相同材料的顶层厚于所述NFET沟道区域的顶层，并且所述PFET沟道区域和所述NFET沟道区域的沟槽不同。
19.根据权利要求18的结构，其中与所述NFET沟道区域的应力相比，所述PFET沟道区域中的所述顶层在沟槽蚀刻后减少了由应力引起下层产生的应力。
20.根据权利要求19的结构，其中所述PFET沟道区域的应力引起层和所述沟槽是硅锗合成物。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101924107A (zh) * 2010-07-15 2010-12-22 电子科技大学 一种应力增强的cmos晶体管结构
CN102064177A (zh) * 2010-11-11 2011-05-18 电子科技大学 一种应力放大的cmos晶体管结构
CN102456720A (zh) * 2010-10-20 2012-05-16 国际商业机器公司 高k金属栅极半导体晶体管的结构
WO2013177725A1 (zh) * 2012-05-28 2013-12-05 中国科学院微电子研究所 半导体器件及其制造方法
CN109065610A (zh) * 2018-08-21 2018-12-21 电子科技大学 一种屏蔽栅器件
CN113496954A (zh) * 2020-04-08 2021-10-12 长鑫存储技术有限公司 存储器的形成方法及存储器

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7186622B2 (en) * 2004-07-15 2007-03-06 Infineon Technologies Ag Formation of active area using semiconductor growth process without STI integration
US7691698B2 (en) * 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US7525161B2 (en) * 2007-01-31 2009-04-28 International Business Machines Corporation Strained MOS devices using source/drain epitaxy
JP4896789B2 (ja) * 2007-03-29 2012-03-14 株式会社東芝 半導体装置の製造方法
KR100944339B1 (ko) * 2008-02-29 2010-03-02 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
FR2934085B1 (fr) * 2008-07-21 2010-09-03 Commissariat Energie Atomique Procede pour containdre simultanement en tension et en compression les canaux de transistors nmos et pmos respectivement
US8129247B2 (en) * 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8097515B2 (en) * 2009-12-04 2012-01-17 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US8143113B2 (en) 2009-12-04 2012-03-27 International Business Machines Corporation Omega shaped nanowire tunnel field effect transistors fabrication
US8173993B2 (en) * 2009-12-04 2012-05-08 International Business Machines Corporation Gate-all-around nanowire tunnel field effect transistors
US8384065B2 (en) * 2009-12-04 2013-02-26 International Business Machines Corporation Gate-all-around nanowire field effect transistors
US8455334B2 (en) * 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US8722492B2 (en) 2010-01-08 2014-05-13 International Business Machines Corporation Nanowire pin tunnel field effect devices
US8324940B2 (en) 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices
US8361907B2 (en) 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8324030B2 (en) 2010-05-12 2012-12-04 International Business Machines Corporation Nanowire tunnel field effect transistors
US8835231B2 (en) 2010-08-16 2014-09-16 International Business Machines Corporation Methods of forming contacts for nanowire field effect transistors
US8536563B2 (en) 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
US8647941B2 (en) * 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8735303B2 (en) 2011-11-02 2014-05-27 Globalfoundries Inc. Methods of forming PEET devices with different structures and performance characteristics
FR2986369B1 (fr) * 2012-01-30 2016-12-02 Commissariat Energie Atomique Procede pour contraindre un motif mince et procede de fabrication de transistor integrant ledit procede
US8642430B2 (en) * 2012-04-09 2014-02-04 GlobalFoundries, Inc. Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers
JP6251604B2 (ja) * 2013-03-11 2017-12-20 ルネサスエレクトロニクス株式会社 フィンｆｅｔ構造を有する半導体装置及びその製造方法
US9099565B2 (en) * 2013-10-08 2015-08-04 Stmicroelectronics, Inc. Method of making a semiconductor device using trench isolation regions to maintain channel stress
US9018057B1 (en) * 2013-10-08 2015-04-28 Stmicroelectronics, Inc. Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
EP2930752A3 (en) * 2014-04-08 2016-01-20 IMEC vzw Method for manufacturing a transistor device
US9559120B2 (en) 2015-07-02 2017-01-31 International Business Machines Corporation Porous silicon relaxation medium for dislocation free CMOS devices
US9472671B1 (en) * 2015-10-31 2016-10-18 International Business Machines Corporation Method and structure for forming dually strained silicon
US9379110B1 (en) * 2015-11-25 2016-06-28 International Business Machines Corporation Method of fabrication of ETSOI CMOS device by sidewall image transfer (SIT)
US10056382B2 (en) 2016-10-19 2018-08-21 International Business Machines Corporation Modulating transistor performance

Family Cites Families (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602841A (en) * 1970-06-18 1971-08-31 Ibm High frequency bulk semiconductor amplifiers and oscillators
US4853076A (en) * 1983-12-29 1989-08-01 Massachusetts Institute Of Technology Semiconductor thin films
US4665415A (en) * 1985-04-24 1987-05-12 International Business Machines Corporation Semiconductor device with hole conduction via strained lattice
EP0219641B1 (de) * 1985-09-13 1991-01-09 Siemens Aktiengesellschaft Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
US4858213A (en) * 1986-08-08 1989-08-15 Dictaphone Corporation Display for modular dictation/transcription system
US4958213A (en) 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5459346A (en) * 1988-06-28 1995-10-17 Ricoh Co., Ltd. Semiconductor substrate with electrical contact in groove
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5108843A (en) * 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5310446A (en) * 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5060030A (en) * 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
US5081513A (en) * 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5371399A (en) * 1991-06-14 1994-12-06 International Business Machines Corporation Compound semiconductor having metallic inclusions and devices fabricated therefrom
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6008126A (en) * 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5557122A (en) * 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
KR100213196B1 (ko) * 1996-03-15 1999-08-02 윤종용 트렌치 소자분리
US6403975B1 (en) * 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
US5880040A (en) * 1996-04-15 1999-03-09 Macronix International Co., Ltd. Gate dielectric based on oxynitride grown in N2 O and annealed in NO
US5861651A (en) * 1997-02-28 1999-01-19 Lucent Technologies Inc. Field effect devices and capacitors with improved thin film dielectrics and method for making same
US5940736A (en) * 1997-03-11 1999-08-17 Lucent Technologies Inc. Method for forming a high quality ultrathin gate oxide layer
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6025280A (en) * 1997-04-28 2000-02-15 Lucent Technologies Inc. Use of SiD4 for deposition of ultra thin and controllable oxides
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
JP3139426B2 (ja) * 1997-10-15 2001-02-26 日本電気株式会社 半導体装置
US6066545A (en) * 1997-12-09 2000-05-23 Texas Instruments Incorporated Birdsbeak encroachment using combination of wet and dry etch for isolation nitride
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR100275908B1 (ko) * 1998-03-02 2000-12-15 윤종용 집적 회로에 트렌치 아이솔레이션을 형성하는방법
US6165383A (en) * 1998-04-10 2000-12-26 Organic Display Technology Useful precursors for organic electroluminescent materials and devices made from such materials
US6361885B1 (en) * 1998-04-10 2002-03-26 Organic Display Technology Organic electroluminescent materials and device made from such materials
US5989978A (en) * 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JP4592837B2 (ja) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6319794B1 (en) * 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
US6235598B1 (en) * 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
US6117722A (en) * 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6255169B1 (en) * 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
US6326082B1 (en) * 1999-03-11 2001-12-04 Agfa-Gevaert Security document comprising a mixture of polyurethanes
US6284626B1 (en) * 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6281532B1 (en) * 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6656822B2 (en) * 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
US6362082B1 (en) 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
TW426940B (en) * 1999-07-30 2001-03-21 United Microelectronics Corp Manufacturing method of MOS field effect transistor
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6284623B1 (en) * 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
US6476462B2 (en) * 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6531369B1 (en) * 2000-03-01 2003-03-11 Applied Micro Circuits Corporation Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US6368931B1 (en) * 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
US6493497B1 (en) 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6501121B1 (en) 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
US7312485B2 (en) * 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6563152B2 (en) * 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
US20020086497A1 (en) * 2000-12-30 2002-07-04 Kwok Siang Ping Beaker shape trench with nitride pull-back for STI
US6265317B1 (en) * 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
US6403486B1 (en) * 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
US6531740B2 (en) * 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6498358B1 (en) 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6908810B2 (en) * 2001-08-08 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
US6974735B2 (en) * 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
AU2002349881A1 (en) 2001-09-21 2003-04-01 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20030057184A1 (en) * 2001-09-22 2003-03-27 Shiuh-Sheng Yu Method for pull back SiN to increase rounding effect in a shallow trench isolation process
US6656798B2 (en) * 2001-09-28 2003-12-02 Infineon Technologies, Ag Gate processing method with reduced gate oxide corner and edge thinning
US6635506B2 (en) * 2001-11-07 2003-10-21 International Business Machines Corporation Method of fabricating micro-electromechanical switches on CMOS compatible substrates
US6600170B1 (en) * 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
US6621392B1 (en) * 2002-04-25 2003-09-16 International Business Machines Corporation Micro electromechanical switch having self-aligned spacers
US7388259B2 (en) * 2002-11-25 2008-06-17 International Business Machines Corporation Strained finFET CMOS device structures
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US6825529B2 (en) * 2002-12-12 2004-11-30 International Business Machines Corporation Stress inducing spacers
US6974981B2 (en) 2002-12-12 2005-12-13 International Business Machines Corporation Isolation structures for imposing stress patterns
US6887798B2 (en) 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7279746B2 (en) 2003-06-30 2007-10-09 International Business Machines Corporation High performance CMOS device structures and method of manufacture
US7119403B2 (en) * 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US8008724B2 (en) * 2003-10-30 2011-08-30 International Business Machines Corporation Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7122849B2 (en) * 2003-11-14 2006-10-17 International Business Machines Corporation Stressed semiconductor device structures having granular semiconductor material
US7247912B2 (en) * 2004-01-05 2007-07-24 International Business Machines Corporation Structures and methods for making strained MOSFETs
US7205206B2 (en) * 2004-03-03 2007-04-17 International Business Machines Corporation Method of fabricating mobility enhanced CMOS devices
US7504693B2 (en) * 2004-04-23 2009-03-17 International Business Machines Corporation Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering
US7354806B2 (en) * 2004-09-17 2008-04-08 International Business Machines Corporation Semiconductor device structure with active regions having different surface directions and methods
US7465972B2 (en) * 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7282402B2 (en) * 2005-03-30 2007-10-16 Freescale Semiconductor, Inc. Method of making a dual strained channel semiconductor device
US7402476B2 (en) * 2005-06-15 2008-07-22 Freescale Semiconductor, Inc. Method for forming an electronic device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101924107A (zh) * 2010-07-15 2010-12-22 电子科技大学 一种应力增强的cmos晶体管结构
CN101924107B (zh) * 2010-07-15 2012-09-26 电子科技大学 一种应力增强的cmos晶体管结构
CN102456720A (zh) * 2010-10-20 2012-05-16 国际商业机器公司 高k金属栅极半导体晶体管的结构
CN102456720B (zh) * 2010-10-20 2016-04-06 国际商业机器公司 高k金属栅极半导体晶体管的结构
CN102064177A (zh) * 2010-11-11 2011-05-18 电子科技大学 一种应力放大的cmos晶体管结构
CN102064177B (zh) * 2010-11-11 2012-09-26 电子科技大学 一种应力放大的cmos晶体管结构
CN103456782A (zh) * 2012-05-28 2013-12-18 中国科学院微电子研究所 半导体器件及其制造方法
US9281398B2 (en) 2012-05-28 2016-03-08 The Institute of Microelectronics, Chinese Academy of Science Semiconductor structure and method for manufacturing the same
WO2013177725A1 (zh) * 2012-05-28 2013-12-05 中国科学院微电子研究所 半导体器件及其制造方法
CN103456782B (zh) * 2012-05-28 2016-12-14 中国科学院微电子研究所 半导体器件及其制造方法
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