CN101051950A - Optical fiber communication network route signal processor based on FPGA and using method - Google Patents
Optical fiber communication network route signal processor based on FPGA and using method Download PDFInfo
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- CN101051950A CN101051950A CNA2006100671336A CN200610067133A CN101051950A CN 101051950 A CN101051950 A CN 101051950A CN A2006100671336 A CNA2006100671336 A CN A2006100671336A CN 200610067133 A CN200610067133 A CN 200610067133A CN 101051950 A CN101051950 A CN 101051950A
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Abstract
The signal processor thereof comprises an input unit, an input signal buffer circuit, a signal processing circuit, an I/O state indication circuit, an output signal buffer circuit and an output unit. The input unit comprises an input keyboard, a computer communication interface, a FPGA configuration chip and an upper layer communication interface. The inputted signals are read into the buffer memory or high speed RAM in the FPGA; a CPU is integrated into the signal processing circuit in order to process the inputted signals, to extract route signals, to convert the extracted route signals to driving signals, and to save the driving signal into output buffer. The output unit is used to read out the driving signals from the buffer, and after boosting the strength of the driving signals, sends them to the multi-channel photoelectron chip.
Description
Technical field
The present invention relates to technical field of optical fiber communication, particularly based on optical fiber communication network route signal processor and the using method of FPGA.
Background technology
Dense wave division multipurpose (DWDM) technology is a kind of effective ways that solve broadband, high capacity optical fiber network communication.The multi-channel photoelectronic chip is the critical component of structure dwdm system.Research at the multi-channel photoelectronic chip, in producing and using, need a kind of specific testing equipment, this equipment can accurately receive and handle in the optical communication network route signal of each packet in the Networks of Fiber Communications, and be translated into the receptible drive signal of multi-channel photoelectronic chip drive circuit, drive the multi-channel photoelectronic chip and finish the switching of light path. aid in the optical parameter measuring instrument device, this equipment can also be applied to detect the various optics of each port of multi-channel photoelectronic chip and the composite characteristic parameter of electricity, possesses higher detection efficient, also simple to operate simultaneously, be easy to carry, be fit to common operator and maintenance use fast.Trade information up to now and open source literature show still do not have the testing apparatus that satisfies above-mentioned requirements in present existing test mode and the testing equipment.Mainly there is following defective in currently used testing apparatus: the one, and the equipment heaviness is not easy to carry, and especially is not easy to the quick maintenance of fault in the practical application; The 2nd, complicated operation need possess abundant optics and electricity knowledge ability correct measurement desired parameters; The 3rd, to finish by artificial calculating the judgement of light path, be not suitable for the test of extensive multichannel chip; The 4th, test process needs expensive signal generator, and these equipment costs are very high, and also very high to the requirement of test environment; The 5th, the speed of some equipment can not reach the test request of high speed multi-channel photoelectronic chip, can not truly reflect the real work situation of chip in optical communication network.
Summary of the invention
The object of the present invention is to provide a kind of Networks of Fiber Communications route signal processing unit and method, its have cost low, be convenient for carrying, simple to operate, speed is fast, processing mode advantage flexibly.
The invention still further relates in the Networks of Fiber Communications based on FPGA multi-channel photoelectronic chip characteristics method of measurement, and multi-channel photoelectronic failure of chip detection method.
Designed a kind of Networks of Fiber Communications route signal processing unit according to above-mentioned purpose based on FPGA, comprise key input section, with Computer Communications Interface, the FPGA configuring chip, with higher level's circuit communication interface, input signal buffer circuit, signal processing circuit, the input/output state indicating circuit, output signal buffer circuit and output.All circuit can be integrated in a high-speed printed circuit board (PCB) and go up realization.The device that device is adopted is the TTL or the CMOS interface device of standard, can adopt DC power supply or powered battery mode, also can pass through computer USB confession; The routing iinformation of Networks of Fiber Communications can directly be taked by keyboard input, utilizes the software control acquisition by private communication interface and computer or higher level's circuit communication or by the FPGA configuring chip.Routing iinformation is read into input-buffer, and input-buffer is high speed SDRAM and FPGA ram in slice, and signal processing circuit can adopt the FPGA with soft nucleus CPU function, thereby improves data-handling capacity and processing speed greatly.Signal processing circuit reads the routing iinformation data from input-buffer, be processed into the drive signal that the multi-channel photoelectronic chip drive circuit can discern and the drive signal of input and output indicating section, and it is sent into output buffers output.The input and output indicating section can be light-emitting diode or LED, and it indicates the port information of the pairing multi-channel photoelectronic chip of route signal of input.Drive signal in the output buffers is loaded into the drive circuit of multi-channel photoelectronic chip after the output level conversion, finish the switching of light path.
The present invention is by the powerful data-handling capacity of fpga chip soft nucleus CPU, routing iinformation conversion of signals in the optical communication network is become the drive signal of multi-channel photoelectronic chip controls and drive circuit, can be for chip provide test signal, control multichannel chip status is realized the switching of light path.Auxiliary with optical testing instrument such as power meter, oscilloscope etc., can detect the luminous power P that each output port is exported easily
oThereby, can accurately simulate the operating state of multi-channel photoelectronic chip in optical communication network, and in time detect the normal attribute parameter of multi-channel photoelectronic chip, as Output optical power with the P that concerns of operating current
o-I
OpCurve, loss and operating current concern Loss-I
OpCurve, and crosstalk, operating power, speed etc.; Simple to operate, improve detection efficiency greatly.What is more important, this equipment is by means of modern FPGA technology and advanced soft nucleus CPU technology, the height of having realized whole system at low cost is integrated, and can adopt multiple supply power mode that power supply is provided, whole device volume is little, be convenient for carrying, be particularly suitable for the on-the-spot maintenance fast of fault in the practical application.
The device that described device adopts is the TTL or the CMOS interface device of standard, and its supply power mode can adopt DC power supply or powered battery, also can take computer USB confession.
The route signal that need handle can adopt by key input section directly imports acquisition.
The route signal that needs to handle can be by coming to obtain with compunication with Computer Communications Interface.
The route signal that needs to handle can adopt the FPGA configuring chip to produce automatically by software control.
The route signal that needs to handle can be by coming to obtain with higher level's circuit communication with higher level's circuit communication interface.
The whole bag of tricks that is adopted can use separately, also can be used in combination.When being used in combination, can adopt the priority and the interrupt condition of software control distinct methods.
Random access memory ram can be adopted in input/output signal buffer circuit (5) and (8), flash memory FLASH, or the high-speed RAM of FPGA inside constitutes.
Input/output state indicating section (7) adopts light emitting diode matrix LED or LCDs.
Described route signal treatment circuit is an on-site programmable gate array FPGA, comprises command register, command decoder, data register and soft nuclear central processing unit etc.
The FPGA that is adopted has the ability of supporting the soft nucleus CPU processor.
The route signal that the present invention can be applicable in multi-channel photoelectronic chip measuring technique and the malfunction monitoring produces and processing unit.
Description of drawings
For further specifying content of the present invention and characteristics, below in conjunction with drawings and Examples the present invention is done a detailed description, wherein:
Fig. 1 is the block diagram of testing apparatus of the present invention.
Fig. 2 is the hardware designs PCB schematic diagram of one embodiment of the invention.
Fig. 3 is that the present invention carries out the workflow schematic diagram of multi-channel photoelectronic chip characteristics when measuring.
Fig. 4 is the workflow schematic diagram of the present invention when being applied to fault detect in the real work.
Embodiment
From Fig. 1 as seen, key input section of the present invention (1), with Computer Communications Interface (2), FPGA configuring chip (3), with higher level's circuit communication interface (4), input signal buffer circuit (5), signal processing circuit (6), input/output state indicating circuit (7), output signal buffer circuit (8) and output (9).All circuit can be integrated in a high-speed printed circuit board (PCB) and go up realization.Wherein, importation (1) (2) (3) (4) is connected with input signal buffer circuit (5) respectively, signal processing circuit (6) and input signal buffer circuit (5), input/output state indicating circuit (7), output signal buffer circuit (8) is connected with output (9).
Fig. 2 has provided the circuit diagram of an embodiment of the described device of Fig. 1.Wherein, signal processing circuit is the FPGA of soft nucleus CPU of can programming, and has comprised register, adder etc.In order to satisfy the needs of high speed test, input-buffer has adopted high speed SDRAM, and the route signal of importing via keyboard or computer communication port can enter high speed SDRAM immediately and obtain processing.Soft nucleus CPU directly reads in and handles the data among the SDRAM.Adopt FPGA configuring chip software control input route signal and by communicating input route signal mode with higher level's circuit, the RAM IP kernel that input-buffer utilizes FPGA inside to provide is realized.The then unified RAM IP kernel that adopts FPGA inside to provide of output buffers is realized.Be light emitting diode matrix LED in this example of input/output state indicating circuit, indicate the input/output port of the pairing multi-channel photoelectronic chip of routing iinformation, the convenient operating state of judging multi-channel photoelectronic chip this moment and light path the device cell of process.In the present embodiment, FPGA has adopted the Cyclone II series of altera corp, and what corresponding configuring chip adopted is the EPCS1 chip.The optics auxiliary equipment that is adopted in the present embodiment is power meter, oscilloscope etc.The multi-channel photoelectronic chip that is adopted is the thermo-optic switch array that has drive circuit.
The job order that Fig. 3 has provided the embodiment of the invention when carrying out thermo-optic switch array/modulator feature measurement.When the present invention is applied to thermo-optic switch array/modulator feature measurement, multi-channel photoelectronic chip characteristics method of measurement, should follow following job step:
1) sent route signal or obtained route signal with computer or higher level's circuit communication by keyboard, also can produce route signal by the FPGA control chip, this route signal is read into the input signal buffer circuit;
2) route signal is converted to the driving command of multi-channel photoelectronic chip drive circuit after signal processing circuit is handled;
3) according to driving command, the driver of each chip unit of driving multi-channel photoelectronic chip of corresponding driving circuit changes the light signal state, utilizes optical measuring apparatus to monitor the power output of each output port;
4) by calculate the loss can obtain chip, crosstalk, characteristic such as power consumption;
5) zero clearing is sent the zero clearing order by keyboard, and device is placed init state;
6) detect whether do not survey port in addition, if all surveyed, EOT, otherwise repeat above step.
Fig. 4 has provided the workflow diagram the when embodiment of the invention is carried out fault detect.When the present invention is applied to thermo-optic switch array/modulator fault detect, multi-channel photoelectronic failure of chip detection method, should follow following job step:
1) sent route signal or obtained route signal with computer or higher level's circuit communication by keyboard, also can produce route signal by the FPGA control chip, this route signal is read into the input signal buffer circuit.
2) route signal is converted to the driving command of multi-channel photoelectronic chip drive circuit after signal processing circuit is handled.
3) detect the output port power output;
4) with each port power output during with the device operate as normal index compare, if performance requirement is satisfied in output, illustrate that chip units all on this light path is normally, returns step 1;
5) if output can not be satisfied the operate as normal index, obtain another group route signal, make its gating light path and have cross unit (being total certain switch element of gating light path) by the gating light path that last one group of route signal is determined;
6) with each port power output during with the device operate as normal index compare, if performance requirement is satisfied in output, then in twice measuring process shared cross unit be the operate as normal unit, otherwise the cross unit of two light paths may be trouble unit.
7) repeat 5 repeatedly) and 6), if it is all undesired to contain all light paths of this trouble unit, determine that then this element is a trouble unit.
In sum, the optical fiber communication network route signal processor that the present invention is based on FPGA has the following advantages at least:
1. the optical fiber communication network route signal processor that the present invention is based on FPGA is simple in structure, technical maturity, and cost of manufacture is low.
2. the optical fiber communication network route signal processor that the present invention is based on FPGA is simple to operate, and volume is little, is easy to carry, and can adopts multiple mode to power, and this advantage is particularly important in physical fault detects.
3. the optical fiber communication network route signal processor that the present invention is based on FPGA has been introduced the elementary cell that FPGA handles as circuit signal, greatly reduces cost and is easy to and realize.
4. the optical fiber communication network route signal processor that the present invention is based on FPGA is aided with optical measuring apparatus, can disposablely finish the test of multi-channel photoelectronic chip multinomial performance index, the testing efficiency height.
The above; only be embodiments of the invention; be not that the present invention is done any pro forma restriction; every according to the technology of the present invention essence to any simple modification, equivalent variations and modification that above embodiment did; all still belong within the technical solution of the present invention scope, so protection scope of the present invention is when being as the criterion with claims.
Claims (13)
1. optical fiber communication network route signal processor based on FPGA, comprise key input section (1), with Computer Communications Interface (2), FPGA configuring chip (3), with higher level's circuit communication interface (4), input signal buffer circuit (5), signal processing circuit (6), input/output state indicating circuit (7), output signal buffer circuit (8) and output (9), all circuit can be integrated on the high-speed printed circuit board and realize, wherein, importation (1) (2) (3) (4) is connected with input signal buffer circuit (5) respectively, signal processing circuit (6) and input signal buffer circuit (5), input/output state indicating circuit (7), output signal buffer circuit (8) is connected with output (9).
2. the optical fiber communication network route signal processor based on FPGA according to claim 1, it is characterized in that, the device that described device adopts is the TTL or the CMOS interface device of standard, its supply power mode can adopt DC power supply or powered battery, also can take computer USB confession.
3. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that, the route signal that need handle can adopt by key input section directly imports acquisition.
4. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that, the route signal that needs to handle can be by coming to obtain with compunication with Computer Communications Interface.
5. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that, the route signal that needs to handle can adopt the FPGA configuring chip to produce automatically by software control.
6. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that, the route signal that needs to handle can be by coming to obtain with higher level's circuit communication with higher level's circuit communication interface.
7. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that, claim 3, and 4,5,6 the whole bag of tricks that adopted can use separately, also can be used in combination.When being used in combination, can adopt the priority and the interrupt condition of software control distinct methods.
8. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that, random access memory ram can be adopted in input/output signal buffer circuit (5) and (8), flash memory FLASH, or the high-speed RAM of FPGA inside constitutes.
9. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that, input/output state indicating section (7) adopts light emitting diode matrix LED or LCDs.
10. the optical fiber communication network route signal processor based on FPGA according to claim 1, it is characterized in that, described route signal treatment circuit is an on-site programmable gate array FPGA, comprises command register, command decoder, data register and soft nuclear central processing unit.
11. the optical fiber communication network route signal processor based on FPGA according to claim 1 is characterized in that the FPGA that is adopted has the ability of supporting the soft nucleus CPU processor.
12. a multi-channel photoelectronic chip characteristics method of measurement, its step is as follows:
1) sent route signal or obtained route signal with computer or higher level's circuit communication by keyboard, also can produce route signal by the FPGA control chip, this route signal is read into the input signal buffer circuit;
2) route signal is converted to the driving command of multi-channel photoelectronic chip drive circuit after signal processing circuit is handled;
3) according to driving command, the driver of each chip unit of driving multi-channel photoelectronic chip of corresponding driving circuit changes the light signal state, utilizes optical measuring apparatus to monitor the power output of each output port;
4) by calculate the loss can obtain chip, crosstalk, power consumption characteristics;
5) zero clearing is sent the zero clearing order by keyboard, and device is placed init state;
6) detect whether do not survey port in addition, if all surveyed, EOT, otherwise repeat above step.
13. a multi-channel photoelectronic failure of chip detection method, its step is as follows:
1) sent route signal or obtained route signal with computer or higher level's circuit communication by keyboard, also can produce route signal by the FPGA control chip, this route signal is read into the input signal buffer circuit;
2) route signal is converted to the driving command of multi-channel photoelectronic chip drive circuit after signal processing circuit is handled;
3) detect the output port power output;
4) with each port power output during with the device operate as normal index compare, if performance requirement is satisfied in output, illustrate that chip units all on this light path is normally, returns step 1;
5) if output can not be satisfied the operate as normal index, obtain another group route signal, make its gating light path and have cross unit by the definite gating light path of last one group of route signal;
6) with each port power output during with the device operate as normal index compare, if performance requirement is satisfied in output, then in twice measuring process shared cross unit be the operate as normal unit, otherwise the cross unit of two light paths may be trouble unit;
7) repeat 5 repeatedly) and 6), if it is all undesired to contain all light paths of this trouble unit, determine that then this element is a trouble unit.
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| CNB2006100671336A CN100446482C (en) | 2006-04-03 | 2006-04-03 | Optical fiber communication network route signal processor based on FPGA and using method |
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| JP2002094369A (en) * | 2000-09-18 | 2002-03-29 | Hitachi Ltd | Write data conversion method for fpga, optical transmission reception level monitor method using the same |
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| CN102075318B (en) * | 2010-12-28 | 2013-07-17 | 重庆邮电大学 | FPGA-based multi-channel data packet monitoring and timestamp capture system and method |
| CN102075318A (en) * | 2010-12-28 | 2011-05-25 | 重庆邮电大学 | FPGA-based multi-channel data packet monitoring and timestamp capture system and method |
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| CN102650962B (en) * | 2012-04-10 | 2015-04-08 | 北京航空航天大学 | Soft core fault-tolerant spaceborne computer based on FPGA (Field Programmable Gata Array) |
| CN102710396A (en) * | 2012-04-20 | 2012-10-03 | 上海卫星工程研究所 | Method for designing retransmission of satellite load data |
| CN102710396B (en) * | 2012-04-20 | 2015-03-04 | 上海卫星工程研究所 | Method for designing retransmission of satellite load data |
| CN102932099A (en) * | 2012-10-11 | 2013-02-13 | 三维通信股份有限公司 | Method for transmitting data between reduced media independent interface (RMII) and common public radio interfaces (CPRI) |
| CN102932099B (en) * | 2012-10-11 | 2015-10-21 | 三维通信股份有限公司 | Data transmission method between a kind of RMII and multiple CPRI |
| CN103152938A (en) * | 2013-02-07 | 2013-06-12 | 苏州市昆士莱照明科技有限公司 | Light-emitting diode (LED) lamp-based programmable integrated circuit and LED lamp assembly |
| CN109884613A (en) * | 2019-03-29 | 2019-06-14 | 湖南赛博诺格电子科技有限公司 | A kind of diode array on-line synchronous control system and method based on FPGA |
| CN113589142A (en) * | 2021-07-16 | 2021-11-02 | 广东利扬芯片测试股份有限公司 | Optical chip testing device and method based on FPGA |
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