JP2002094369A - Write data conversion method for fpga, optical transmission reception level monitor method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for writing write data to an FPGA(field programmable gate array) that can easily realize a setting revision in a logic circuit in a logical circuit design by the FPGA. SOLUTION: In the method of this invention, where data of a logic circuit and its initial setting value are read, write data consisting of binary data are generated on the basis of data of the logic circuit, and its initial setting value and the write data are written in the FPGA, when write data other than desired write data have already been written in the FPGA, binary data for the initial setting value of the write data and the initial setting value of the other write data are revised and written in the FPGA.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a programming method for a field programmable gate array.

[0002]

2. Description of the Related Art Conventionally, in a programming method for a field programmable gate array (hereinafter referred to as an "FPGA"), if there is a logic circuit that requires a change in the setting of a logic circuit, the logic circuit to which each setting change has been made is replaced by a logic circuit. It is common to input, perform logic circuit synthesis, generate write data, and write. For example, JP-A-6-76
A logic circuit design processing method disclosed in Japanese Patent Application Publication No. 019 is known.

FIG. 1 shows a logic circuit design flow 1 in an FPGA. First, when designing a logic circuit of an FPGA, a logic circuit input 2 for inputting a logic circuit from a keyboard, a storage device, or the like to the central control device is performed. Based on the logic circuit, a logic circuit synthesis 3 for optimizing a macro cell or the like is performed by the central control device. Further, at the time of the logic circuit synthesis 3, the data generation 4
Is also performed by the central controller. Thereafter, writing 5 is performed from the central control device to the FPGA, and the process is completed 6.

FIG. 2 shows a case where N settings such as an initial value of a counter are required here. In the logic circuit input 2 shown in the logic circuit design flow 1, the logic circuit inputs 7 to 9 that have been set are required, and the logic circuit design flow has to be repeated for each setting.

[0005]

Conventionally, when it is necessary to change the setting of a logic circuit for writing to an FPGA, FIG.
It is common to repeat a series of steps as shown in
For this reason, there has been a problem that the work efficiency is reduced. In addition, a series of steps as in the conventional example described above is performed by a microprocessor,
In the case of performing automatic control using a memory or the like, a microprocessor having a high processing capability, a large-capacity memory, or the like is required, and thus there has been a problem that the circuit scale and the mounting space are increased.

An object of the present invention is to reduce the time required for changing the setting of a logic circuit in designing a logic circuit and to reduce the size of related circuits such as a memory.

[0007]

According to the present invention, attention is paid to the fact that write data necessary for writing a logic circuit into an FPGA is composed of binary data of "0" or "1". When a logic circuit having a different setting such as the initial value of the counter is required, the above-mentioned problem is solved by changing the binary data.

[0008]

FIG. 3 is a logic circuit design flow showing an example of the embodiment of the present invention. First, at setting = 1, a logic circuit input 10 for inputting a logic circuit from a keyboard, a storage device or the like to the central control device is performed. Based on the logic circuit, a logic circuit synthesis 3 for optimizing a macro cell or the like is performed by the central control device. Further, as the generation of the write data at the time of the logic circuit synthesis 3, the data generation 4 is also performed by the central controller. After that, the central controller writes to the FPGA 5
And the completion is 6.

Here, if the setting = 1 is not the setting desired by the designer, it is necessary to change the setting. However, when a logic circuit with the setting = N is designed by applying the present invention, the setting = Based on the write data composed of “0” or “1” binary data generated in 1, the write data of the logic circuit whose setting = N is changed only in the change of the binary data in the data change 11. Can be generated. Therefore, it is possible to write to the FPGA with the write data newly generated by the data change 11. For this reason, if you need to change the settings,
If the original write data exists, the write data can be easily generated only by performing the data change 11 of the binary data which is the write data.

Further, in the present invention, since only the change of the binary data of the portion for setting the initial value of the counter and the like is performed, the other logic circuit portions are not affected at all.

An example of the above-described logic circuit design in the present invention will be described with reference to FIGS. 3 bitN shown in FIG.
When designing the binary counter 12, according to the logic circuit design flow shown in FIG. 3, the logic circuit input 10 of the 3-bit N-ary counter 12 is performed, the macro cell is optimized by the logic circuit synthesis 3, and the like. As the write data 16 as shown in FIG.
Generally, mn binary data 20 and the like are generated. The A0 binary data 17 to mn binary data 20 are composed of A0 macro cells 22 to
The binary conversion of the correspondence information with the mn macro cell 25, the wiring information of the fuses 31 to 33 for wiring the basic logic in the macro cell, the wiring information between the macro cells, and the like.

Also, each A0 macro cell 22-m
A flip-flop 26, an XOR
Generally, it is composed of basic logics such as 27 and ORs 28 to 30.

Here, for example, the A0 binary data 17 is taken as an example, and the correspondence information with the A0 macro cell 22 is indicated by the first 6 bits, and the A0 macro cell 2 is indicated by the next 2 bits.
Generally, wiring information of the fuses 31 to 33 for wiring the two basic logics is shown, and wiring information between the A0 macrocell 22 to the mn macrocell 25 is generally shown by subsequent bits.

Here, a 3-bit N-ary counter 1 shown in FIG.
Assume that A0 binary data 17 to mn binary data 20 are generated as write data 16 as shown in FIG. In addition, if the logic circuit is about 3 bit N-ary counter 12 shown in FIG. 4, A0 macro cell 22 to A2 macro cell 2 shown in FIG.
Assuming that it is possible to configure the logic circuit of the FPGA in FIG. 4, if it is necessary to change the setting of the logic circuit from the 3-bit N-ary counter 12 to the 3-bit M-ary counter due to a change in the logic function of the FPGA, the 3-bit N-ary counter 12 shown in FIG. Of the counter number setting pins 13 to 15 need to be changed.
In addition, as the setting change from the N-ary counter to the M-ary counter, the counter number setting pins 13 to 15 are changed from “H” to “L”,
Alternatively, it is necessary to change from “L” to “H”. Here, by applying the present invention, in A0 binary data 17 to A2 binary data 19 which are write data 16,
The fuses 31 to 33 which set the counter number of the 3-bit N-ary counter 12 are A0 binary data 17 to A2
If the fuse setting bit 21 of the binary data 19 is assumed, the value of the fuse setting bit 21 is changed from “0” to “1” or from “1” to “0”, so that the A0 macro cells 22 to A2 are changed. In the macro cell 24, the wiring of the basic logic by the fuses 31 to 33 is changed, and the setting change of the counter number can be realized.

Thus, by performing the write 5 of the logic circuit to the FPGA with the write data obtained by changing the fuse setting bit 21, the setting change to the 3-bit M-ary counter can be realized. As described above, the A0 binary data 17 to mn which are the write data 16 already generated.
By changing the binary data 20, it is possible to easily change the setting of the logic circuit.

FIG. 7 shows an example of the embodiment of the present invention, and shows a configuration in a general analog-digital conversion. This configuration includes an amplifying unit 34, an A / D converter 3
5, an FPGA 36, a central control device 37, a storage device 38, and the like.
4, and A / D conversion is performed by the A / D conversion unit 35.
This configuration allows the digital output signal 40 to be extracted from the FPGA 36. Here, generally, the amplification unit 3
4, an input offset value occurs, and a conversion error occurs in the A / D converter 35. Further, the input offset value and the conversion error are various due to component variations and the like. Therefore, the connection form of the analog input signal 39 makes it possible to extract the digital output signal 40 from the FPGA 36 using the input offset value of the amplifier 34 and the conversion error of the A / D converter 35 as the signal conversion error.

Here, the data conversion method according to the present invention is applied, and the setting of the logic circuit is changed using the logic circuit design tool 43 having the central control device 37, the storage device 38 and the like. First, the digital output signal 40 extracted as a signal conversion error from the FPGA 36 is read into the central controller 37. Next, the set value 41 corresponding to the signal conversion error read into the central control device 37 is read from the storage device 38, and the central control device 37 performs the data change 11 shown in FIG. 42
Is generated and writing 5 is performed, thereby implementing a change in the logic circuit of the FPGA 36. As a result, it is possible to extract the digital output signal 40 in which the signal conversion error such as the input offset value and the conversion error has been corrected from the FPGA 36.

FIG. 8 shows an example of the embodiment of the present invention, and shows a configuration of a monitor monitoring section in an optical transmitting / receiving module. This configuration includes an E / O converter 44, an O / E converter 45, amplifiers 46 and 47, a selector 48, an A / D converter 49, an FPGA 50, a microprocessor 51, a memory 52, and the like. / O converter 44, O
The / E converter 45 outputs a light emission level analog signal 53, a light reception level analog signal 54, and the like, and these signals are generally output as analog signals. The signal is subjected to analog-to-digital conversion, and FP
The data is extracted from the GA 50 as data. In addition, a function of switching between the error detection mode and the normal operation mode of the amplification units 46 and 47 and the A / D conversion unit 49 by the control signal 55 output from the microprocessor 51 and automatically correcting the signal conversion error is added. It is a structural example of an optical module characterized by the above. In the error detection mode, the amplification units 46, 4
7. It is assumed that the digital output signal 56 can be detected from the FPGA 50 as a signal conversion error by the A / D converter 49.

Here, by applying the data conversion method of the present invention, the microprocessor 51 reads out from the memory 52 a set value 57 corresponding to the digital output signal 56 captured as a signal conversion error by the processing program. Further, the processing of the data change 11 shown in FIG. 3 is performed, and the microprocessor 51 generates write data 58 that enables correction of each signal conversion error. After that, the setting of the logic circuit can be changed by writing to the FPGA 50 from the microprocessor 51. Thus, in the normal operation mode, the E / O converter 44 and the O / E converter 45
An A / D conversion signal such as a light emission level value digital signal 53 and a light reception level value digital signal 54 from the FPGA 5
Digital output signal 56 with signal conversion error corrected at 0
It is possible to take out as.

According to the present invention, the data change 11 shown in FIG.
Is a control for changing a small-scale logic circuit, and can be realized by a processing program of about several hundred kbits.
It can be realized by such as. For this reason, there are about four parts each having a size of about 5 mm to 15 mm square, and at present, general ultra-high-speed optical modules have a size of about 100 mm square.
Even if an A / A / D converter, a microprocessor, a memory, and the like are added, the mounting space can be suppressed to about 15%, and a light emission level value signal and a light reception level from the E / O converter and the O / E converter can be suppressed. Advanced processing such as automatic signal conversion error correction of an analog-digital conversion signal such as a value signal can be easily realized.

Further, such functions can be realized by creating a custom LSI or the like. However, in the present invention, only software development is required, and device development such as an FPGA, a microprocessor, and a memory is not required. Since device development is not required as compared to other methods, the development period can be shortened and development costs can be dramatically reduced.

[0022]

In the design of the logic circuit, the setting of the logic circuit can be changed by changing the binary data which is the write data. This is a very effective means when it is necessary to change the setting of the logic circuit of the FPGA, for example, when a function of correcting the initial error of the amplification unit, the conversion unit, and the like is added to the FPGA.

Further, a processing program capable of realizing the present invention can be realized in about several hundred kbits, and when the setting is changed by automatic control, it can be realized by a small and low-speed microprocessor, memory or the like. Therefore, this is a very effective means when the setting of the logic circuit of the FPGA is changed by automatic control.

[Brief description of the drawings]

FIG. 1 shows a general logic circuit design flow in an FPGA.

FIG. 2 shows an FPGA logic circuit design flow requiring a setting change according to a conventional example.

FIG. 3 shows an FPGA logic circuit design flow requiring a setting change according to the present invention.

FIG. 4 shows a logic circuit cited as an embodiment of the present invention.

FIG. 5 shows write data generated by the embodiment of FIG.

FIG. 6 shows a macrocell generated by the embodiment of FIG.

FIG. 7 shows a configuration in an analog physical quantity measurement method.

FIG. 8 shows a configuration of an optical transmitting / receiving module having a monitor monitoring unit having an automatic offset control correction function.

[Explanation of symbols]

1: Logic circuit design flow, 2, 7, 8, 9, 10: Logic circuit input step, 3: Logic circuit synthesis step, 4: Data generation, 5
... writing step, 6 ... step completion, 11 ... data change step,
12 ... 3-bit N-ary counter, 13, 14, 15 ... initial value setting pin, 16, 42, 58 ... write data, 17, 18,
19, 20: binary data, 21: fuse setting bit, 22, 23, 24, 25: macro cell, 26: flip-flop, 27: XOR gate, 28, 29, 30 ...
OR gate, 31, 32, 33 ... fuse, 34, 46, 4
7 Amplifying unit, 35, 49 A / D converter, 36, 50 F
PGA, 37: Central control device, 38: Storage device, 39 ...
Analog input signal, 40, 56 ... digital output signal,
41, 57: setting values, 43: logic circuit design tool, 44
... Electrical / optical converter, 45 ... optical / electrical converter, 48 ... selector, 51 ... microprocessor, 52 ... memory, 53
... light emission level analog signal, 54 ... light reception level analog signal, 55 ... control signal.

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[Procedure amendment]

[Submission date] October 19, 2000 (2000.10.
19)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Taro Kitayama 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Communications Division 5J022 AA01 CF09 CF10 5J042 BA03 BA11 DA04 5K029 AA18 CC04 JJ01 KK24

Claims (4)

[Claims] 1. A method for reading data of a logic circuit and an initial setting value of the logic circuit, and based on the data of the logic circuit and the initial setting value,
In a method of generating write data composed of binary data of “0” or “1” and writing the write data to a field programmable gate array (hereinafter referred to as an FPGA), the FPGA stores another write data different from the write data. In the case where write data has been written, binary data different from the initial set value of the write data and the initial set value of the another write data is changed and written to the FPGA.
Write data conversion method. 2. An analog signal is input, the analog signal is amplified to output an amplified signal, the amplified signal is input, the amplified signal is converted from analog to digital, and a digital signal is output. And converting the digital signal with a logic circuit, and outputting the logic signal. In the analog / digital conversion method, the logic circuit is configured by an FPGA, reads the digital signal, and corresponds to the digital signal. Initial setting values read from a storage device storing a plurality of different initial setting values,
An analog / digital converter characterized by generating write data with the initial set value and converting write data of the logic circuit when the initial set value which is an initial set value already written in the FPGA is different. Conversion method. 3. The analog / digital conversion method according to claim 2, wherein said analog signal is an analog signal selected from a plurality of analog signals. 4. An optical transmission / reception level monitor using the analog / digital conversion method according to claim 3, wherein the plurality of analog signals are an optical transmission level monitoring signal and an optical reception level monitoring signal. Method.