CN101051614B - 在衬底上形成加强互连的方法 - Google Patents

在衬底上形成加强互连的方法 Download PDF

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CN101051614B
CN101051614B CN2007101035563A CN200710103556A CN101051614B CN 101051614 B CN101051614 B CN 101051614B CN 2007101035563 A CN2007101035563 A CN 2007101035563A CN 200710103556 A CN200710103556 A CN 200710103556A CN 101051614 B CN101051614 B CN 101051614B
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supporting construction
substrate
scolder
interconnection
wire loop
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CN101051614A (zh
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萧喜铭
周安乐
黎戈
叶兴强
郑通庆
陈兰珠
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

一种在衬底上形成加强的互连或凸块的方法包括首先在衬底上形成支撑结构。然后在该支撑结构周围形成基本上填满的封囊以形成互连。该互连可达到高达300微米的高度。

Description

在衬底上形成加强互连的方法
技术领域
本发明涉及一种用于在半导体晶片或印刷电路板(PCB)上形成互连的方法。更具体地，本发明涉及一种用于形成其中具有支撑结构以实现高基准距(stand-off)的加强互连的方法。
背景技术
微电子器件封装的发展持续受到减小成本、实现更高的封装密度和改善性能同时仍然维持或者甚至提高电路可靠性的需求的驱动。为了满足这些目标，倒装芯片接合工艺(其中半导体芯片被面朝下安装在衬底或电路板上)在微电子器件封装中已变成一种普遍的选择。因为除去了在芯片内对于凸块或者互连在正常情况下所需的空间，倒装芯片接合是有利的。此外，在高频应用中倒装芯片通常提供优良的性能。
倒装芯片安装典型地分三个阶段制造：在芯片上形成互连或凸块，将凸起的芯片附装至板或衬底，并且使用非导电材料填充凸起的芯片下剩余的空间。在半导体晶片上形成互连有许多公知的方法。一种方法包括利用丝焊器在衬底上形成金柱状凸块，并且利用焊料在其上形成第二柱状凸块以增加互连基准距。
尽管在理论上，额外的柱状凸块可以连续堆叠以获得高基准距，但该工艺还是有问题的。首先，每个柱状凸块的顶表面是不太可能平坦的，因此使堆叠困难。其次，如果柱状凸块在三个或者更多的堆叠凸块上形成，就可能在形成期间坍塌。因此，柱状凸块的最大数量受到限制并且基准距高度限制到大约60微米。以大约60微米的低基准距，凸块易受到剪切应变，此剪切应变由半导体芯片和晶片衬底之间的热膨胀系数(CTE)的不匹配产生。超额的应变可以引起凸块破裂而导致该倒装芯片组件失效。
另一种形成互连的方法包括提供具有由两个细长柱形成的总基准距高度在80至120微米范围内的细长柱。这种方法以首先在倒装芯片上形成光致抗蚀剂层开始。然后照射部分该光致抗蚀剂以在该层中形成通孔。用铜分别填充这些孔，随后通过焊料形成细长柱。
为了填充这些孔，整个结构可以首先放置在铜浴中并且电镀以在这些孔中沉积铜。其后，整个结构可以放置在焊料浴中并且电镀以用焊料填充孔中的剩余空间。然后通过化学浴除去该光致抗蚀剂层以暴露该细长柱。接着对该细长柱进行回流以将该倒装芯片连接至衬底。
不幸地，这种形成互连的工艺费用昂贵并且使用大量化学溶液，这将产生化学废料。另一个问题是该柱的基准距受光致抗蚀剂层厚度的限制。尽管光致抗蚀剂层的厚度可以增加，但这样就限制了柱的间距。实际上，光致抗蚀剂层中的开口通常具有倒圆锥形，即，开口朝向焊垫处的窄端逐渐变细。因此，如果想得到精细间距，该光致抗蚀剂层的厚度可以限制到大约80微米。因此，在高基准距和精细间距之间需要权衡。
鉴于上述，期望得到一种低成本并且不涉及湿式化学试剂的形成互连的方法。此外，期望得到一种提供高基准距和精细间距的方法。
附图说明
本发明通过以下的结合相关附图的详细描述将容易地理解。为便于描述，相同的参考数字指代相同的结构部件。
图1显示根据本发明一实施例的半导体晶片的放大截面图。
图2显示根据本发明一实施例的图1中的接收粘着剂的半导体晶片的放大截面图。
图3显示根据本发明一实施例的图2中的接收焊料源的半导体晶片的放大截面图。
图4显示根据本发明一实施例的回流焊之后在图3的半导体晶片上形成的凸块的放大全图。
图5显示根据本发明一实施例的图4中的接收未满层的半导体晶片的放大截面图。
图6A显示根据本发明另一实施例的在半导体晶片上形成的支撑结构的放大透视图。
图6B显示根据本发明一实施例的包围图6A中的支撑结构的互连的放大全图。
图6C显示根据本发明另一实施例的图6B中的互连的放大透视图。
具体实施方式
提供在半导体芯片或印刷电路板(PCB)环境中的衬底上形成细长互连或凸块的方法。在以下描述中，为了提供对本发明全面的理解，大量特殊的细节以后会提及。然而，在公知领域中可以明白，缺少这些特殊细节的部分或全部本发明也可以实现。在其它实例中，对于本发明不必要具体的众所周知的工艺操作没有进行详细的描述。
在一实施例中，本发明是一种形成导电凸块的方法，包括以下步骤：在衬底上形成支撑结构；将焊料附着至该支撑结构上；并且熔融该焊料以形成该导电凸块。该支撑结构包括一个或多个利用导线接合工艺形成的导线回路。该焊料可以通过在该支撑结构上沉积粘着剂，然后在粘着剂上沉积焊料来附着。可选择地，可以将该支撑结构浸入到熔融的焊料浴中来附着焊料。
现在参考图1，示出了根据本发明第一实施例的半导体晶片104或衬底的放大截面图。在衬底104上通过例如导线接合装置形成支撑结构108。导线可以接合到衬底104的焊垫112上或者热基准距上。支撑结构108的材料可以从金、铜或任何可焊的合金中选择。在实施例中，该支撑结构包括铜导线。
在这个具体实施例中，该支撑结构108由单导线回路形成。支撑结构108通常适于形成具有小的截面积的互连。如果要得到较大的截面或较大的体积的互连，可以使用本发明的其它构型，例如显示在图6A中的实施例。
支撑结构108的高度可以在大约150微米至大约300微米的范围内，这受制于导线接合装置的能力。大部分导线接合装置可以提供基准距高度达300微米，这对于倒装芯片应用是有益的。
典型地，倒装芯片组件会受到硅(CTE约2至4单位每百万每摄氏度或者PPM/℃)和陶瓷衬底(CTE约6至7PPM/℃)之间或硅和常用的电路板(CTE约12至18PPM/℃)之间的热膨胀系数的不匹配的影响。由于CTE的不匹配，互连受制于制造工艺温度循环期间或倒装芯片器件正常使用期间的热疲劳。超额的热应力可导致互连的破裂，和/或半导体芯片的脱层或碎裂，最终引起器件失效。
在使用低K(介电常数)材料的器件中破裂的发生率特别高，这种器件具有低的机械和内聚强度。这是重要的，因为半导体制造中低K材料的使用迅速增长。由于热应力的大小依赖于材料之间的CTE不匹配和互连的长高比，必须增加互连的基准距高度以承受大的温度波动和CTE不匹配。因此，本发明提供的基准距的范围有利于提高互联的可靠性。
现在参考图2，示出了根据本发明一实施例中接收粘着剂116的衬底104的放大截面图。可以通过直接向支撑结构108分配或者通过将支撑结构108浸入到粘着剂浴中来沉积粘着剂116。适合的粘着剂可以包括焊剂，例如，锡-铅焊剂、水溶焊剂和无杂质焊剂。应当理解，焊剂会提高焊料的润湿和接合能力。另外，焊剂可以用于从焊垫112和/或支撑结构108的表面去除杂质和氧化物。
然而，如果支撑结构108是新形成的，则不需要焊剂，并因此基本上没有氧化。如果不需要应用焊剂，支撑结构108可以浸入到熔融的焊料浴中以用焊料涂敷该支撑结构108。然后可以从熔融的焊料浴中取出涂敷后的支撑结构108并使熔融的焊料固化。如此，固化的焊料形成互连，其一个实施例就是围绕支撑结构108基本填满的封囊。
现在参考图3，示出了根据本发明一实施例中接收了焊料源120的衬底104的放大截面图。焊料源120被附着或者被设置与每个支撑结构108接触。焊料源120可以预先附着到半导体集成电路芯片124上。
焊料源120可包括低共熔焊料，例如，低共熔锡-铅焊料(37％铅和63％锡)、或低共熔锡-银-铜焊料(96.5％锡，3％银和0.5％铜)、或高铅焊料(95％铅和5％锡)。可替代地，可以使用无铅焊料。优选地，焊料源120具有低于支撑结构材料熔点的熔点，以使在回流期间支撑结构108保持固态。焊料熔点可在大约150摄氏度到大约320摄氏度之间。
进行回流工艺以形成如图4所示的焊料凸块或者互连128。更具体地，加热衬底104和半导体芯片124以熔融焊料源120。适合于回流工艺的温度依赖于焊料源120的材料，并且可在大约150摄氏度到大约320摄氏度之间变化。回流期间，焊料源120变成熔融并与粘着剂116溶合，然后封闭该支撑结构108。由于支撑结构108具有高于焊料120的熔点，该支撑结构108在整个回流工艺中维持固态。
使半导体芯片124朝向支撑结构108，直至该半导体芯片124与该支撑结构108并置，以在芯片124与衬底104之间形成电性连接。当熔融的焊料固化时，在支撑结构108周围形成互连128。图4示出了图3中的衬底104上形成的互连128在回流焊之后的放大全图。应当理解，一个实施例的互连128是基本上填满的封囊，其结构上由可提高互连128的机械强度的支撑结构108加强。
现在参考图5，示出了根据本发明一实施例的图4中的衬底104接收介电材料形成未满层132的放大截面图。可在半导体芯片124与衬底104之间引入介电材料以向半导体芯片124和互连128提供支撑和稳定性。未满层132的另一个目的是将互连128与相邻的互连隔离，以阻止短路。
代替图3中所示的结构，焊料源120可为焊料粉末容器，该粉末的颗粒直径在大约5微米至大约10微米之间。虽然也可以使用其它的颗粒尺寸，但应该意识到，较大的颗粒尺寸会导致较大的互连尺寸和间距。将焊料粉末沉积到支撑结构108上，并在回流之前附着到在支撑结构108上事先沉积粘着剂116的顶部。在使用焊料粉末的情况下，可能需要进一步的回流，以通过互连128电性连接半导体芯片124和衬底104。
现在参考图6A，示出了根据本发明另一实施例的在衬底104上形成的支撑结构608的替代结构。用于形成第一回路612的第一导线和用于形成第二回路616的第二导线接合至衬底104，以形成支撑结构608。两个回路612、616优选彼此交叉，以在其间相对于图1的单回路实施例包围更大的区域。双回路支撑结构608使得比起图1中的支撑结构108能够支撑更多的焊料材料，并且因此适合于形成具有较大截面的互连。第一和第二导线回路608和612由导线接合装置形成。虽然可以使用任何导线，例如铜或金，但优选使用铜导线，因为它的高机械强度。
图6B示出了通过在图6A的支撑结构608上沉积焊料形成的焊料凸块或互连628的放大全图。与图4的互连128类似，应该意识到互连628是基本填满的封囊，其结构上由支撑结构608加强。也就是说，以与上面描述的互连128相同的方式形成互连628。图6C示出了该互连628的放大透视图。
本发明的一个益处是可以增加互连的长宽比。公知的互连或凸块通常是球形的，从而具有仅大约为1的长宽比。尽管一些互连可以具有大于1的长宽比，但这样的互连通常通过耦合两个或更多的细长柱并且使用化学工艺形成，这两者都很昂贵。
本发明中，可以不用形成多个互连或凸块而实现大于约1.5的增加的长宽比。由于焊垫尺寸通常在约40微米至约100微米的范围内，并且本发明形成的互连的基准距高度在150微米至300微米之间，所以通过本发明可以实现比约1.5更高的长宽比。
另一个主要的益处是高基准距可以由本发明获得。基准距取决于支撑结构108或608的高度，它可以通过改变回路高度而进行调整。如此，互连128或封囊的高度可以高达150微米至300微米，这取决于导线接合装置的能力。
高的基准距可以减小由封装材料中的热膨胀系数(CTE)的不匹配产生的热机械应力。典型地，硅的CTE在2至4范围内，而电路板的CTE在12至18的范围内。本发明的高基准距释放了由于CTE不匹配产生的应力，从而提高了连接可靠性。鉴于前述的CTE值(即硅的为4的高CTE和电路板的为12的低CTE)，本发明适于电路板和硅的CTE比大于大约3的装置。
本发明的另一个益处是可减小互连直径，从而提供不会有短路危险的更精细的互连间距。公知的互连典型地为球形。因为本发明的互连通常是更细长的，所以较高的互连密度可以实现，而不会增加互连与相邻的互连相接触而导致短路的风险。
另一个益处是本发明不涉及昂贵且破坏环境的湿法化学工艺。进一步的益处是由于由支撑结构108、608提供的加强，从而互连的机械强度得到提高。
虽然上述工艺是针对在半导体晶片上形成互连或者凸块进行描述的，本发明也可以应用到PCB衬底上。考虑本发明的说明和实践，本发明的其它实施例对本领域技术人员来讲是显而易见的。进一步的，为了描述清楚而使用了某些术语，这并不限制本发明。上述的实施例和优选的特征应认为是示例性的，本发明由所附权利要求限定。

Claims (9)

1.一种在衬底上形成互连的方法，包括：
在衬底上形成支撑结构，其中所述支撑结构是通过接合第一导线回路和第二导线回路至所述衬底形成，所述第一导线回路与所述第二导线回路交叉，所述第一导线回路与所述第二导线回路中每个都具有接合至所述衬底的第一端和第二端，并且在每个导线回路的与所述衬底间隔开的中点处交叉；
在所述支撑结构周围形成封囊，以形成所述互连；
2.根据权利要求1所述的形成互连的方法，其中形成封囊的步骤进一步包括：
在所述支撑结构上沉积粘着剂；
在所述粘着剂上沉积焊料；并且
熔融所述焊料以形成所述封囊。
3.根据权利要求2所述的形成互连的方法，其中所述支撑结构的熔点高于所述焊料的熔点。
4.根据权利要求2所述的形成互连的方法，其中所述封囊的高度在150微米至300微米之间。
5.根据权利要求2所述的形成互连的方法，其中所述焊料是颗粒尺寸在5微米至10微米之间的粉末。
6.根据权利要求2所述的形成互连的方法，其中所述焊料为低共熔锡-铅焊料、低共熔锡-银-铜焊料和高铅焊料中之一。
7.根据权利要求1所述的形成互连的方法，其中所述封囊具有大于1.5的长宽比。
8.一种形成导电凸块的方法，包括：
在衬底上形成支撑结构，其中所述支撑结构包括由导线接合工艺形成的两个交叉的导线回路，每个导线回路具有接合至所述衬底的第一端和第二端，并且在导线回路的中点处交叉；
在所述支撑结构上沉积粘着剂；
在所述粘着剂上沉积焊料；并且
熔融所述焊料以形成所述导电凸块。
9.根据权利要求8所述的形成导电凸块的方法，其中所述焊料附着步骤包括将所述支撑结构浸入到熔融的焊料中。
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US9082763B2 (en) * 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US9351436B2 (en) * 2013-03-08 2016-05-24 Cochlear Limited Stud bump bonding in implantable medical devices
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252175B1 (en) * 1993-11-16 2001-06-26 Igor Y. Khandros Electronic assembly comprising a substrate and a plurality of springable interconnection elements secured to terminals of the substrate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4705205A (en) * 1983-06-30 1987-11-10 Raychem Corporation Chip carrier mounting device
JPH05166811A (ja) 1991-12-19 1993-07-02 Fujitsu General Ltd 半田バンプの形成方法
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US6540524B1 (en) * 2000-02-14 2003-04-01 Advantest Corp. Contact structure and production method thereof
US6437591B1 (en) * 1999-03-25 2002-08-20 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6281607B1 (en) * 1999-04-06 2001-08-28 Trw Inc. Electric motor with vibration attenuation
JP2001237512A (ja) * 1999-12-14 2001-08-31 Nitto Denko Corp 両面回路基板およびこれを用いた多層配線基板ならびに両面回路基板の製造方法
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US7032311B2 (en) * 2002-06-25 2006-04-25 Eli Razon Stabilized wire bonded electrical connections and method of making same
US6959856B2 (en) * 2003-01-10 2005-11-01 Samsung Electronics Co., Ltd. Solder bump structure and method for forming a solder bump
US7462942B2 (en) * 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
JP4427298B2 (ja) * 2003-10-28 2010-03-03 富士通株式会社 多段バンプの形成方法
KR101237172B1 (ko) * 2003-11-10 2013-02-25 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US20050133928A1 (en) * 2003-12-19 2005-06-23 Howard Gregory E. Wire loop grid array package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252175B1 (en) * 1993-11-16 2001-06-26 Igor Y. Khandros Electronic assembly comprising a substrate and a plurality of springable interconnection elements secured to terminals of the substrate

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TW200741923A (en) 2007-11-01

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