CN101047135A - 金/硅共晶芯片焊接法 - Google Patents

金/硅共晶芯片焊接法 Download PDF

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CN101047135A
CN101047135A CNA2007100896762A CN200710089676A CN101047135A CN 101047135 A CN101047135 A CN 101047135A CN A2007100896762 A CNA2007100896762 A CN A2007100896762A CN 200710089676 A CN200710089676 A CN 200710089676A CN 101047135 A CN101047135 A CN 101047135A
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gold
silicon
layer
die bonding
bonding method
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刘凯
孙明
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Abstract

本发明公开了一种金/硅共晶芯片焊接法，它包括如下步骤：1)将钛层真空脱水粘附到硅片的背面，钛层的厚度小于200；2)随即将金层真空脱水粘附到钛层上，金层的厚度在0.5到1.5微米范围之内；3)切割硅片；和4)在共晶温度下将芯片装配到基片上生成金/硅共晶合金键。

Description

金/硅共晶芯片焊接法
技术领域
本发明一般地涉及将一个半导体芯片焊接到一个部件上的方法。更具体地，本发明涉及一种金/硅共晶芯片焊接法。
背景技术
常规芯片焊接法包括广泛选择用来连接硅片与基片的材料，这些材料包括硬钎料和软焊剂、导电的环氧树脂和金/硅共晶合金。对于诸如SOT563和SOT623的小部件而言，金/硅共晶合金则是较理想的选择。
常规的金/硅共晶芯片焊接法包括在硅片背面涂金，然后将芯片加热到高于363℃的共晶温度，生成金/硅共晶合金。在大多数应用中，常用Cr和/或Ti粘附层或其它三明治形结构来改善金在硅片上的粘附。然后，芯片通过进一步的、使用金/硅共晶合金作为焊接剂的加热步骤连接到一个诸如引线框架的金属基片上，另外的金层也可以沉积在金/硅共晶合金层上，金或金合金前体可有助于芯片焊接。其它的常规技术还包括使用金/硅种作为催化剂生成共晶键以及在金层中使用通过硅注入生成的金/硅合金。
常规的金/硅共晶芯片焊接法的一个问题是金扩散硅片后造成在芯片上生成的器件的电性能不理想。为了应对这一问题，通常将一层Ti或Cr阻挡层与其它包括钨和白金在内的金属一起沉积在硅片背面与金层之间。这样，阻挡层起着扩散式叠层的功能，限制硅的氧化数量，其厚度通常约500左右。随后需要有520℃到更高的焊接温度范围，使芯片共晶焊接到基片上。
520℃到更高的温度范围对于封装MOSFET芯片来说是太高了。另外，在芯片背面提供粘附和阻挡层成本太高，降低了器件的产量。因此，仍然存在着发明一种新的、能克服上述问题的芯片焊接法的需要。同时还存在着这样的需要，即一种使用金/硅合金的芯片焊接法，它采用较低的、但不会负面影响MOSFET器件性能的焊接温度，又能够确保MOSFET芯片的连接质量。此外，还进一步存在着这样的需要，即发明一种芯片焊接法，这种方法具有较高的性价比，并能提高器件的产量。
发明内容
本发明的金/硅共晶芯片焊接法解决了将MOSFET焊接到诸如引线框架的基片所遇到的问题。本发明发现，一层薄的、厚度小于200(优选50到150)的Ti粘附层能足够地与金层粘附，使用低于470℃的焊接温度可以生成一种金/硅共晶合金键，这种温度适合于MOSFET器件的组装。
根据本发明的一个方面，一种金/硅共晶芯片焊接法包括如下步骤：1)将钛层真空脱水粘附到硅片的背面，钛层的厚度小于200；2)随即将金层真空脱水粘附到钛层上，金层的厚度在0.5到1.5微米范围之内；3)切割硅片；和4)在共晶温度下将芯片装配到基片上生成金/硅共晶合金键。
根据本发明的另一个方面，一种将MOSFET硅片焊接到引线框架的金/硅共晶芯片焊接法包括如下步骤：1)真空溅射钛层之前碾磨含有MOSFET芯片的硅片背面；2)将钛层真空脱水粘附到硅片的背面，钛层的厚度小于200；3)随即将金层真空脱水粘附到钛层上，金层的厚度在0.5到1.5微米范围之内；4)切割硅片；和5)在共晶温度下将芯片装配到基片上生成金/硅共晶合金键。
本发明提供的金/硅共晶芯片焊接法，具有较高的性价比，而且可以在对MOSFET器件的性能没有负面影响的温度下实施。本方法还省去了需要沉积一层阻挡层的要求，从而提高了器件的产量。
为了便于以下的详细介绍能够更加容易地理解，也为了更清楚地了解本发明对该领域的技术所作的贡献，我们粗略地、概要地对本发明的一些主要的特征进行了描述。当然，我们还将在下面的说明中对本发明的另一些特征进行介绍。
结合以下的附图和说明，可以更加容易地理解本发明的上述和其它特征、方面和优点。
附图说明
图1是一个流程图，显示了一种根据本发明的金/硅共晶芯片焊接法。
具体实施方式
本发明提供了一种金/硅共晶芯片焊接法，其中，一层厚度小于200(优选50到150)的薄Ti粘附层可提供与金层的足够粘附，而金层粘附在硅片的背面。应用低于470℃的焊接温度生成一种金/硅共晶合金键，该键通过了诸如TC500周期、PCT96小时和HAST100小时的可靠性试验。低于470℃的焊接温度适合于MOSFET器件的组装。
参看图1，本发明的方法100包括将硅片背面碾磨到所需的厚度的步骤110。在步骤120中，一层50到200的Ti层，优选50到150的Ti层，在真空环境下在硅片背面上脱水，Ti层有助于突破在硅片背面表面上生成的SiO2层，生成一个可连接金的表面。因此，Ti层在随后的金层与硅片之间提供了一层粘附层。
优选地，Ti层是足够薄的，当硅片在芯片连接阶段加热时，硅和金将相互扩散生成共晶合金。另外，Ti层又优选具有足够的厚度，以避免金层从Ti层上剥落下来。
步骤130紧随步骤120，一层具有0.5到1.5微米厚度的金层在Ti层上脱水，然后在步骤140中将硅片固定、切割。最后，在步骤150中，将芯片拿出，在高于370℃的金/硅共晶温度下，根据芯片尺寸的大小和焊接机的条件优选410℃到470℃的范围，将其装置在一个镀有银层的引线框架上。
根据本发明的方法100提供了一种金/硅共晶芯片焊接法，这种方法具有较高的性价比，而且可以在对MOSFET器件的性能没有负面影响的温度下实施。这种方法100还进一步省去了需要沉积一层阻挡层的要求，从而提高了器件的产量。
当然，必须认识到，上述介绍是有关本发明优选实施例的说明，只要不偏离随后所附权利要求所显示的精神和范围，本发明还存在着许多修改。
本发明决不是仅局限于上述说明或附图所显示的细节和方法。本发明能够拥有其它的实施例，并可采用多种方式予以实施。另外，大家还必须认识到，这里所使用的措辞和术语以及文摘只是为了实现介绍的目的，决不是仅仅局限于此。
正因为如此，本领域的技术人员将会理解，本发明所基于的观点可随时用来作为实施本发明的几种目标而设计其它结构、方法和系统。所以，至观重要的是，所附的权利要求将被视为包括了所有这些等价的建构，只要它们不偏离本发明的精神和范围。

Claims (12)

1.一种金/硅共晶芯片焊接法，所述方法包括如下步骤：
将钛层真空脱水粘附到硅片的背面，所述钛层的厚度小于200；
随即将金层真空脱水粘附到所述钛层上，所述金层的厚度在0.5到1.5微米范围之内；
切割硅片；和
在共晶温度下将芯片装配到基片上生成金/硅共晶合金键。
2.根据权利要求1所述的金/硅共晶芯片焊接法，其特征在于，所述钛层的厚度在50到150之间。
3.根据权利要求1所述的金/硅共晶芯片焊接法，其特征在于，进一步包括在切割硅片之前要固定硅片。
4.根据权利要求1所述的金/硅共晶芯片焊接法，其特征在于，所述基片包含有一层银层。
5.根据权利要求1所述的金/硅共晶芯片焊接法，其特征在于，共晶温度范围是410℃到470℃。
6.根据权利要求1所述的金/硅共晶芯片焊接法，其特征在于，所述芯片包含有MOSFET器件。
7.根据权利要求1所述的金/硅共晶芯片焊接法，其特征在于，进一步包括真空溅射所述钛层之前碾磨硅片的背面。
8.一种将MOSFET硅片焊接到引线框架的金/硅共晶芯片焊接法，其包括如下步骤：
真空溅射钛层之前碾磨含有MOSFET硅片的硅片背面；
将所述钛层真空脱水粘附到所述硅片的背面，所述钛层的厚度小于200；
随即将金层真空脱水粘附到所述钛层上，所述金层的厚度在0.5到1.5微米范围之内；
切割硅片；和
在共晶温度下将芯片装配到基片上生成金/硅共晶合金键。
9.根据权利要求8所述的金/硅共晶芯片焊接法，其特征在于，共晶温度范围是410℃到470℃。
10.根据权利要求8所述的金/硅共晶芯片焊接法，其特征在于，所述钛层的厚度在50到150之间。
11.根据权利要求8所述的金/硅共晶芯片焊接法，进一步包括在切割硅片之前要固定硅片。
12.根据权利要求8所述的金/硅共晶芯片焊接法，其特征在于，所述引线框架包含有一层银层。
CNA2007100896762A 2006-03-31 2007-03-26 金/硅共晶芯片焊接法 Pending CN101047135A (zh)

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