CN101031895A - Simultaneous external read operation during internal programming in a flash memory device - Google Patents
Simultaneous external read operation during internal programming in a flash memory device Download PDFInfo
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- CN101031895A CN101031895A CNA200580024560XA CN200580024560A CN101031895A CN 101031895 A CN101031895 A CN 101031895A CN A200580024560X A CNA200580024560X A CN A200580024560XA CN 200580024560 A CN200580024560 A CN 200580024560A CN 101031895 A CN101031895 A CN 101031895A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2022—Flash memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
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Abstract
A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.
Description
Technical field
The present invention relates to semiconductor storage.More particularly, relate to a kind of implementation system and method for depositing operation of in storage unit, returning.
Background technology
Semiconductor storage is divided into volatile storage and Nonvolatile memory devices usually.Volatile storage can be subdivided into dynamic RAM (DRAMs) and static RAM (SRAMs).Types of non-volatile comprises that mask venerates memory read (MROMs), able to programmely venerates memory read (PROMs), and erasable programmable venerates memory read (EPROMs) and electric erazable programmable is venerated memory read (EEPROMs).And EEPROMs is applied among the programing system that requires continual renovation or auxilary unit just more and more.Specifically, fast erasable electric erazable programmable is venerated memory read and is good as a large amount of storeies, because its integration density be a height compared with the EEPROMs of routine.Venerate in the memory read at described fast erasable electric erazable programmable, AOI type or venerate memory read with the fast erasable electric erazable programmable of type and compare is venerated memory read with the no type quick erasable electric erazable programmable and is had high density of integration.
At present, a kind of operation of fast erasing apparatus make the user can be in source address location directly with the copying data of one page (size of a memory page is typically 256 byte to 2 kilobyte) stored to the destination address position, rather than data are written out to external storage and write back to described destination address again.Therefore, described operating efficiency height is because step of its need.This is one and returns and to deposit the example of operation.Yet this class is returned and deposited is a kind of blind operation.The user does not know correct data, and whether oneself is copied.If it is destroyed or wrong to wait upon copies data, just described data can be write described destination mistakenly.
Therefore, as if though deposit the performance that operation strengthens described device this time, it can not guarantee the reliability of source data.Moreover this time scheme of depositing can not prevent that misdata from copying described destination address to.
Can guarantee wherein a kind of reliability of main method with a kind of error correcting code (ECC).Can use various error correction schemes to guarantee reliability of data storage.A kind of error correction scheme can be corrected a mistake, for example, because discharge loss is proofreaied and correct the integrality of described data and is abolished misdata.Yet for a kind of error correction scheme of typical check data integrity, at least one additional serial random read cycle need be carried out.Described additional serial read step reduces the performance of described fast erasing apparatus and reduces overall system performance by linking with the CPU truck and requiring the cpu clock cycle to carry out error correction.
Scheme is deposited in another time that Figure 1 shows that prior art.Fig. 1 comprises a flash memory device 101, a microcontroller 107 and a series connection bus 109.Described flash memory device 101 comprises a source address location 103 and a destination address position 105.
Described flash memory device 101 can be, for example, and a kind of and non-type device.Described flash memory device 101 is generally by described serial bus 109 and is communicated with a kind of outer treating apparatus of all microcontrollers as described 107.Described microcontroller 107 also can be another kind for the treatment of apparatus such as a kind of CPU or other microprocessors.Deposit operation for carrying out back, described microcontroller 107 at first reads to be included in the data of described source address location 103.Subsequently, described microcontroller 107 is write described destination address position 105 with the copy of a institute read data.
At last, described microcontroller 107 is checked the data of writing described destination address position 105 by carrying out a final read operation (not shown) that is positioned at the new writen data of described destination address position 105.Be feasible although it is so, but typical returning deposited scheme, as shown in Figure 1 all, be slow, because all between described flash memory device 101 and described microcontroller 107 are read and write operation must just carry out by described serial bus 109.
Deposit scheme another time that Figure 2 shows that prior art.In this scheme, add a kind of interior data register 209 in the flash memory device 201.In this, directly be sent to described data register 209 in source address location 103 stored data.Afterwards, this data register 209 is sent to destination address position 205 with portion at the copy of described source address location 203 stored data.Described system can provide high-speed data transfer.Yet possible check data integrality is not because have and described microcontroller 107 interactions.Usually, need require a microcontroller to carry out error correction (for example, such as carrying out an error correcting code (ECC)) if having.There has been described data register 209 to make cache write operation become possibility, so that can before the destination address programming, revise by described microcontroller in the data of this data register 209.
Support one page with no type quick erasable EEPROM and return and deposit operation, its expression data information can be copied to another page or leaf and needn't be outputed to an external devices by one page.At the United States Patent (USP) RE36 of MIYAMOTO, a kind of this type of device has been described in No. 732.Described announcement device for " a kind ofly transmit the Nonvolatile semiconductor memory device that data are used ... returned when depositing when data, need do not read institute's read data to an external unit " (in the MIYAMOTO summary with emphasis).Described MIYAMOTO device reduces total returning by this and deposits the time by side by side not using delegation's storage copying data CPU to carry out back and deposit operation to another row.
In No. the 2003/0076719th, U.S.'s publication application of people such as BYEON, describe a kind of combination and returned the additional memory devices of depositing operation.BYEON describes a kind of Nonvolatile memory devices, and it comprises a page impact damper, and when read operation, it can be used as a kind of sensor amplifier, and when programming operation, it can be used as a kind of write driver.Described page buffer has two and detects and latch blocks, and it carries out identical functions.When the one of described detection and latch blocks was carried out read operation, the data that another piece then will be detected before outputed to described external devices.In addition, when the one of described detection and latch blocks is carried out programming operation, another piece data to be programmed of then packing into.Because this page buffer, the operating speed of described Nonvolatile memory devices just can promote." (having emphasis in the BYEON summary).
Yet MIYAMOTO or BYEON etc. does not disclose a kind of device per capita, its (1) check data integrality; (2), carry out error correction, or (3) in carrying out during programming operation, the outer read operation of execution side by side if when data are invalid.
Therefore, a kind of flash memory device need a kind of system and method can carry out external read operation and carry out simultaneously in programming, check data integrality and if needed after read operation provides error correction.
Summary of the invention
The present invention is a kind of at the memory storage internal programming, carries out the system of external read operation simultaneously, and it is provided to by realizing in the accessible cache register of outer treating apparatus by portion being waited the mirror-image copies that transmits data.Described memory storage constitutes randomly storage data and comprises memory location, a source, a purpose memory location, a data register and a cache register.Described data register constitutes writes data described purpose memory location and described cache register simultaneously.This source and purpose memory location can accomplish to make electrical communication with described data register, and described data register can be accomplished to be communicated with described cache register in addition.Described system also comprises a kind for the treatment of apparatus (for example, a kind of microprocessor or microcontroller), its by with the accuracy of described memory storage electric connection check any data that receive.If described reception data are inaccurate, described treating apparatus also constitutes and carries out error correction.
In typical operation of the present invention, a microcontroller reads in data stored in the cache memory, and described data are programmed into destination address simultaneously.In addition, described microcontroller energy checked for errors and correction, and described data are programmed into described destination address.
The present invention also be a kind of in memory storage internal programming, the simultaneously manner of execution of external read operation.Described method comprises the former copying data of source address location that will be stored in described memory storage to data register, simultaneously the former copying data of described data register is sent to treating apparatus to cache register and destination locations and the former data that will be stored in this cache register.
In case described former data arrive described treating apparatus, the integrality of described former data can be made comparisons with the data that are stored in described source address location by the former data that will be transmitted and be checked.This check can transmit in this institute and find out any potential errors in the former data.If the mistake of detecting then can be carried out error correction to the former data of transmit, form data by this through error correction.In addition, described treating apparatus can join additional random data described in the data stream of error correction or described the transmission in the former data stream, forms by this through the correction data of error correction or the former data of correction.Then, described data through error correction, described correction data or described correction data through error correction are sent to described cache register from described treating apparatus, make a copy that is sent to the data of described data register from described treating apparatus become mirror image subsequently and the most at last from copying data that described treating apparatus the transmits destination locations in the memory storage.
Description of drawings
Figure 1 shows that a prior art returns the scheme of depositing, it adopts a microcontroller, the serial bus of described in succession memory storage of a flash memory device and one and described microcontroller;
Figure 2 shows that another prior art returns the scheme of depositing, it adopts a microcontroller and to have the described in succession memory storage of flash memory device and of interior data register and the serial bus of described microcontroller;
Figure 3 shows that the block scheme of flash memory device of the present invention, wherein a series connection bus makes a microcontroller and the coupling of described memory storage;
Figure 4 shows that a chronogram, in its presentation graphs 1 among prior-art devices and Fig. 3 the relative time between the present invention poor;
Figure 5 shows that prior art is returned the diagram oscillogram of depositing operation among Fig. 1;
Figure 6 shows that and adopt the present invention to return the diagram oscillogram of depositing operation; And
Figure 7 shows that the present invention returns the process flow diagram of depositing operation.
Embodiment
Carry out the block scheme of the system 300 of external read operation simultaneously during the programming operation in Figure 3 shows that in fast erasing apparatus.Fig. 3 comprises a flash memory device 301, a destination address position 303, a source address location 305, a data register 307 and a cache register 309.A kind of state machine (not shown), it can for example be co-located on the integrated circuit (IC) wafer that comprises described flash memory device 301, is designed to control and executive routine, and is as described below.
In one embodiment, described flash memory device 301 is a kind of and nand flash device.Perhaps, described flash memory device 301 can be based on or/no type or with the logical unit of type.Deposit operational order in case send back, just read in the described data register 307 from the data of described source address location 305.The data of reading in data register 307 can be, for example, and a whole page data.In one embodiment, the size of the described page is made up of to 2 kilobyte 256 bytes or 512 bytes.In case described source data is read in the described data register 307, described data register 307 writes described cache register 309 with the mirror-image copies of these data simultaneously, (represent with write operation 311) to described destination address position 303 and simultaneously these data are write (that is programming) conceptive.Because writing fast erasable memory location required time may be much longer than read the required time from fast erasable memory location, so can by described serial bus 109 will be in described cache register 309 mirror-image copies of storage data be read in the described microcontroller 107 (conceptive with read operation 313 expressions), and described data are write described purpose source position 303.More than, with reference to Fig. 4 the concrete relative time of each following operation is done narration in more detail.
In case be sent to described microcontroller 107 to the described data of small part, described microcontroller 107 just begins these data and expectation are made comparisons in the data that described source address location 305 stores originally.If described microcontroller 107 is determined to described data and loses locally completeness, for example, because of the whole bit-errors that charge escaping causes, described microcontroller 107 reduces these data by error-correcting code technique as well known to those skilled in the art.If described data are by error correction, described microcontroller 107 is write described cache register 309 to corrected data with series system again by described serial bus.Subsequently, described cache register 309 just transmits described data to described data register 307, and it writes this corrected data described destination address position 303 again.Below, with reference to Fig. 4 more detailed narration is done in typical error-correction operation.
Even described data do not require error correction, still required than prior art among Fig. 1 T.T. of whole operation time of origin of the present invention is weak point.Will be appreciated that of the present invention saving time significantly, it, and can read described cache register 309 and again the data 313 of reading from described cache register 309 are passed to described microcontroller 107 simultaneously to described destination locations 303 by write data side by side 311.Therefore, error correction if desired, this error correction method with write out described data and begin simultaneously to described destination locations 303.On the contrary, prior art only relies on in-sequence operational step, and it relies on and utilizes satisfying the position or satisfying the byte transmission of serial bus and associated very much.
Deposit the operation except carrying out pure time, the present invention can also be added in one page additional or random data and from the data that read of described source address location 305.Below, with reference to Fig. 6 and 7 this random data is inserted operation and do more complete narration.
With reference to Fig. 4, the relative time among time figure expression the present invention and Fig. 2 between the prior art is poor.According to Fig. 4, trace 401 expression data copy described data register 307 to from described source address location 305.In case copy described data register 307 to, shown in trace 403, just these data are written to described cache register 309.Two traces 405,407 are for optionally afterwards.
Selectivity of being made by described microcontroller 107 of trace 405 expressions reads.If described microcontroller 107 check data, then check in described source-register 305 data integrity and by trace 407 expression.By selective trace 405,407, described microcontroller 107 can guarantee just that the data in described source position 305 have been verified and effectively (for example, this check can be ECC).System all can not finish with the selectivity read step shown in the trace 405 now.
If error correction/checking procedure or random data are added in the data that read from source position 305, afterwards, in selecting trace 405, by described serial bus 109 data are read described microcontroller 107 from described cache register 309.Then, error correction data or random data are read back in the cache register 309 from described microcontroller 107 by described serial bus 109 shown in the trace 407 as selecting.
Select trace 407 expressions one to be sent to the data of described microcontroller 107 from described cache register 309.Transmit for series connection by the data that described serial bus 109 is sent to described microcontroller 107 owing to get memory storage 301 from described fast wiping, it is much longer to write the internal data delivery time that described microcontroller 107 desired total transmission times get in the memory storage 301 than described fast wiping from described cache register 309.In case data begin to be sent to described microcontroller 107, whether described microcontroller 107 just needs error correction to make decision to received data.
In addition, described microcontroller 107 adds data randomly to the page data that selects part that is read from described source address location 305.It shown in the trace 409 relative time of any error correction.It should be noted that described microcontroller 107 just can begin error correction immediately when receiving at least a portion data.
If carry out error correction or insert random data, then as shown in trace 411, described microcontroller 107 should be revised data back to cache register 309.As shown in trace 413, the mirror-image copies of these correction data is sent to described data register 307 from described cache register 309, and the described destination locations 303 of Zhongdao.After perpendicular line 415 is illustrated in that error correction produces or inserts additional random data by described microcontroller 107, require correction data is write the relative time of described destination locations 303.
In addition, if do not need error correction or do not add random data (that is, skipping over),, then shown in perpendicular line 417, return to deposit to operate and finish in case data are write described destination locations 303 by selecting the step shown in the trace 405,407.
With reference to Fig. 4, time diagram represents that the relative time between the time diagram 450 of prior art among typical time diagram 400 of the present invention and Fig. 2 is poor.According to Fig. 4, trace 401 expressions copy the data of described data register 307 to from described source address location 305.In case copy described data register 307 to, then shown in trace 403, just these data are written to described cache register 309.
Two traces 405,407 are for optionally afterwards.If described microcontroller 107 is carried out the step of the data integrity of a check in described source 305 and made any modification, then shown in trace 407, trace 405 is represented the selectivity read step of being undertaken by described microcontroller 107.By just like the selection step shown in the trace 405,407, described microcontroller 107 can be guaranteed that described data source is verified and effectively (for example, pass through ECC).Flash memory device all can not be finished this step now.(only can before the present invention, finish) by the step shown in the trace 407.
In addition, described microcontroller 107 can skip over the step shown in trace 405,407.In this case, described microcontroller 107 just loses the dirigibility of correction data before programming.
If error correction/checking procedure or random data are added to 305 data that read from the source position, afterwards, in selecting trace 405, data are read described microcontroller 107 from described cache register 309 by described serial bus 109.Then, error correction data or random data read back in the cache register 309 of selection shown in trace 407 from described microcontroller 107 by described serial bus 109.It should be noted that,,, shown in the first relative time line 415, return to deposit to operate and finish in case described data are write described destination address position 303 if do not need error correction or do not add random data.If carry out error correction or insert random data, then shown in trace 411, described microcontroller 107 should be revised data back to cache register 309.On trace 409, the mirror-image copies of these correction data is sent to described data register 307 and finally shown in trace 411, passes to described destination locations 303 from described cache register 309.The time that 417 expressions of the second relative time line require described microcontroller 107 to carry out and read is simultaneously correctly write described destination locations 303 (as described below, as to make comparisons in trace 459 and prior art) to guarantee described data.Guarantee the correct transmission to described destination locations 303 of described data by the circuit in the described design from described cache register 309.
Data to described data register 307 transmit from described cache register 309 in trace 409 expressions.Importantly, as trace 411 and 413 respectively shown in, with data when cache register 309 is sent to microcontroller 107, data transmit can also be simultaneously from described data register 307 to described purpose 303.Transmit for series connection by the data that described serial bus 109 is sent to described microcontroller 107 owing to get memory storage 301, get internal data delivery time in the memory storage 301 so require then to be longer than described fast wiping from the total transmission time that described cache register 309 is write described microcontroller 107 from described fast wiping.In case data begin to be sent to described microcontroller 107, whether described microcontroller 107 just needs error correction to make decision to received data.
Time diagram 450 is depicted as the relative time that requires the pure sequential grammar of transmission data according to prior art scheme shown in Figure 2.In the prior art, data are sent to described data register 209 and pass to microcontroller 107 (trace 453) by serial bus 109 subsequently from described source address location 203 on trace 451.Only after data were sent to microcontroller 107, described data register just can write data to described purpose 205 (trace 455).For final data check or data read, data from described purpose 205 read back described data register 209 (trace 457) and afterwards by described data register 209 to described microcontroller 107 (trace 459).Figure 4 shows that, if the present invention needs error correction or random data to insert, then can than require data by source address location 203 in data register 209 passes to time of time much shorter of prior art microcontroller 107, finish from described data register 307 to returning of described destination address position 303 deposit operation (trace 411 and 455 and the described first relative time line 415 make comparisons).Even can make improvements, transmit to guarantee data but still will carry out an operation bidirectional to prior art.
Described microcontroller 107 is checked the data integrity that is transmitted from described source address location 203 and need to be determined whether the error correction (not shown).If detect data integrity arranged any lacking, art methods will repeat beginning at trace 451 again.Moreover, it should be noted that data transfer step in the prior art can not be carried out (that is, side by side actual figure reportedly send step) simultaneously.
Figure 5 shows that returning of a prior art deposit typical waveform Figure 50 0 of operation.Described oscillogram 500 comprises a RDY/ BUSY signal wire 501 and an I/O line 503.Described oscillogram 500 expression typical cases return and deposit the required method step of operation.
Deposit operation for described time by read operation 505 beginning, obtain source address 507 afterwards and be back to deposit and operate 509 and send one and read instruction.When described signal wire 501 expressions determine that low signal is applied to the status pin (not shown) of described integrated circuit.It should be noted that, determine RDY/ BUSY signal when low logic level, described device was just busy during it was illustrated in the signal reduction.Therefore, during reading, determine t
R511 low logic levels are applied on the described status pin, prevent that by this any other from reading or program/write operation takes place.In case the data in described source address location are read, return and deposit programming operation 513 by determining that at first purpose source address 515 begins, return afterwards that depositing affirmation operates 517 to check described destination address position 105 not programme.Described signal wire 501 expressions one programming (that is, writing) cycle t
PROG519, determine that wherein low logic level is applied to described status pin.In general, in a kind of Nonvolatile memory devices, particularly a kind of and nand flash device, t
PROG＞t
RDescribed programmed method is slow, and this is because programming mechanism itself causes (that is, needing to produce high voltage).After read states step 512 is carried out, be I/O check 523.Described I/O check 523 return deposit in the programming operation with qualified/defectively write down any error.In order to check the integrality of writing purpose source address 105 data, finally read step 525 and be determined the back execution again, afterwards at read cycle t in described purpose source address 527
RDetermine during 529 that a low logic level is applied to described status pin.
According to Fig. 6, be depicted as one of the present invention time and deposit typical waveform Figure 60 0 of operation.Described oscillogram 600 comprises an inverted read enable trace, RE601, a RDY/ BUSY trace 603 and an I/O trace 605.
Returning among Fig. 6 deposited returning among operation and Fig. 5, and to deposit operation similar, but some obviously reaches important difference.For example, at least one selectivity random data input step 607 can add be inserted in destination address determine with programming affirmation step between.Deposit operation for of the present invention time and carry out read operation, be one afterwards and guarantee a page programming operation.Read and programming operation between, data are read and by inserting additional random data in page or leaf and revise.Because the programming time can be grown read time significantly, therefore returning in prior art has the significant stand-by period in the deposit system.Flash memory device 301 of the present invention utilizes the described stand-by period side by side to read described data, and these data can obtain in described cache register 309 by switching the described enabling signal of reading.Here, data add and are inserted in the data stream that described source address location 305 reads and and become the part of described random data input programming 607a.As adding the part of depositing programming of returning that is inserted into former source address location 305 data, only require address, attached purpose hurdle 607b read data 607c (that is, the column address of described random data is identical with the column address of described former data).Whenever requiring that the varying number random data is pieced together different piece into former data, then can repeat described random data input step 607.
In addition, a selectivity read states-I/O loop 611 can be at programming (that is, writing) t
PROGCarry out during this time.Moreover, it should be noted that, because at programming (that is, writing) t
PROGPulse produces described startup (RE) signal of reading during 609, and 615i-615j is so read in additional data 613n-613m from cache register 309.Even when additional data read from and when being programmed into described flash memory device 301, this parallel outer read operation during interior programming operation can significantly reduce back to deposit to be operated the required time.If described t
PROGCan compare with waiting the series connection access of reading data, then described throughput can become maximum because free time becomes the shortest.
Figure 7 shows that method flow diagram 700 of the present invention.Described method flow diagram 700 comprise one read instruction operation 701, one source address 703 the operation of packing into, deposit for one time and read 705 affirmation step and carry out interior read operation step 707.Pack into and deposit programming 711 and suitable destination address 713 for described time.
Described suitable destination address 713 can be selected random data input step 715 in case pack into.Described random data input step 717 is begun by desired data 721 in pack into the intermediate address 719 and the described source address location 305 of packing into.After the described data of packing into, make described cache register 309 upgrade 723.Make whole required random data of whether packing into and determine 724.Whole random data if pack into, then described method proceed to final step 733 to carry out programming phases, preset data register and to upgrade cache register.
If do not need described selection random data input step 715, described method will copy data 725 to described data register 307 by described cache register 309.Setting described status pin (not shown) is that high logic level 727 has been ready to read to the user to represent described flash memory device 301.Whether in step 731, making one has the available decision of more data.Can obtain if any more data, then described method turns back to described data output step 729 and will proceed to data and no longer obtains.
Though be described in detail and accompanying drawing described a kind of during interior programming operation, give parallel outside the flash memory device of read operation, yet those skilled in the art all can recognize, can easily dream up other embodiment.In the specified scope that does not break away from said apparatus.For example, the exemplary embodiments that can be used as special time figure and oscillogram flash memory device of the present invention.Yet those skilled in the art can easily rearrange some operation by described time or oscillogram, and still can reach the same required result that the operation required time appears back depositing in shortening.In addition, though this paper particularly with reference to ' with non-type ' flash memory, employing ' and type ' or ' or/no type ' flash memory also can similarly return and deposit operation.Therefore, protection scope of the present invention is only limited by these claims.
Claims (25)
- One kind the memory storage internal programming simultaneously outside the executive system of read operation, it is characterized in that described system comprises:One storage device of storage data randomly, described storage device comprises memory location, a source, a purpose memory location, a data register and a cache register, described data register formation side by side writes data to described purpose memory location and described cache register, electric connection can be made with described data register in memory location, described source and described purpose memory location, and described data register can be made electric connection with described cache register again; AndOne checking is any by making the demo plant that electric connection receives the accuracy of data with described memory storage, if described demo plant constitutes described data again when inaccurate, for described data provide error correction.
- 2. the system as claimed in claim 1 is characterized in that, described memory storage is a kind of flash memory device.
- 3. system as claimed in claim 2 is characterized in that, described fast erasable storage device is a kind of and non-type device.
- 4. the system as claimed in claim 1 is characterized in that, described demo plant is a kind of microcontroller.
- 5. the system as claimed in claim 1 is characterized in that, described demo plant is a kind of microprocessor.
- 6. the system as claimed in claim 1 is characterized in that, passes through a kind of serial bus electric connection between described memory storage and the described demo plant.
- 7. the system as claimed in claim 1 is characterized in that, described data accuracy reaches by making described data and the data comparison that is stored in memory location, described source originally.
- 8. the system as claimed in claim 1 is characterized in that, described data accuracy reaches by a kind of error correction coding.
- 9. the system as claimed in claim 1 is characterized in that, described demo plant constitutes again random data added and is inserted in the described data accepted.
- One kind the memory storage internal programming simultaneously outside the manner of execution of read operation, it is characterized in that step since described method comprises:To be stored in the former copying data of source address location in the described memory storage to a data register; AndMake the described former data or the mirror image that copy described data register to, and simultaneously from described data register with described former copying data to a cache register and a destination locations.
- 11. method as claimed in claim 10 is characterized in that, described method is further comprising the steps of:The former data that are stored in described cache register are sent to a kind for the treatment of apparatus;By making former data that transmitted and the anticipatory data that is stored in described source address location relatively verify the integrality of described former data, to find out the latent fault that has transmitted former data described; And if detect any mistake, transmitted former data and carried out error correction described, form error correction data by this.
- 12. method as claimed in claim 11 is characterized in that, described method is further comprising the steps of:Error correction data is sent to described cache register from described treating apparatus;Make the copy of a described error correction data to described data register become mirror image from described cache register; AndMake described error correction data copy described destination locations to from described data register.
- 13. method as claimed in claim 11 is characterized in that, described method is further comprising the steps of:Before form revising error correction data, random data added be inserted into described error correction data;The error correction data of revising is sent to described cache register from described treating apparatus;Make the copy of a described correction error correction data to described data register become mirror image from described cache register; AndCopy described correction error correction data to described destination locations from described data register.
- 14. method as claimed in claim 11 is characterized in that, described method is further comprising the steps of:Random data added to be inserted in the described former data to form revise data;Make described correction data be sent to described cache register from described treating apparatus;Make the copy of a described correction data to described data register become mirror image from described cache register; AndCopy described correction data to described destination locations from described data register.
- 15. method as claimed in claim 11 is characterized in that, described treating apparatus is a kind of microcontroller.
- 16. method as claimed in claim 11 is characterized in that, described treating apparatus is a kind of microprocessor.
- 17. the executive system in the read operation outside the while of memory storage internal programming is characterized in that described system comprises:One memory storage of storage data randomly, described memory storage comprises memory location, a source, a purpose memory location, a data register and a cache register, described data register formation side by side writes data to described purpose memory location and described cache register, electric connection can be made with described data register in memory location, described source and described purpose memory location, and described data register can be made electric connection with described cache register again; AndOne checking is any by making the demo plant that electric connection receives the accuracy of data with described memory storage, if described microcontroller constitutes described data again when inaccurate, for described data provide error correction.
- 18. system as claimed in claim 17 is characterized in that, described memory storage is a kind of flash memory device.
- 19. system as claimed in claim 18 is characterized in that, described flash memory device is a kind of and non-type device.
- 20. system as claimed in claim 17 is characterized in that, described treating apparatus is a kind of microcontroller.
- 21. system as claimed in claim 17 is characterized in that, described treating apparatus is a kind of microprocessor.
- 22. system as claimed in claim 17 is characterized in that, passes through a kind of serial bus electric connection between described memory storage and the described treating apparatus.
- 23. system as claimed in claim 17 is characterized in that, described data accuracy reaches by making described data and the data comparison that is stored in memory location, described source originally.
- 24. the system as claimed in claim 1 is characterized in that, described data accuracy reaches by a kind of error correction coding.
- 25. system as claimed in claim 17 is characterized in that, described treating apparatus constitutes again random data added and is inserted in the described data accepted.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/875,652 US7159069B2 (en) | 2004-06-23 | 2004-06-23 | Simultaneous external read operation during internal programming in a flash memory device |
| US10/875,652 | 2004-06-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101031895A true CN101031895A (en) | 2007-09-05 |
Family
ID=35507446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200580024560XA Pending CN101031895A (en) | 2004-06-23 | 2005-06-01 | Simultaneous external read operation during internal programming in a flash memory device |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7159069B2 (en) |
| EP (1) | EP1769362A2 (en) |
| JP (1) | JP2008504637A (en) |
| KR (1) | KR20070024624A (en) |
| CN (1) | CN101031895A (en) |
| TW (1) | TW200613978A (en) |
| WO (1) | WO2006007264A2 (en) |
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| CN103035291A (en) * | 2011-10-04 | 2013-04-10 | 爱思开海力士有限公司 | Semiconductor device and method of operating the same |
| CN103035291B (en) * | 2011-10-04 | 2017-05-03 | 爱思开海力士有限公司 | Semiconductor device and method of operating the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2006007264A2 (en) | 2006-01-19 |
| EP1769362A2 (en) | 2007-04-04 |
| US20050289314A1 (en) | 2005-12-29 |
| TW200613978A (en) | 2006-05-01 |
| WO2006007264A3 (en) | 2007-05-31 |
| JP2008504637A (en) | 2008-02-14 |
| KR20070024624A (en) | 2007-03-02 |
| US7159069B2 (en) | 2007-01-02 |
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