JP4332132B2 - Memory controller, flash memory system, and flash memory control method - Google Patents

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, flash memory performance (storage capacity, reliability, operation speed, etc.) has been improved, and it is being used as a nonvolatile recording medium for storing programs and the like.

  Due to the characteristics of the flash memory, data may not be written normally (incorrect data may be mixed). For this reason, a procedure (verification) is required in which after the data is written, the written data is read and the normal writing is confirmed. The most reliable verification method is a method of collating all bits of data, but this method is time consuming and lacks convenience.

For this reason, the data is divided into predetermined bits, and the checksum value obtained by sequentially adding the data is obtained, and by confirming a match between the checksum value and the expected value calculated in advance, the verification can be shortened. A method for achieving time has been proposed (for example, Patent Document 1).
JP 2001-175478 A

  However, in the above method, since it is necessary to obtain the expected value of the checksum in advance, considering the time for obtaining the expected value of the checksum at the time of data creation, the verification can be shortened. That's not enough.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a flash memory control method, a memory controller, and a flash memory system including the memory controller that can suppress verification time.

A memory controller according to a first aspect of the present invention includes a writing unit that writes data to a flash memory in response to an instruction from a host system that uses the flash memory as a storage medium, and a memory that stores data written to the flash memory. and error correction code generating means for generating an error correction code, in parallel with the error correction code writing means for writing the error correction code in the flash memory, and the writing means for writing data to the flash memory, wherein an expected value calculation means for calculating an expected value of the checksum of the data being written to the flash memory, and reading means for reading the data written in the flash memory, the error correction code that is written in the flash memory And error correction code reading means for out look, the errors included in data read from the flash memory, and correction means for correcting, based on the error correction code read from the flash memory, the writing means After writing the data to the flash memory, the written data is read from the flash memory, the checksum calculation means for calculating the checksum value of the read data, and the expected value of the checksum calculated by the expected value calculation means And a check means for comparing the checksum value calculated by the checksum calculation means to determine whether or not data has been correctly written to the flash memory, and the checksum calculation means includes: If the read data contains errors And calculates a checksum value of the data whose error is corrected by said correcting means.
In the present invention, the host system refers to a device that uses a flash memory as a recording medium.

  The expected value calculation means is preferably composed of an adder by hardware.

  The checksum calculation means is preferably composed of an adder by hardware.

  The expected value calculation means and the checksum calculation means may change the number of bits of the expected value and checksum value to be calculated in response to a request from the host system.

  The expected value calculation unit and the checksum calculation unit may calculate the number of bits of the expected value and the checksum value to be equal to the bit width of the bus connecting the memory controller and the flash memory.

  A flash memory system according to a second aspect of the present invention includes a memory controller having at least one of the above characteristics and a flash memory.

A flash memory control method according to a third aspect of the present invention includes a writing step of writing data to the flash memory in response to an instruction from a host system that uses the flash memory as a storage medium, and writing to the flash memory. and error correction code generation step of generating an error correction code of data, the error correction code writing step of writing the error correction code on the flash memory, Doo data to the flash memory by the writing step writing write Murrell in parallel, the expected value calculation step of calculating an expected value of the checksum of the data to be written to the flash memory, a reading step of reading write Mareta data from the flash memory writing by said write step, the write stearate An error correction code reading step of reading out the error correction code of the data written by the memory from the flash memory, and an error included in the data read out by the reading step is read by the error correction code reading step. A correction step for correcting based on the error collection code; a checksum calculation step for calculating a checksum value of the data read by the reading step; and an expected value of the checksum calculated by the expected value calculation step; the collates the checksum value calculated by the checksum calculating step, and a determination step of determining whether or not data has been written correctly, there is an error in the data read by the reading step If The serial checksum calculation step, and calculates a checksum value of the data whose error is corrected by said correction step.

  According to the present invention, since the expected value of the checksum is obtained in parallel with the data writing to the flash memory, the verification time can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, A ROM (Read Only Memory) 12, a first adder 15, a first register 16, a second adder 17, and a second register 18 are configured. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 according to the program recorded in the ROM 12. Specifically, the microprocessor 6 performs processing such as writing processing for writing data to the flash memory 2, reading processing for reading data, creation of an address conversion table, creation of an erased block search table, and the like. Control each part to do.

  The host interface block 7 exchanges data, address information, status information, external command information, and the like with the host system 4. That is, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. In such a state, the data supplied from the host system 4 to the flash memory system 1 is taken into the controller 3 through the host interface block 7 and the data supplied from the flash memory system 1 to the host system 4 is The host interface block 7 is supplied to the host system 4 as an exit.

  More specifically, the host interface block 7 is a command register that temporarily stores a host address and an external command supplied from the host system 4, a sector number register that stores the size of data to be written or read, and a write or read command. An LBA (Logical Block Addressing) register for storing a logical block address of data to be performed. Information is exchanged with the host system 4 via these registers.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2.

The flash memory interface block 10 exchanges data, address information, status information, internal command information, and the like with the flash memory 2 via the internal bus 14.
In the flash memory system 1 of the present embodiment, the internal bus 14 is assumed to have a bit width of 16 bits.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines processing procedures such as writing processing, reading processing, creation of an address conversion table, creation of an erased block search table, and the like.

  When data is written to the flash memory 2, the first adder 15 cooperates with the first register 16 to divide the data to be written for each bit number of the internal bus 14 and add the accumulated value (checksum). Expected value). More specifically, the first adder 15 is an adder having a bit width equal to that of the internal bus 14 (that is, 16 bits), and the write data supplied from the internal bus 14 and the first register 16 The supplied value is added, and the value is held in the first register 16.

  The first register 16 is a storage element that temporarily holds the value output from the first adder 15. The first register 16 returns the held value to the first adder 15.

  The second adder 17 cooperates with the second register 18 to calculate an accumulated value (check sum value) obtained by dividing and adding data read from the flash memory 2 for each bit number of the internal bus 14. More specifically, the second adder 17 is an adder having a bit width equal to that of the internal bus 14 (ie, 16 bits), and is supplied from the read data supplied from the internal bus 14 and the second register 18. And the value to be stored in the second register 18.

  The second register 18 is a storage element that temporarily holds the value output from the second adder 17. The second register 18 returns the retained value to the second adder 17.

[Description of flash memory]
Next, the flash memory 2 will be described. FIG. 2 is a diagram schematically showing a memory structure of the flash memory 2. As shown in FIG. 2, the flash memory 2 is composed of a page which is a processing unit for reading and writing data and a block which is a data erasing unit.

  The page is composed of a 512-byte user area 25 and a 16-byte redundant area 26, for example. The user area 25 is an area for mainly storing data supplied from the host system 4, and the redundant area 26 is an area for storing additional information such as an error collection code, a block status, and a corresponding logical block address. is there.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25 and is generated by the ECC block 11. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

  The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored, so whether the corresponding logical block address is stored or not is determined whether the block is an erased block. Judgment can be made. That is, when the corresponding logical block address is not stored, it can be determined that the block is an erased block.

[Description of logical block address and physical block address]
Since the flash memory 2 cannot overwrite data, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data (data before rewriting). ) Must be performed in a two-step process of erasing the block in which it was written. At this time, since erasure is processed in units of blocks, data of all pages of a block including a page in which old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

  When data is rewritten as described above, since the data after rewriting is written in a block different from that before rewriting, the logical block address given from the host system 4 side and the block address in the flash memory 2 are used. The correspondence with the physical block address dynamically changes every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area 26 of the flash memory 2, and each time data is rewritten, the correspondence relationship of the part involved in the rewriting is updated. The

[Description of zone configuration]
Next, zone management for assigning a zone composed of a plurality of blocks in the flash memory 2 to a logical block address space will be described with reference to the drawings. FIG. 3 shows an example in which a zone is composed of 512 blocks. In the example shown in FIG. 3, the zone is composed of 512 blocks B0000 to B0511 (physical block addresses 0000 to 0511), and each block is composed of 32 pages P00 to P31 which are units of read and write processing. It is configured. Here, the block is a unit of erasing processing, and the page is a unit of reading and writing processing.

In addition, when this zone is allocated to a logical block address space, it is allocated to a logical block address space having a smaller number of blocks than the number of blocks constituting the zone in consideration of the occurrence of defective blocks. This allocation is normally performed according to the specifications of the flash memory 2. For example, a zone composed of 512 blocks is allocated to a logical block address space of 500 blocks, or a logical block address of 490 blocks. Can be assigned to the space. At this time, if the number of blocks allocated to the space of the logical block address is increased, the use efficiency of the flash memory 2 is improved, but the allowable amount for the generation of defective blocks (the allowable number of generated defective blocks) is reduced.
In the flash memory system 1 of the present embodiment, as shown in FIG. 4, a zone composed of 512 blocks is assigned to a space of logical block addresses for 496 blocks.

[Description of address translation table]
Next, the address conversion table will be described. The address conversion table manages the correspondence between logical block addresses and physical block addresses.
FIG. 5 shows an example of an address conversion table for the zone 0 shown in FIG. 4, and the physical block address in the flash memory 2 in which data corresponding to each logical block address is stored is a logical block. Described in the order of addresses. For a logical block address in which no data is stored in the flash memory 2, a flag indicating that no data is stored in the portion corresponding to the logical block address in the address translation table (not a physical block address) , A flag indicating that the corresponding data is not stored is referred to as an unstored flag).

  For example, when the address conversion table for zone 0 shown in FIG. 4 is created, the microprocessor 6 secures an area in the work area 8 (SRAM) where a physical block address for 496 blocks can be described, and the physical block address. An unstored flag is set as an initial setting in the area describing. Thereafter, the microprocessor 6 controls the flash memory interface block 10 to sequentially read the redundant areas 26 of the blocks constituting the zone 0 of the flash memory 2, and writes the logical block address (corresponding to the corresponding logical block address) in the redundant area 26. In the address conversion table, the physical block address of the block in which the logical block address is described is described in the portion corresponding to the logical block address.

  It should be noted that the unstored flag described in the initial setting remains as it is for the part where the physical block address is not described in the address conversion table creation process.

[Description of erased block search table]
Next, the erased block search table will be described with reference to the drawings. The erased block search table is a table for searching for an erased block that can be a data write destination.

  First, a method for searching for an erased block using the erased block search table will be described. For example, when searching for an erased block in the zone shown in FIG. 4, the microprocessor 6 secures a 512-bit area on the SRAM and assigns each block constituting the zone to each bit in the area. Create a block search table.

  FIG. 6 is a conceptual diagram conceptually showing the erased block search table for zone 0 and zone 1 shown in FIG. Here, bits on the erased block search table for zone 0 correspond to blocks B0000 to B0511 (physical block addresses 0000 to 0511), and bits on the erased block search table for zone 1 correspond to block B0512. To B1023 (physical block addresses 0512 to 1023).

  For the correspondence between the bits on the erased block search table and the blocks constituting the zone, the bits on the erased block search table shown in FIG. 6 are changed from the upper row to the lower row. Each row is associated from left to right in the order of physical block addresses. Therefore, in the erased block search table for zone 0, the upper left bit corresponds to the block B0000 (physical block address 0000) and the lower right bit corresponds to the block B0511 (physical block address 0511). To do.

  The bit on the erased block search table indicates whether the block is an erased block with “0” and “1”. For example, when data is written (or a defective block) Is set to “0” in the bit, and “1” is set in the bit when data is not written (in the case of an erased block).

  The erased block search table can be created together when creating the address conversion table. For example, the microprocessor 6 sets “0” in the area on the work area 8 (SRAM) for creating the erased block search table, and the logical block address corresponding to the redundant area 26 of each block is also a bad block. If the block status indicating that there is no description, the bit corresponding to the block is set to “1” so that the address translation table can be created together. In other words, if this process is performed when data described in the redundant area 26 of the block constituting the zone is read, only “1” is set to the bit corresponding to the erased block, and the block is not the erased block. The corresponding bit remains “0” set in advance.

  Further, when data is written to the erased block, the microprocessor 6 changes the bit corresponding to the block from “1” to “0”, and the block in which the data is written is changed to the block. When erased, the bit corresponding to the block is changed from “0” to “1” to update the erased block search table as needed.

  Next, a case where an erased block is searched using this erased block search table will be described with reference to FIG. FIG. 7 shows an erased block search table for zone 0. For example, each bit in the top row corresponds to blocks B0000 to B0007 (physical block addresses 0000 to 0007), and the bottom row corresponds to blocks B0504 to B0511 (physical block addresses 0504 to 0511). To do.

  The microprocessor 6 scans the erased block search table from the upper row to the lower row. The microprocessor 6 scans each row in the erased block search table from left to right. That is, the microprocessor 6 starts from the bit corresponding to the block B0000 (physical block address 0000) (the leftmost bit in the top row) to the bit corresponding to the block B0511 (physical block address 0511) ( The rightmost bit in the bottom row is scanned, and the bit “1” corresponding to the erased block is searched.

  When searching the erased block search table shown in FIG. 7, since the third bit from the left of the second row from the top is “1”, the microprocessor 6 ends the search here, and this bit The block B0010 (physical block address 0010) corresponding to is specified as the data write destination block.

  The next search starts scanning from the fourth bit from the left in the second row from the top. Since the fifth bit from the left in the fourth row from the top is “1”, the microprocessor 6 The search ends here, and a block B0028 (physical block address 0028) corresponding to this bit is specified as a block to which data is written. Thereafter, such a search is continued, and when the scanning proceeds to the rightmost bit in the bottom row, the processing returns to the leftmost bit in the top row.

[Description of writing process]
Next, write processing executed in response to a command from the host system 4 will be described with reference to a time chart shown in FIG. In this writing process, the expected value of the checksum is calculated along with the data writing to the flash memory 2, and the checksum value is calculated and verified after the writing.
A command requesting execution of the writing process from the host system 4 is written in the command register of the host interface block 7. The logical block address to which data is written and the size of the data to be written are written to the LBA register and the sector number register of the host interface block 7, respectively.

  In response to the instruction written in the command register, the microprocessor 6 writes data into the block identified by searching the erased block search table. In this writing process, the microprocessor 6 controls the flash memory interface block 10 to write data to a page in the writing destination block via the internal bus 14. The microprocessor 6 writes an error correction code, a logical block address, etc. in the redundant area 26 of the block in which the data is written.

  At this time, as shown in FIG. 8A, the data to be written to the flash memory 2 is divided into bit widths (16 bits) of the internal bus 14 and sequentially stored in the flash memory 2 from the top of the data. Sent.

The data written to the flash memory 2 via the internal bus 14 is also supplied to the first adder 15 at the same time. As shown in FIG. 8B, the first adder 15 adds the data received via the internal bus 14 and the data held in the first register 16, and The held value is updated to the added value. The above addition is repeated, and the value held in the first register 16 when reaching the end (Dn) of the data written to the flash memory 2 becomes the expected value of the checksum.
Note that the value held in the first register 16 is reset to 0 at the start of the writing process. In addition, when a so-called overflow occurs due to repeated addition of data, the overflow digit is ignored and only the value of the bit width of the internal bus 14 (that is, the lower 16 bits of the added value) is focused on. The expected value shall be obtained.

  When the writing of data to the flash memory 2 is completed, the microprocessor 6 controls the flash memory interface block 10 to read the written data via the internal bus 14 and confirm whether the data has been written normally. (Verification).

  In this process, the written data is read to the buffer 9 and an error included in the read data is corrected based on the error correction code. The data in which the error is corrected is divided for each bit width (16 bits) of the internal bus 14 and sent to the internal bus 14 side as in the case of writing data. At this time, the flash memory 2 is kept in an inactive state. This data is supplied to the second adder 17 connected to the internal bus 14. As in the case of writing data, as shown in FIG. 8B, the second adder 17 adds the data received via the internal bus 14 and the data held by the second register 18. Then, the value held in the second register 18 is updated to the added value. The above addition is repeated, and the value held in the second register 18 when the data read from the flash memory 2 reaches the end (Dn) becomes the checksum value.

Note that the value held in the second register 18 is reset to 0 at the start of verification.
If so-called digit overflow occurs by repeating the addition of data, the overflow digit is ignored, and only the value of the bit width of the internal bus 14 (that is, the lower 16 bits of the added value) is taken into consideration. Is to be sought.

  When the data reading for obtaining the checksum value is completed, the microprocessor 6 collates the expected checksum value held in the first register 16 with the checksum value held in the second register 18. . That is, if the expected value of the checksum held by the first register 16 matches the checksum value held by the second register 18, the microprocessor 6 determines that the data has been written normally. Then, the writing process is terminated. When the expected checksum value held by the first register 16 and the checksum value held by the second register 18 do not match, the microprocessor 6 does not perform the writing process normally. This is notified to the host system 4.

  In addition, when old data corresponding to the logical block address supplied from the host system 4 side exists in the write process (when overwriting), the old data is erased after the new data write process. Is done. The physical block address of the block storing the old data to be erased can be obtained based on the address conversion table shown in FIG. In this erasing process, the microprocessor 6 controls the flash memory interface block 10 and erases the data of the physical block address of the block storing the old data from the flash memory 2 via the internal bus 14.

[Description of read processing]
The read process is executed in response to a command from the host system 4.
A command requesting execution of read processing from the host system 4 is written in the command register of the host interface block 7. Further, the logical block address of the data to be read is written in the LBA register of the host interface block 7.

  In response to the instruction written in the command register, the microprocessor 6 converts the logical block address written in the LBA register into a physical block address (data corresponding to the logical block address is based on the address conversion table shown in FIG. 5). Converted to the physical block address of the stored block).

  Subsequently, the microprocessor 6 controls the flash memory interface block 10 and stores it in the page in the block in which data corresponding to the logical block address given from the host system 4 side is stored via the internal bus 14. The read data is read out to the buffer 9.

  The microprocessor 6 corrects an error included in the data read to the buffer 9 based on an error correction code added to the data. Then, the microprocessor 6 controls the host interface block 7 to supply the corrected data to the host system 4 via the external bus 13, and ends the reading process.

  As described above, the flash memory system 1 according to the present embodiment obtains the expected checksum value in parallel with the data writing to the flash memory 2. For this reason, it is not necessary to obtain the expected checksum value of the data to be written in advance.

  Further, the flash memory system 1 according to the present embodiment uses an adder (first adder 15 and second adder 17) realized by hardware to obtain an expected checksum value and a checksum value. Is used. Therefore, no additional processing time is required to obtain the expected checksum value and the checksum value, and an increase in the time required for the writing process caused by the verification can be suppressed.

  In particular, in the flash memory system 1 of the present embodiment, the bit width of the adder for obtaining the expected checksum value and the checksum value is equal to the bit width of the internal bus 14. For this reason, when calculating the expected value and the checksum value, it is not necessary to divide the data and supply it to the adder, and it is possible to suppress an increase in the time required for the writing process caused by the verification.

  In the above embodiment, the case has been described in which the number of bits for delimiting when obtaining the checksum value (that is, the bit width of the adder) is equal to the bit width of the internal bus 14, but when obtaining the checksum value. The number of bits of the delimiter may be variable.

  In this case, for example, the bit width for calculating the checksum is set in the LBA register, and the microprocessor 6 divides the data for each set bit width and supplies the data to the first adder 15 to check the checksum. What is necessary is just to calculate an expected value. Similarly, for the read data, the microprocessor 6 may divide the data for each set bit width and supply it to the second adder 17 to calculate the checksum value.

  Further, the flash memory system 1 in the above embodiment includes the first adder 15 and the first register 16 for obtaining the expected checksum value, the second adder 17 for obtaining the checksum value, The case of having the second register 18 has been described as an example. However, the first adder 15 and the second adder 17 can be shared by one adder. Similarly, the first register 16 and the second register 18 can be shared by one register. It can be shared.

  In this case, the expected checksum value obtained in parallel with the data writing is recorded in the work area 8, and the same adder and register as when the expected checksum value was obtained in the verification after writing are stored. To obtain the checksum value. Then, the checksum value held in the register may be collated with the expected checksum value recorded in the work area 8.

1 is a block diagram schematically showing a flash memory system according to the present invention. It is a figure which shows roughly the structure of the address space of flash memory. It is a figure which shows the example which comprised the zone by the block of 512. FIG. It is a figure which shows the structural example of the zone containing a shared block. It is the figure which showed the example of the address conversion table. It is a conceptual diagram which shows the example of the erased block search table. It is a figure for demonstrating the search method of the erased block using the erased block search table. It is a time chart explaining operation | movement of a writing process.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 15 First adder 16 First register 17 Second adder 18 Second register 25 User area 26 Redundant area

Claims (7)

Writing means for writing data to the flash memory in response to an instruction from a host system that uses the flash memory as a storage medium;
Error collection code generation means for generating an error collection code of data written to the flash memory;
Error collection code writing means for writing the error collection code to the flash memory;
In parallel with the writing means writing data to the flash memory, an expected value calculating means for calculating an expected value of a checksum of data written to the flash memory ;
Reading means for reading data written in the flash memory;
Error correction code reading means for reading the error correction code written in the flash memory;
Correction means for correcting an error included in the data read from the flash memory based on the error collection code read from the flash memory;
After the writing means writes data to the flash memory, the written data is read from the flash memory, and a checksum calculation means for calculating a checksum value of the read data ;
A determination unit that compares the expected value of the checksum calculated by the expected value calculation unit with the checksum value calculated by the checksum calculation unit to determine whether data has been correctly written to the flash memory ; Prepared,
The checksum calculation unit calculates a checksum value of the data in which the error is corrected by the correction unit when an error is included in the data read from the flash memory . The expected value calculation means is composed of an adder by hardware.
The memory controller according to claim 1. The checksum calculation means is composed of an adder by hardware.
The memory controller according to claim 1, wherein the memory controller is a memory controller. The expected value calculation means and the checksum calculation means change the number of bits of the expected value and checksum value to be calculated in response to a request from the host system.
The memory controller according to claim 1, wherein the memory controller is a memory controller. The expected value calculation means and the checksum calculation means set the number of bits of the expected value and checksum value to be calculated to be equal to the bit width of the bus connecting the memory controller and the flash memory.
The memory controller according to claim 1, wherein the memory controller is a memory controller.   A flash memory system comprising: the memory controller according to claim 1; and a flash memory. A writing step of writing data to the flash memory in response to an instruction from a host system using the flash memory as a storage medium;
An error collection code generation step of generating an error collection code of data written to the flash memory;
An error collection code writing step of writing the error collection code into the flash memory;
In parallel with the data that write Murrell to the flash memory by the writing step, an expected value calculation step of calculating an expected value of the checksum of the data to be written to the flash memory,
A reading step of reading write Mareta data from the flash memory writing by said writing step,
An error correction code reading step of reading out the error correction code of the data written by the writing step from the flash memory;
A correction step for correcting an error included in the data read by the reading step based on the error collection code read by the error collection code reading step;
A checksum calculation step of calculating a checksum value of the data read by the reading step ;
The expected value of the checksum calculated by the expected value calculating step, wherein collates the checksum value calculated by the checksum calculating step, and a determination step of determining whether or not data has been written correctly,
When an error is included in the data read by the reading step, the checksum calculation step calculates a checksum value of the data whose error is corrected by the correction step . Control method.

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