CN101026106A - Solder bump lead-free flux preparing process - Google Patents
Solder bump lead-free flux preparing process Download PDFInfo
- Publication number
- CN101026106A CN101026106A CNA2006100241357A CN200610024135A CN101026106A CN 101026106 A CN101026106 A CN 101026106A CN A2006100241357 A CNA2006100241357 A CN A2006100241357A CN 200610024135 A CN200610024135 A CN 200610024135A CN 101026106 A CN101026106 A CN 101026106A
- Authority
- CN
- China
- Prior art keywords
- solder bump
- scaling powder
- manufacture method
- solder
- powder manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
This invention relates to a manufacturing method for salient points of solders without scaling powder including: depositing a dielectric layer on a contacted plate to form a salient point lower metal layer, forming an etching sub and part openings to form a through hole pattern on the plate, filling a solder into the through hole and removing the etching sub, taking the solder salient points as the mask to etch the lower metal layer, removing the oxide layer on the points in a vacuum reaction cavity and reflowing the solder salient points in the cavity, which can provide solder salient points without holes so as to leave out scaling powder and its cleaning devices applied when plating solder salient points on a substrate.
Description
Technical field
The present invention relates to the method for packing in the semiconductor manufacturing, particularly relate to a kind of no scaling powder manufacture method of salient point.
Background technology
Though flip chip technology (fct) has had the history in 30 years, begin volume production and have only several years.The development of substrate technology and material technology exploitation has quickened to adopt senior encapsulation technology.Terminal client requires to continue to increase fast to the encapsulation of more complicated and multi-purpose device.Along with this growth has brought the more complicated and demand greater functionality device package.Senior encapsulation technology the earliest is the application of wafer salient point, and it is that form with salient point or ball is applied to the wafer scale device with welding.The wafer salient point has replaced metal wire and has connected the selection that conduct is used for the interconnection of component count growth.The application of wafer salient point is the driving that needed by performance, form factor or array interconnect.The typical solder bump of electroplating is made flow process as shown in Figure 2, comprises under the salient point metal etch, prefluxing under metal deposit, resist coating and exposure, development, plating, the salient point, refluxes, removes scaling powder etc. again.In this flow process, at first be used for pad 2 that solder bump lands and be defined within on the wafer 1 and with after dielectric layer 4 isolation, the metal level 5 under the salient point forms by equal thick film deposit, shown in Figure 1A.Form photoresist layer 6 then, shown in Figure 1B.Photoetching produces through hole on this pad 2 then, shown in Fig. 1 C.Electrochemical deposition is made the solder bump 7 of plating to the open area, shown in Fig. 1 D.Remove photoresist layer, and be metal level under the mask etching salient point, shown in Fig. 1 E with the solder bump of electroplating.The dystectic titanium oxide nitride layer of one deck is arranged on solder bump,, and seriously hinder scolder, therefore need removal closing on the wetting of connection surface because this titanium oxide nitride layer limits flowing of solder bump.In order to remove the high-melting-point titanium oxide nitride that covers on the solder bump, deposit one deck scaling powder on solder structure refluxes in the boiler tube reflux technique to solder bump then again usually, forms solder ball 71, shown in Fig. 1 F.But the application of scaling powder not only needs extra applying step, extra process apparatus, and needs follow-up cleaning step to remove film of flux residue.Film of flux residue combines with the plumbous gold altogether of tin and also has the danger that influences environment.
The solder bump that this method forms also is easy to generate hole.
Summary of the invention
The objective of the invention is to address the above problem, a kind of manufacture craft that need not traditional scaling powder when making the solder bump of conduction is provided.
A further object of the invention provides does not have the solder ball of hole salient point.
The no scaling powder manufacture method of solder bump of the present invention comprises:
Deposit one deck dielectric layer on contact pad;
Form ubm layer;
Form photoresist layer and part opening to form through-hole pattern on contact pad;
Scolder is packed in the described through hole;
Remove photoresist layer;
With the solder bump is the mask etching ubm layer;
In vacuum reaction chamber, remove the oxide skin(coating) on the salient point;
Reflux solder salient point in vacuum reaction chamber.
According to oxide on the salient point of the present invention is the high-melting-point titanium oxide nitride.
Scolder according to the present invention is eutectic, lead-free solder or high kupper solder.Lead-free solder is as tin-silver solder.
According to the present invention, be to remove oxide with the acid reduction, its step comprises:
Nitrogen feeds the bubbler that acid is housed;
Acid is carried by nitrogen and is entered reaction chamber;
Acid reacts with the oxide that covers on the salient point in reaction chamber.
Wherein, described acid is citric acid, oxalic acid or tartaric acid.Feed nitrogen amount and be at least 5 standard Liter Per Minutes (slm).Better be that nitrogen amount is 5～8 standard Liter Per Minutes (slm).The amount of carrying of described acid is for being less than 5 volume %.The amount of carrying that better is acid is 2～3 volume %.
According to the present invention, remove the vacuum degree of the vacuum reaction chamber of oxide and hold in the palm (mtorr) 10 to 20 persons of outstanding talent.
According to the present invention, remove described oxide with the mist reduction of hydrogen and inert gas, its step comprises:
The mixture of hydrogen and inert gas is fed in the reaction chamber;
Oxide in vacuum reaction chamber on hydrogen and the described salient point carries out reduction reaction.
Wherein, hydrogen content is 5 volume % in the described admixture of gas.The vacuum degree of described vacuum reaction chamber is 10 to 20 person of outstanding talent's holders (mtorr).
According to the present invention, the backflow again of solder bump is carried out in vacuum reaction chamber, and its vacuum degree is 10 to 20 person of outstanding talent's holders (mtorr).
No scaling powder manufacture method of the present invention can provide the solder bump that does not have hole.Method of the present invention is fit to be applied to the making of conductivity solder bump, can be arranged in the solder ball array encapsulation on the Chip Packaging substrate.This method not only adopts the composition that does not have scaling powder fully to form nor with any flux cleaning solvent, and the scaling powder equipment and the cleaning scaling powder equipment of employing usually when having saved the solder bump of plated conductive on substrate.
Description of drawings
Introduce the present invention in detail below in conjunction with accompanying drawing.Yet it should be noted that these accompanying drawings just are used for exemplary embodiments of the present invention is described, and do not constitute any limitation of the invention, under the situation that does not deviate from design of the present invention, can have other how equivalent embodiment.And protection scope of the present invention is determined by claims.
Figure 1A～1F represents the schematic cross-section of forming process of the typical solder bump of prior art.
Fig. 2 represents the schematic diagram of manufacture craft flow process of the typical solder bump of prior art.
Fig. 3 represents the schematic diagram of the helpless flux preparing process flow process of solder bump of the present invention.
Fig. 4 represents the workflow schematic diagram of oxide removal reaction chamber of the present invention.
Fig. 5 represents the workflow schematic diagram in back flow reaction more of the present invention chamber.
Fig. 6 represents the X ray testing result of the atresia solder bump that helpless flux preparing process of the present invention obtains.
Fig. 7 represents the shear mode figure of the observed solder bump of the present invention of microscopically.
Fig. 8 represents the observed shear mode figure with solder bump of hole of microscopically.
Description of reference numerals
1 wafer, 2 pads
3 passivation layers, 4 dielectric layers
Metal 6 photoresists under 5 salient points
61 photoresist patterns, 7 scolders
71 solder balls
Embodiment
No scaling powder manufacture method of the present invention can provide the solder bump that does not have hole.Method of the present invention is fit to be applied to the making of conductivity solder bump, can be arranged in the solder ball array encapsulation on the Chip Packaging substrate.This method not only adopts the composition that does not have scaling powder fully to form nor with any flux cleaning solvent, the scaling powder equipment and the cleaning scaling powder equipment of employing usually when therefore having saved the solder bump of plated conductive on substrate.
No scaling powder manufacturing process of the present invention comprises two reaction chambers, and oxide removal reaction chamber and back flow reaction chamber again are applicable to the application of all solder bumps, as eutectic (63 tin, 37 lead), unleaded, high lead and ultralow alpha solder bump.
In one embodiment of the invention, do not have the making of scaling powder salient point according to flow process as shown in Figure 3, and the forming process of solder bump of the present invention also can be with reference to Figure 1A～1F.At first shown in Figure 1A, on the chip 1 that is formed with aluminium contact pad 2, passivation layer 3, dielectric layer 4, electroplate and form metal 5 under the salient point, as tin lead; Shown in Figure 1B, form photoresist layer 6 then, and the part opening is to form through-hole pattern on contact pad 2, shown in Fig. 1 C; As described in deposit one scolder 7 (as leypewter) is filled in the through hole, shown in Fig. 1 D; Remove photoresist 61, and be that mask etching falls metal 5 under the salient point, shown in Fig. 1 E with this solder bump 7;
Wherein, on solder bump 7, because the plumbous oxide layer of tin is coated with titanium oxide nitride layer, it stops flowing of scolder, need get rid of.
Shown in Figure 4 is the schematic block diagram of the oxide removal reaction chamber of one embodiment of the present of invention.Wherein, comprising: vacuum reaction chamber, its inside are provided with gas distribution plate, the preposition line of vacuum (vacuumforeline) (being used to vacuumize), gas control board and sour bubbler (not shown).
In one embodiment, at least 5 standard Liter Per Minutes (slm), the nitrogen that is preferably 5～8 standard Liter Per Minutes (slm) transmits by the citric acid bubbler, carry the citric acid, oxalic acid or the tartaric acid that are less than 5% (2～3%) approximately, be preferably and use citric acid, mix with nitrogen (more than 2slm) then, enter reaction chamber.Wherein the reduction process of oxide is:
MeO+CxHxO(COOH)x→Me(COOH)+H
2O
Me(COOH)→Me+CO
2+H
2
MeO in the formula is a metal oxide.After metal oxide reduction processing procedure, with wafer handling in the chamber of back flow reaction more as shown in Figure 5.
In another embodiment, the oxide removal processing procedure can also be in conjunction with hydrogen (5%) and helium.With gas distribution plate gas is evenly distributed on the wafer with the even perforate of 1mm.This processing procedure is to carry out under the vacuum environment of 10 to 20 person of outstanding talent's holders (mtorr).Wherein the reduction process of oxide is:
MeO+H
2→Me+H
2O
MeO in the formula is a metal oxide.After metal oxide reduction processing procedure, with wafer handling in the chamber of back flow reaction more as shown in Figure 5.
Fig. 5 is the schematic block diagram in the chamber of back flow reaction again of one embodiment of the present of invention.Wherein, comprising: vacuum reaction chamber, wherein be provided with heating station, forvacuum line (vacuum foreline), and the gas control board.
In the reflux course again of an embodiment, the nitrogen of 5～10slm is sent in the back flow reaction chamber again, its heating-up temperature basis reflux temperature is again set, and promptly the reflux temperature of lead-free solder is at 200～260 ℃, and the eutectic solder reflow temperature is at 150～200 ℃.The whole processing procedure that refluxes again carries out under the vacuum environment of 20mtorr at 10mtorr, and this process can effectively be removed the bubble in the scolder, can guarantee imperforate product.
Fig. 6 is applying X-ray carries out the hole monitoring to solder bump of the present invention result.As can be seen, as seen the smooth surface zero defect of solder bump illustrates that bubble is driven out of in above-mentioned reflux course again from scolder.
Reliability data (high-temperature storage 168 hours) shows that also eutectic and lead-free solder salient point all meet the demands, and these data are equal to the data of using the typical solders processing procedure.Unleaded and eutectiferous shearing force specification all is greater than 35.4 gram/salient points; And lead-free solder and the eutectic scolder shearing force specification after reliability testing is 37.4 gram/salient points and 43.6 gram/salient points.
The present invention also provides a kind of light, oxide-free solder bump, and does not need with scaling powder and removal scaling powder process.
Fig. 7 is applied to the salient point outside drawing that the eutectic salient point obtains with no scaling powder processing procedure, and this eutectiferous composition is measured by Thermal Noran XRF, tin Sn (63 ±-5) as a result, plumbous Pb (37 ±-5).
Fig. 8 is the solder bump outside drawing with hole.The composition of its mensuration is that (Sn:63.5%, Pb:36.5%), the shearing force specification is 32.5 gram/salient points.
The present invention is without scaling powder and remove the scaling powder fabrication steps, can greatly reduce running cost (comprising indirect material, the chemicals cost), can reduce cost at least 80% for eutectic, high lead and lead-free solder.Application for ultralow alpha solder bump can reduce by 30% approximately.And the whole cycle will be reduced at least 150% (for the later fabrication steps of metal etch under the salient point, can reduce 20WPH to 50WPH).Because do not have chemical waste without the chemical solvent of scaling powder and removal scaling powder, therefore this no scaling powder method for making solder bump also provides eco-friendly processing procedure.
Though the above is at embodiments of the invention, other and further embodiment of the present invention can design not deviating under its base region, and its protection range is the scope decision by claims.
Claims (15)
1. the no scaling powder manufacture method of a solder bump comprises:
Deposit one deck dielectric layer on contact pad;
Form ubm layer;
Form photoresist layer and part opening to form through-hole pattern on contact pad;
Scolder is packed in the described through hole;
Remove photoresist layer;
With the solder bump is the mask etching ubm layer;
In vacuum reaction chamber, remove the oxide skin(coating) on the salient point;
Reflux solder salient point in vacuum reaction chamber.
2. the no scaling powder manufacture method of solder bump according to claim 1 is characterized in that, oxide is the high-melting-point titanium oxide nitride on the described salient point.
3. the no scaling powder manufacture method of solder bump according to claim 1 is characterized in that, described scolder is eutectic, lead-free solder, high kupper solder.
4. the no scaling powder manufacture method of solder bump according to claim 3 is characterized in that described lead-free solder is a tin-silver solder.
5. the no scaling powder manufacture method of solder bump according to claim 1 is characterized in that, described removal oxide is that its step comprises with the acid reduction:
Nitrogen feeds the bubbler that acid is housed;
Acid is carried by nitrogen and is entered reaction chamber;
Acid reacts with the oxide that covers on the salient point in reaction chamber.
6. the no scaling powder manufacture method of solder bump according to claim 5 is characterized in that, described acid is citric acid, oxalic acid, tartaric acid.
7. the no scaling powder manufacture method of solder bump according to claim 5 is characterized in that, described nitrogen feeding amount is at least 5 standard Liter Per Minutes (slm).
8. the no scaling powder manufacture method of solder bump according to claim 5 is characterized in that, described nitrogen feeding amount is 5～8 standard Liter Per Minutes (slm).
9. the no scaling powder manufacture method of solder bump according to claim 5 is characterized in that, the amount of carrying of described acid is for being less than 5 volume %.
10. the no scaling powder manufacture method of solder bump according to claim 5 is characterized in that, the amount of carrying of described acid is 2～3 volume %.
11. the no scaling powder manufacture method of solder bump is characterized in that according to claim 1 or 5, the vacuum degree of removing the oxide vacuum reaction chamber is in 10 to 20 person of outstanding talent's holders (mtorr).
12. the no scaling powder manufacture method of solder bump according to claim 1 is characterized in that, removes described oxide with the mist reduction of hydrogen and inert gas, its step comprises:
The mixture of hydrogen and inert gas is fed in the reaction chamber;
Oxide in vacuum reaction chamber on hydrogen and the described salient point carries out reduction reaction.
13. the no scaling powder manufacture method of solder bump according to claim 12 is characterized in that, hydrogen content is 5 volume % in the described admixture of gas.
14. the no scaling powder manufacture method according to claim 1 or 12 described solder bumps is characterized in that, the vacuum degree of removing the oxide vacuum reaction chamber is 10 to 20 person of outstanding talent's holders (mtorr).
15. the no scaling powder manufacture method of solder bump according to claim 1 is characterized in that, the vacuum degree in described back flow reaction again chamber is 10 to 20 person of outstanding talent's holders (mtorr).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100241357A CN100452335C (en) | 2006-02-24 | 2006-02-24 | Solder bump lead-free flux preparing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100241357A CN100452335C (en) | 2006-02-24 | 2006-02-24 | Solder bump lead-free flux preparing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101026106A true CN101026106A (en) | 2007-08-29 |
| CN100452335C CN100452335C (en) | 2009-01-14 |
Family
ID=38744232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100241357A Expired - Fee Related CN100452335C (en) | 2006-02-24 | 2006-02-24 | Solder bump lead-free flux preparing process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100452335C (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728347B (en) * | 2008-10-22 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Package structure and manufacture method thereof |
| CN101621044B (en) * | 2008-07-04 | 2011-06-01 | 中芯国际集成电路制造(上海)有限公司 | Chip lug structure and manufacturing method thereof |
| CN102528194A (en) * | 2010-12-15 | 2012-07-04 | 无锡华测电子系统有限公司 | Vacuum eutectic welding method |
| CN102881604A (en) * | 2011-07-12 | 2013-01-16 | 格罗方德半导体公司 | Solder bump cleaning before reflow |
| CN104485293A (en) * | 2014-12-12 | 2015-04-01 | 南通富士通微电子股份有限公司 | Method for increasing balling rate of metal convex block in vacuum backflow technology |
| CN111690962A (en) * | 2020-03-02 | 2020-09-22 | 浙江铖昌科技有限公司 | Method for manufacturing large solder ball based on electroplating process |
| CN114433971A (en) * | 2021-12-20 | 2022-05-06 | 中国电子科技集团公司第二十九研究所 | Device and method for stack welding with assistance of magnetic vibration particles |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3397313B2 (en) * | 1999-12-20 | 2003-04-14 | 富士通株式会社 | Semiconductor device manufacturing method and electronic component mounting method |
| CN1355555A (en) * | 2000-11-28 | 2002-06-26 | 中国科学院微电子中心 | Method for generating convex welding points on semiconductor chip |
| US7134199B2 (en) * | 2002-06-13 | 2006-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fluxless bumping process |
-
2006
- 2006-02-24 CN CNB2006100241357A patent/CN100452335C/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101621044B (en) * | 2008-07-04 | 2011-06-01 | 中芯国际集成电路制造(上海)有限公司 | Chip lug structure and manufacturing method thereof |
| CN101728347B (en) * | 2008-10-22 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Package structure and manufacture method thereof |
| CN102528194A (en) * | 2010-12-15 | 2012-07-04 | 无锡华测电子系统有限公司 | Vacuum eutectic welding method |
| CN102881604A (en) * | 2011-07-12 | 2013-01-16 | 格罗方德半导体公司 | Solder bump cleaning before reflow |
| CN102881604B (en) * | 2011-07-12 | 2015-12-02 | 格罗方德半导体公司 | The method of solder projection is cleaned before reflow |
| US9773744B2 (en) | 2011-07-12 | 2017-09-26 | Globalfoundries Inc. | Solder bump cleaning before reflow |
| CN104485293A (en) * | 2014-12-12 | 2015-04-01 | 南通富士通微电子股份有限公司 | Method for increasing balling rate of metal convex block in vacuum backflow technology |
| CN104485293B (en) * | 2014-12-12 | 2017-08-11 | 通富微电子股份有限公司 | A kind of method of balling ratio of the raising metal coupling in vacuum back-flow technique |
| CN111690962A (en) * | 2020-03-02 | 2020-09-22 | 浙江铖昌科技有限公司 | Method for manufacturing large solder ball based on electroplating process |
| CN114433971A (en) * | 2021-12-20 | 2022-05-06 | 中国电子科技集团公司第二十九研究所 | Device and method for stack welding with assistance of magnetic vibration particles |
| CN114433971B (en) * | 2021-12-20 | 2023-07-25 | 中国电子科技集团公司第二十九研究所 | Method for carrying out stacking welding with assistance of magnetic vibration particles |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100452335C (en) | 2009-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100339190B1 (en) | Barrier layers for electroplated snpb eutectic solder joints | |
| CN100452335C (en) | Solder bump lead-free flux preparing process | |
| US6750133B2 (en) | Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps | |
| CN102157473B (en) | Semiconductor device and manufacturing method thereof | |
| KR100545008B1 (en) | Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same | |
| US9263412B2 (en) | Packaging methods and packaged semiconductor devices | |
| JP4704679B2 (en) | Under bump metal of semiconductor element | |
| JP5808403B2 (en) | Method for forming a solder deposit on a substrate | |
| US9824991B2 (en) | Organic thin film passivation of metal interconnections | |
| Koh et al. | Copper pillar bump technology progress overview | |
| TWI478255B (en) | Solder bump cleaning before reflow | |
| KR20110002816A (en) | Method and structure for adhesion of intermetallic compound (imc) on cu pillar bump | |
| JP2010109032A (en) | Method of manufacturing semiconductor device | |
| US11728180B2 (en) | Chip package structure with conductive adhesive layer | |
| TW201314805A (en) | Solder cap bump in semiconductor package and method of manufacturing the same | |
| Lau et al. | Hybrid substrate with ultra-large organic interposer for heterogeneous integration | |
| US6417088B1 (en) | Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding | |
| JP5277788B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP6702108B2 (en) | Terminal structure, semiconductor device, electronic device, and method for forming terminal | |
| US8377816B2 (en) | Method of forming electrical connections | |
| TWI549246B (en) | Thin nib or cob capping layer for non-noble metallic bonding landing pads | |
| US20070045833A1 (en) | Copper bump barrier cap to reduce electrical resistance | |
| TWM589366U (en) | Chip package assembly with enhanced interconnects | |
| JP2009164524A (en) | Method for forming electrode | |
| CN117438407A (en) | Flip-chip bonding structure convenient to weld and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111205 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111205 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090114 Termination date: 20190224 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |