CN1355555A - Method for generating convex welding points on semiconductor chip - Google Patents
Method for generating convex welding points on semiconductor chip Download PDFInfo
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- CN1355555A CN1355555A CN00133603A CN00133603A CN1355555A CN 1355555 A CN1355555 A CN 1355555A CN 00133603 A CN00133603 A CN 00133603A CN 00133603 A CN00133603 A CN 00133603A CN 1355555 A CN1355555 A CN 1355555A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1183—Reworking, e.g. shaping
- H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
A process for preparing convex solder point on semiconductor chip includes such steps as preparing metallized layer under ball, depositing and etching medium film, electroplating copper micro-convex points, using the formulation of bright sulphate plating liquid for copper-blating to a thickness of 5-10 microns, and then convex Pb-Sn alloy points and reflux at the temp 10-50 deg.C higher than the smelting point of solder and with neutral flux.
Description
The invention belongs to technology of semiconductor chips field, be meant a kind of method for generating convex welding points on semiconductor chip especially.
Along with developing rapidly of semiconductor integrated circuit (IC), promote the corresponding development of encapsulation technology, flip chip bonding technology is a kind of novel advanced person's packing forms in the semiconductor device packaging technique field just.So-called flip chip bonding technology is to adopt various connection materials and method, and chip front side (significant surface or I/O face) is installed together towards substrate.Compare with traditional packaged type, its advantage is: necessary lead-in wire is the shortest; Inductance is low; The frequency height; Best noise control; Maximum I/O density; Minimum overall dimension etc.And the process technology of salient point is the major technique link in the flip chip bonding technology.The early 1990s, salient point process technology and relevant proprietary material and equipment are used widely.
The present situation of method for generating convex welding points is quoted as proof with relevant:
External convex point material of being used widely comprises: gold and alloy such as Au/Sn, Au/In etc.; Indium; Scolder.Wherein terne metal (lead base or lead-free alloy) adopts electroplating technology, but makes it to be easy to processing, the low large-scale production of cost, thereby is used widely.The scolder that 60Sn/40Pb in the terne metal (or 63Sn/37Pb) forms is that typical low temperature melts system altogether, and eutectic point is 183 ℃, has low yield strength and high ductibility energy.Be a kind of typical bullet moulding material, thereby improved the reliability of the device of falling soldering and sealing.
The plating of solder bump: in prior art, be coated with thick glue before the plating, carve hole (deep-well) at the I/O terminal position then, make bottom metallization layer (UBM) exposed, require wall steep, the remnants of glue must not be arranged at the bottom.Electroplate then, fill scolder in the hole; Remove photoresist after the plating, through reflux technique and the glomeration salient point.Need special-purpose photoresist, automatic double surface gluer and thick glue etching technics for this reason.And our method is not coated with thick glue, replaces thick glue with thin dielectric film, and carves the hole, and Direct Electroplating becomes the blank salient point, is salient point through the reflux technique balling-up again; Simultaneously, do reasonable adjustment, solve I/O fenestra charge concentration and cause the dusting of point discharge coating very to cause the problem of burning for the relevant additive level of electroplating technology, current density etc.Thereby realize to electroplate the back and form blank solder bump, in the reflux course behind the solder fusing, by self surface tension effects pull-up lower curtate scolder and glomeration (hemisphere or big hemisphere) salient point with certain altitude.All need in view of being coated with required proprietary material of thick glue and equipment in the prior art, and thick glue etching technics technical difficulty is big from external introduction.
The object of the present invention is to provide a kind of method for generating convex welding points on semiconductor chip, it can simplify technology, reduces investment.
A kind of method for generating convex welding points on semiconductor chip of the present invention comprises the steps:
Step 1: metal layer under the ball;
Step 2: the deposit of deielectric-coating and etching;
Step 3: electroplating technology: a, the miniature salient point of electro-coppering or claim thick copper: adopt bright sulfuric acid salt electroplate liquid formulation, copper facing thickness 5-10 μ m; B, electroplating lead tin alloy salient point: adopt bright terne metal electroplating formula and material, the binary system terne metal is once electroplated and is finished;
Step 4: reflux technique: adopt the backflow peak temperature to be higher than 10-50 ℃ of scolder fusing point, and adopt neutral scaling powder.
Metal layer under the ball of step 1 wherein, titanium is an adhesion layer, and tungsten is separator, and gold is for electroplating basal layer; Titanium thickness 1000-2000 , titanium tungsten gross thickness 3000～5000 , golden thickness 800-1000 adopt sputtering technology.
Metal layer under the ball of step 1 wherein adopts under the ball sputtered titanium on the aluminum pad: metal layer under tungsten-gold formation ball.
B electroplating lead tin alloy technology in the step 3 wherein, measure is:
A interconnection line design: under the certain prerequisite of metallization layer thickness, widen the interconnection line width, improve uniformity of current density so that reduce resistance; Main line is 50-60 μ m, and branch line is 15-30 μ m.
The design of B hanger: the design of hanger will increase chip surface current input terminal; Except that being provided with the input terminal around chip, chip center's point is provided with this terminal simultaneously; Thereby improve the consistency of bump height.
The graphical back copper facing of metal layer under the C ball: because the increase of chip size, under the ball metal layer graphical after, copper facing 3-5 μ m again.
For further specifying technology contents of the present invention, below in conjunction with embodiment the present invention is made a detailed description, wherein:
Fig. 1 is a process chart of the present invention;
Fig. 2 adopts interconnect technology solder bump microphoto;
Fig. 3 is the miniature salient point photo of copper;
Fig. 4 is the solder bump photo;
Fig. 5 is the distribution of salient point brightness along 4 cun chip diameters.
At first see also shown in Figure 1ly, a kind of method for generating convex welding points on semiconductor chip of the present invention comprises the steps:
Step 1: metal layer under the ball: titanium is adhesion layer, and tungsten is separation layer, and gold is for electroplating the basis Layer; Titanium thickness 1000-2000 , titanium tungsten gross thickness 3000～5000 , Gold thickness 800-1000 adopts sputtering technology.
Step 2: the deposit of deielectric-coating and etching: it is deielectric-coating that this method adopts silicon nitride, thickness Be 3000-5000 , adopt plasma chemical deposition (PECVD) method; Window Etching adopt wet method, to avoid dry method to having stored the infringement of information in the chip.
Step 3: electroplating technology: a, the miniature salient point of electro-coppering or claim thick copper: adopt bright sulfuric acid The salt electroplate liquid formulation, copper facing thickness 5-10 μ m; B, electroplating lead tin alloy salient point: adopt environmental protection Type light terne metal electroplating formula and material, the coating densification, alloying component is stable, does not have obviously Environmental pollution; And the binary system terne metal is once electroplated and is finished;
Step 4: reflux technique: adopt the backflow peak temperature to be higher than 10-50 ℃ of scolder fusing point, And adopt neutral scaling powder.
Metal layer under the ball of step 1 wherein adopts under the ball sputtered titanium on the aluminum pad: tungsten-golden shape Metal layer under the balling-up (UBM), its interface is in conjunction with good, and contact resistance is low, the shear strength height; After the balling-up, shear strength is higher than the standard of 24.3 gram forces in the standard.
B electroplating lead tin alloy technology in the step 3 wherein is the uniformity that guarantees bump height, and this method is in the design of the design of interconnection line, hanger, and measure is:
The design of A interconnection line: under the certain prerequisite of metallization layer thickness, widen the interconnection line width, Improve uniformity of current density in order to reduce resistance; Main line is 50-60 μ m, and branch line is 15-30 μ m.
The design of B hanger: because electroplating device is domestic coating bath, the design of hanger will increase chip The surface current input terminal; Except arranging the input terminal around chip, chip center's point is established simultaneously Put this terminal; Thereby improve the uniformity (Fig. 5) of bump height.
After C UBM metal layer is graphical, copper facing; Since the increase of chip size, above-mentioned two The measure of aspect still has some deficits, for this reason behind the UBM metal layer, and copper facing 3-5 μ m again, from And the resistance of reduction interconnection line, the uniformity of raising bump height; Particularly distribute again for salient point, The increase of interconnect length must copper facing on the UBM interconnection line, increases interconnection line thickness, reduces Resistance;
The setting of fictitious load and the adjustment of additive:
In view of the reasons such as detection of electroplating power supply ripple factor, adjustment precision and current density, electricity During plating fictitious load should be set, thereby improve electric current output, reduce ripple factor, be easy to adjust and electricity The detection of current density;
What adopt in plating this method of terne metal is bright coating, and its additive has significantly whole Flat effect, and plating blank salient point requires to increase height as far as possible, is beneficial to the backflow balling-up; Spend liquid for this reason Middle main brightener standard is 30ml/L, is reduced to 15-20ml/L, has both guaranteed suitable light Pool property can make again the blank salient point increase height, improves good balling ratio.
Therefore, this method can meet the needs of production, and has the value of applying again.
The feasible way of this method processing solder bump: this method comprises the plating of adhesion layer, separator, plating basal layer, miniature copper bump and solder bump and backflow etc.Difference is not to be coated with thick glue, and 60Sn/40Pb binary system alloy is once electroplated.
The good effect of this method:
1, avoids expensive from external introduction proprietary material and equipment;
2, avoid thick glue etching technics, this technology is strict relatively, technical difficulty is big and the etching technics of film (thickness is less than 1 μ m) is ripe.
3, environment-friendly type electroplate liquid BR-31N type prescription is adopted in the plating of binary system terne metal, this method, once finishes the plating of blank salient point, and non-environmental-pollution is simplified technology, and bath stability is easy to control.
4, the plating bath composition simply is easy to analyze and adjusts, and solder compositions is stable, is suitable for large-scale production.
The best way that this method realizes:
1, UBM metal layer: metal layer comprises adhesion layer, separator and plating basal layer below the ball, and promptly Ti:W-Au adopts sputtering technology, and the Ti:W gross thickness is 3000-5000 , and Au thickness is 800-1000 .
2, the UBM metal layer is graphical: finish the graphical of UBM metal layer before the plating earlier, promptly between power input and pad (I/O terminal), form interconnection line, both can improve the uniformity of electroplating process current density, in the time of can avoiding electrodeposited coating etching UBM metal layer again to the corrosion of scolder.Method photoetching process (Fig. 2) is peeled off in employing.
3, the deposition of inorganic dielectric film and etching: UBM wants deposit one deck dielectric film after graphical, can be inoranic membrane or organic membrane.Inoranic membrane is generally silicon dioxide or silicon nitride, and this method adopts PECVD method deposit silicon nitride, thickness 3000-5000 ; And the etching of deielectric-coating can adopt wet method or dry method, and this method adopts wet etching.
4, electroplate:
4.1 the miniature salient point of electro-coppering (or claiming thick copper Fig. 3).This method adopts bright sulfuric acid salt electrolytic copper plating technology, its main technique standard: cathode-current density 2-4A/dm2, temperature 15-25 ℃.
4.2 electroplating lead tin alloy salient point: this method adopts environment-friendly type electroplate liquid formulation and material, bright terne coating, its main technique standard: cathode-current density 2-3A/dm2; Temperature 18-25 ℃; For guaranteeing the height of blank salient point, the reply content of additive is done suitable adjustment.
5, reflux technique (Fig. 4): this technology can adopt box type furnace, tube furnace or chain-conveyer furnace, and the backflow peak temperature is higher than 10-50 ℃ of scolder fusing point.This method reflux technique adopts neutral scaling powder, and scaling powder remnants are removed with organic solvent in the back of refluxing.
And this method is electroplated technical maturity after adopting film to carve the hole; The solder bump of this method processing simultaneously can satisfy the requirement of solder bump range of application again.
Claims (4)
1, a kind of method for generating convex welding points on semiconductor chip is characterized in that,
Comprise the steps:
Step 1: metal layer under the ball;
Step 2: the deposit of deielectric-coating and etching;
Step 3: electroplating technology: a, the miniature salient point of electro-coppering or claim thick copper: adopt bright sulfuric acid salt electroplate liquid formulation, copper facing thickness 5-10 μ m; B, electroplating lead tin alloy salient point: adopt bright terne metal electroplating formula and material, the binary system terne metal is once electroplated and is finished;
Step 4: reflux technique: adopt the backflow peak temperature to be higher than 10-50 ℃ of scolder fusing point, and adopt neutral scaling powder.
2, method for generating convex welding points on semiconductor chip according to claim 1 is characterized in that, metal layer under the ball of step 1 wherein, and titanium is an adhesion layer, and tungsten is separator, and gold is for electroplating basal layer; Titanium thickness 1000-2000 , titanium tungsten gross thickness 3000～5000 , golden thickness 800-1000 adopt sputtering technology.
3, method for generating convex welding points on semiconductor chip according to claim 1 is characterized in that, metal layer under the ball of step 1 wherein adopts under the ball sputtered titanium on the aluminum pad: metal layer under tungsten-gold formation ball.
4, method for generating convex welding points on semiconductor chip according to claim 1 is characterized in that, b electroplating lead tin alloy technology in the step 3 wherein, and measure is:
A interconnection line design: under the certain prerequisite of metallization layer thickness, widen the interconnection line width, improve uniformity of current density so that reduce resistance; Main line is 50-60 μ m, and branch line is 15-30 μ m;
The design of B hanger: the design of hanger will increase chip surface current input terminal; Except that being provided with the input terminal around chip, chip center's point is provided with this terminal simultaneously; Thereby improve the consistency of bump height;
The graphical back copper facing of metal layer under the C ball: because the increase of chip size, under the ball metal layer graphical after, copper facing 3-5 μ m again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN00133603A CN1355555A (en) | 2000-11-28 | 2000-11-28 | Method for generating convex welding points on semiconductor chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN00133603A CN1355555A (en) | 2000-11-28 | 2000-11-28 | Method for generating convex welding points on semiconductor chip |
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| CN1355555A true CN1355555A (en) | 2002-06-26 |
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| CN00133603A Pending CN1355555A (en) | 2000-11-28 | 2000-11-28 | Method for generating convex welding points on semiconductor chip |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420007C (en) * | 2006-02-06 | 2008-09-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor end-electrode structure and its making method |
| CN100452335C (en) * | 2006-02-24 | 2009-01-14 | 中芯国际集成电路制造(上海)有限公司 | Solder bump lead-free flux preparing process |
| CN1933106B (en) * | 2005-09-12 | 2010-04-28 | 中芯国际集成电路制造(上海)有限公司 | Method for producing golden convex points with more smooth surface |
| CN102184875A (en) * | 2011-04-05 | 2011-09-14 | 山东理工大学 | Manufacturing method of nail head gold bump |
| CN102194719A (en) * | 2010-03-15 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Method for improving welding spot characteristics in packaging process |
| CN102522347A (en) * | 2011-12-23 | 2012-06-27 | 清华大学 | Method for manufacturing solder bump |
| CN101740422B (en) * | 2008-11-17 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Method for fabricating bump |
-
2000
- 2000-11-28 CN CN00133603A patent/CN1355555A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1933106B (en) * | 2005-09-12 | 2010-04-28 | 中芯国际集成电路制造(上海)有限公司 | Method for producing golden convex points with more smooth surface |
| CN100420007C (en) * | 2006-02-06 | 2008-09-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor end-electrode structure and its making method |
| CN100452335C (en) * | 2006-02-24 | 2009-01-14 | 中芯国际集成电路制造(上海)有限公司 | Solder bump lead-free flux preparing process |
| CN101740422B (en) * | 2008-11-17 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Method for fabricating bump |
| CN102194719A (en) * | 2010-03-15 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Method for improving welding spot characteristics in packaging process |
| CN102184875A (en) * | 2011-04-05 | 2011-09-14 | 山东理工大学 | Manufacturing method of nail head gold bump |
| CN102522347A (en) * | 2011-12-23 | 2012-06-27 | 清华大学 | Method for manufacturing solder bump |
| CN102522347B (en) * | 2011-12-23 | 2015-04-29 | 清华大学 | Method for manufacturing solder bump |
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