CN100561697C - Method for making tin solder bump - Google Patents

Method for making tin solder bump Download PDF

Info

Publication number
CN100561697C
CN100561697C CNB2006101477884A CN200610147788A CN100561697C CN 100561697 C CN100561697 C CN 100561697C CN B2006101477884 A CNB2006101477884 A CN B2006101477884A CN 200610147788 A CN200610147788 A CN 200610147788A CN 100561697 C CN100561697 C CN 100561697C
Authority
CN
China
Prior art keywords
bump
layer
dry film
method
photoresist
Prior art date
Application number
CNB2006101477884A
Other languages
Chinese (zh)
Other versions
CN101207047A (en
Inventor
何智清
孙支柱
王重阳
章剑名
蒋瑞华
杰 陈
陈圣琰
Original Assignee
中芯国际集成电路制造(上海)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中芯国际集成电路制造(上海)有限公司 filed Critical 中芯国际集成电路制造(上海)有限公司
Priority to CNB2006101477884A priority Critical patent/CN100561697C/en
Publication of CN101207047A publication Critical patent/CN101207047A/en
Application granted granted Critical
Publication of CN100561697C publication Critical patent/CN100561697C/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

一种能够控制底切的凸点的制作方法,包括:在已经形成有焊盘的晶片上形成凸点下金属层;形成干膜光刻胶层;曝光、显影形成光刻胶的凸点开口图案;在开口中电镀铜层和镍层,再在开口中填充凸点材料;去除光刻胶;以凸点为掩模刻蚀凸点下金属;高温回流。 Controlling method capable of making undercut bumps, comprising: an under bump metal layer is formed on the wafer has been formed pad; dry film photoresist layer; exposing and developing the resist opening forming bumps pattern; electroplated copper layer in the openings and the nickel layer, then filling in the openings bump material; removing the photoresist; a lower metal bump to bump etching mask; to reflux temperature. 该方法可以用于12″晶片,提高凸点下金属刻蚀的制程容许度,以及更容易控制凸点的底切,而且所得到的凸点更坚固。 This method can be used for 12 "wafer, improve the tolerance of the metal etch process of the bump, and the undercut is easier to control the bump, the bump and the resulting stronger.

Description

一种焊料凸点的制作方法 A solder bump fabrication method

技术领域 FIELD

本发明涉及半导体制造过程中焊料凸点的制作方法,特别是涉及可以控制底切的焊料凸点的制作方法。 The present invention relates to a method for manufacturing a semiconductor manufacturing process the solder bump, particularly to a manufacturing method to control undercut the solder bumps.

背景技术 Background technique

尽管倒装焊技术己经存在30年了,但近几年才开始得到量产。 Although flip-chip technology has existed for 30 years, but in recent years began to be mass production. 衬底技术和材料技术开发的发展加速了釆用高级封装技术。 Substrate technology development and accelerate the technology development of materials preclude the use of advanced packaging technology. 随着终端客户对更复杂和更多功能的器件的封装要求的继续快速增长,带来了对更复杂和更多功能器件封装的需求。 With the end-user packaging requirements to continue to grow rapidly more complex and more functional devices has created a need for more complex and more functional device package. 最早的高级封装技术是晶片凸点的应用,其是以凸点或球的形式将焊料应用于晶片级器件。 The first wafer is advanced packaging applications bump, which is in the form of bumps or solder balls is applied to the wafer-level device.

晶片凸点取代了金属线连接作为用于组件数量增长的互连的选择。 Wafer bumping substituents selected line is connected as an interconnect metal for growth of the number of components. 晶片凸点的应用是受性能、波形因数或阵列互连需要的驱动。 Wafer bumping is subject to the application of the driving performance, or crest factor array interconnecting desired. 在典型的电镀焊料凸点工艺流程中。 In a typical process flow electroplated solder. 包括凸点下金属淀积、涂光刻胶和曝光、显影、电镀、凸点下金属刻蚀、涂助焊剂、再回流、去除助焊剂等。 Including under bump metal deposition, resist coating and exposure, development, plating, etching the under-bump metal, fluxing, was refluxed to remove flux and the like. 在该流程中, 所用光刻胶是液体光刻胶。 In this process, the photoresist used is a liquid photoresist. 在光刻胶形成的开口区域制作电镀焊料凸点。 An open region formed in the photoresist making electroplated solder. 光刻胶层可以去除,以及凸点下金属层可以以电镀焊料凸点为掩模进行刻蚀。 The photoresist layer may be removed, and the under bump metal layer may be electroplated solder bumps as an etching mask. 因为在12"晶片的应用中普遍采用铜和钛作为凸点下金属层,因此底切的控制总是成为大的问题。在各向同性刻蚀中,底切(undercut)是影响剪切试验结果的主要问题。这是由于溅射淀积的铜层的密度大于电镀铜层的密度,因此位于双层结构铜层上面的电镀铜层容易过度刻蚀,在焊料凸点下面的镍(Ni)隔离层下形成向内凹进的切口。由此对焊料凸点的剪切力测试结果造成负面影响。使焊料凸点和半导体器件的可靠性下降。 Since the 12 "wafer application of copper and titanium commonly used as the under-bump metal layers, thus undercutting the control is always a significant problem. In the isotropic etching, an undercut (undercut) impact shear test the main problem of the results. this is because the density of the sputter deposited copper layer is greater than the density of the electroplated copper layer, a copper layer is therefore located above the two-layer structure of a copper plating layer is readily etched excessively, the solder bump in the following nickel (Ni ) lower spacer layer is formed a cut recessed inwardly, thereby adversely affecting the results of shear test solder bump. solder bumps of the semiconductor device and reduction in reliability.

在焊料凸点上有一层高熔点的氮化钛氧化物层,因为该氮化钛氧化物层限制焊料凸点的流动,而且严重阻碍焊料对临近连接表面的润湿,因此需要去除。 A layer of high-melting titanium nitride oxide layer on the solder bump, since the oxide layer is a titanium nitride restrict the flow of solder bump, and a serious impediment to the adjacent solder wets the surface of the connector, and therefore needs to be removed. 为了去除覆盖在焊料凸点上的高熔点氮化钛氧化物,通常在悍料结构上淀积一层助焊剂,然后对焊料凸点在炉管回流工艺中进行再回流,形成焊料球。 In order to remove the solder bump overlying the refractory oxide of titanium nitride, it is usually deposited on a layer of structure material defended flux, the solder bumps and then re refluxed tubes reflow process, solder balls are formed.

在焊料结构上为了破坏高熔点氮化钛氧化物覆盖该焊料结构而沉积 On the solder structure in order to break the high-melting oxide coating of titanium nitride deposited solder structure

助焊剂,然后焊料凸点在炉内进行回流工艺。 Flux and solder bump reflow process is performed in a furnace. 该层限制焊料流动以及阻止润湿要结合的邻近表面。 The solder limiting layer adjacent the surface wettability and preventing the flow to be bonded.

发明内容 SUMMARY

本发明所要解决的技术问题是提供一种可以控制底切的焊料凸点的制作方法。 The present invention solves the technical problem is to provide a manufacturing method of controlling undercut the solder bumps.

本发明的焊料凸点的制作方法,包括如下步骤: Solder bump fabrication method of the present invention, comprising the steps of:

在已经形成有焊盘的晶片上溅射形成凸点下金属层; Has been formed on the wafer pad is formed by sputtering under bump metal layer;

形成干膜光刻胶层; Forming a dry film photoresist layer;

曝光、显影形成光刻胶的凸点开口图案; 在开口中电镀铜层和镍层; Exposure, developed to form a photoresist bump opening pattern; opening electroplated copper layer and nickel layer;

在开口中填充凸点材料; 去除光刻胶; Filling the opening bump material; removing the photoresist;

以焊料凸点为掩模刻蚀凸点下金属层; In the solder bumps as an etching mask under bump metal layer;

淀积助焊剂; Flux deposition;

高温回流。 High-temperature reflow.

根据本发明的焊料凸点的制作方法优选用于12"的晶片。 根据本发明的凸点下金属层为铜或钛。 For the 12 "wafer manufacturing method according to the present invention, the solder bump is preferred. According to the present invention, an under bump metal layer is copper or titanium.

本发明的干膜光刻胶,优选是AsahiCX-A240 、 TOK Ordyl P-50120。 Dry film photoresists of the invention, preferably AsahiCX-A240, TOK Ordyl P-50120. 干膜光刻胶可以用压滚机滚压到晶片上,通常以压力0.2〜0.5mPa,温度为80〜10(TC,速度为0.5〜1.5m/min的条件滚压。在这个条件下干膜光刻胶和凸点下金属层之间的粘和较好。干膜光刻胶和凸点下金属层之间的粘和主要取决于滚压的压力,通常滚压压力越高凸点下金属层和干膜光刻胶的粘和越好。如果想要获得轻微的铜渗镀(foot plating)而且在电镀焊料之后干膜光刻胶轮廓仍坚固,则优选滚压压力为0.2〜0.3mPa。滚压形成的干膜光刻胶的厚度为100~140 P m,优选为120〜140 um。 The dry film photoresist may rolling machine with a press roller to the wafer, typically at a pressure 0.2~0.5mPa, a temperature of 80~10 (TC, speed 0.5~1.5m / min rolling conditions. Dryness under this condition and better adhesion between the resist film and the under bump metal layer and the adhesive depends rolled between pressure a dry film photoresist and the under bump metal layer, usually rolling pressure higher bumps the dry film photoresist and the metal layer and the better the adhesion. If you want to get slight copper diffusion coating (foot plating) and a dry film photoresist profile is still strong after the plating of the solder, the rolling pressure is preferably 0.2~ 0.3mPa. the thickness of the dry film photoresist is formed roll 100 ~ 140 P m, preferably 120~140 um.

通常本发明的干膜光刻胶层曝光参数为曝光能量和焦距。 The present invention is generally a dry film photoresist layer exposure parameters for the exposure energy and focus. 优选釆用g 线光,且优选采用能量为200〜500mJ/cm2。 Preferably preclude the g-line light, and preferably using the energy of 200~500mJ / cm2. 其轮廓可以通过适宜的焦距调整到倾斜的轮廓。 The inclination can be adjusted to the contour of the profile by a suitable focal length.

在电镀凸点材料之前,先电镀一铜层和镍层。 Bump material prior to electroplating, a copper plating layer and the first nickel layer. 优选采用罗门哈斯电子级电镀液电镀铜层和镍层。 Rohm and Haas Electronic grade is preferably used copper plating solution and nickel layers. 在电镀铜时,在特定的滚压条件形成的干膜光刻胶轮廓下,电镀液将渗透到干膜光刻胶轮廓的边缘角落,这种现象在此称为"渗镀"。 When copper electroplating, at a dry film photoresist profile specific rolling conditions of formation, the plating solution will penetrate into the dry film photoresist edge corner profile, a phenomenon referred to herein as "diffusion coating." 然后用罗门哈斯电子级电镀液进行焊料的电镀,优选焊料 Then the solder plating, preferably with a solder plating solution Rohm and Haas Electronic grade

凸点材料为锡铅、锡银焊料,更优选凸点材料为锡63%、铅37%的共晶锡铅。 Bump material is a tin-lead, tin-silver solder bump material and more preferably 63% tin, 37% lead-tin-lead eutectic.

再去除光刻胶层,以凸点为掩模,对多余的凸点下金属进行各向同性刻蚀去除。 And then removing the photoresist layer to the bump as a mask, the under bump metal of the excess is etched away isotropically. 由于渗镀的存在,刻蚀凸点下金属时会形成较小的底切。 Because of the presence of infiltration of the coating, etching the bump will form a small undercut metal.

在凸点结构上沉积助焊剂,以防止高熔点氮化钛氧化物形成并覆盖凸点结构,该覆盖层会限制焊料回流和严重阻碍焊料对邻近欲结合表面的润湿。 The flux is deposited on the bump structures to prevent the formation of a refractory oxide of titanium nitride and covering the bump structure, the cover layer may limit the solder reflow solder and a serious impediment to be bonded to the adjacent surface wetting.

然后进行高温回流,形成焊料球。 Followed by high temperature reflow, the solder balls are formed.

本发明的焊料凸点的制作方法用于12〃晶片上,提高凸点下金属刻蚀的制程容许度,以及更容易控制凸点的底切程度,而且所得到的凸点更坚固。 Manufacturing method of the present invention, the solder bump on a wafer 12〃 improved process tolerance under bump metal etching, and easier to control the extent of the undercut bump, the bump and the resulting stronger. 本发明应用干膜光刻胶(DRF),与液体光刻胶比较,具有低成本和高产能的优点。 Application of a dry film photoresist (the DRF) according to the present invention, compared with the liquid photoresist, has the advantage of low cost and high capacity.

附图说明 BRIEF DESCRIPTION

图1是表示本发明的焊料凸点的制作流程的剖面图。 FIG. 1 is a sectional view of the present invention, the solder bump manufacturing process. 图2是本发明的焊料凸点制作过程中,滚压形成干膜光刻胶层的示意图。 FIG 2 is a schematic view of the solder bump manufacturing process according to the present invention, the roller is formed of a dry film photoresist layer.

图3A是传统的焊料凸点制作过程中,液体光刻胶膜曝光后的剖面SEM图。 3A is a conventional solder bump manufacturing process, the photoresist film is exposed to the liquid cross-sectional SEM image.

图3B是本发明的焊料凸点制作过程中,干膜光刻胶曝光后的剖面SEM图。 FIG 3B is a solder bump fabrication process of the present invention, after the dry film photoresist exposure sectional SEM image.

图4A是传统的焊料凸点制作过程中,电镀铜后的剖面SEM图,其中没有渗镀现象。 4A is a conventional solder bump manufacturing process, the copper cross-sectional SEM image, the phenomenon in which no diffusion coating.

图4B是本发明的焊料凸点制作过程中,电镀液渗镀到干膜光刻胶下的剖面SEM图。 FIG 4B is a solder bump fabrication process of the present invention, the plating solution to a cross-sectional SEM image of surface alloying under a dry film photoresist.

图5A是传统的焊料凸点制作过程中,刻蚀凸点下金属后的剖面SEM 图,其中有很严重的底切产生。 5A is a conventional solder bump manufacturing process, the cross-sectional SEM image after etching the metal bump, which has produced serious undercut.

图5B是本发明的焊料凸点制作过程中,刻蚀凸点下金属后的剖面SEM图,产生较小的底切。 FIG 5B is a solder bump fabrication process of the present invention, the cross-sectional SEM view of a metal bump under the etching, produce less undercutting.

图6是本发明的焊料凸点高温回流后的剖面SEM图。 FIG 6 is a cross-sectional SEM view of the present invention is a high temperature solder bump reflow.

附图标记说明 REFERENCE NUMERALS

1 形成有焊盘的晶片 A pad is formed in the wafer 1

2 凸点下金属溅射铜层 Sputtered copper layer under the metal bump 2

3 干膜光刻胶 3 dry film photoresist

31 曝光轮廓 31 exposure profile

4 开口 4 opening

5 电镀铜层 5 electroplated copper layer

6 电镀镍层 Nickel plating layer 6

7 焊料凸点 7 solder bumps

9 渗镀 9 diffusion coating

10 底切 Undercut 10

液体光刻胶层 Liquid photoresist layer

31' 曝光轮廓 31 'exposure profile

4, 开口 4, the opening

5' 电镀铜层 5 'electroplated copper layer

6' 电镀镍层 6 'electroless nickel

7, 焊料凸点 7, solder bumps

9' 无渗镀 9 'No Alloying

10' 底切 10 'undercut

15 压滚机 15 pressure roll machine

具体实施方式 Detailed ways

下面通过实施例详细介绍本发明。 The present invention is described below in detail by examples. 实施例 Example

以在12"的硅晶片上按照本发明的方法制作锡铅焊料凸点为例进行说明。 For the production of tin-lead solder bump method according to the present invention on a 12 "silicon wafer as an example.

图1为表示在已经形成了焊盘的硅晶片上制作焊料凸点的过程剖面图。 1 is a sectional view in FIG been formed during the production of the solder bump pads on the silicon wafer.

如图1A所示,在已经形成了焊盘的硅晶片1上,采用溅射方法形成凸点下金属铜层,厚度为5um。 1A, the pad has been formed on a silicon wafer 1, the under bump metal copper layer is formed using a sputtering method, a thickness of 5um.

如图2所示,用压滚机15,通常以压力0.2〜0.5mPa,温度为80〜100。 As shown in FIG. 2, with a pressure roller unit 15, typically a pressure 0.2~0.5mPa, the temperature is 80 ~ 100. C, 速度为0.5-1.5m/min,将厚度为100~140 ym的干膜光刻胶层滚压到硅晶片3上。 C, the speed of 0.5-1.5m / min, the roll 100 ~ 140 ym thick dry film photoresist layer onto a silicon wafer 3. 干膜光刻胶和凸点下金属层之间的粘和主要取决于滚压的压力。 And viscosity depends rolled between pressure a dry film photoresist and the under bump metal layers. 通常滚压压力越高凸点下金属层和干膜光刻胶的粘和越好。 Rolling pressure is generally higher under bump metal layer and a dry film photoresist and the better the adhesion. 如果想要获得轻微的铜渗镀(foot plating)而且在电镀焊料之后干膜光刻胶轮廓仍坚固, 则优选滚压压力为0.2〜0.3mPa。 If you want to get slight copper diffusion coating (foot plating) and a dry film resist after the plating of the solder remains solid outline, the roll pressure is preferably 0.2~0.3mPa. 在这个条件下千膜光刻胶和凸点下金属层之间的粘和较好。 One thousand and bumps photoresist film in this condition and good adhesion between the metal layers.

例如,在本实施例中,压力为0.3mPa,温度为105t:,速度为1.0m/min, 将干膜光刻胶3,如Asahi CX-A240、 TOK Ordyl P-50120干膜光刻胶,滚压到硅晶片1上,厚度为120um。 For example, in the present embodiment, a pressure of 0.3 mPa, a temperature of 105t :, speed of 1.0m / min, the dry film photoresist 3 as Asahi CX-A240, TOK Ordyl P-50120 dry film photoresist, rolled onto a silicon wafer 1, having a thickness of 120um.

通常本发明的干膜光刻胶层曝光参数为曝光能量和焦距。 The present invention is generally a dry film photoresist layer exposure parameters for the exposure energy and focus. 优选采用g 线光的能量可以为200〜500mJ/cm2。 Preferably in g-line light energy may 200~500mJ / cm2. 其轮廓可以通过适宜的焦距调整到倾斜的轮廓,如图3B所示。 The contour of the focal length can be adjusted by a suitable inclination of the profile, shown in Figure 3B. 其中31是曝光部分轮廓,从图中可以看出其曝光部分31的侧边倾斜,有利于在后续的电镀铜过程中形成渗镀。 Wherein the contour section 31 is exposed, which can be seen from FIG exposed side of the inclined portion 31, it facilitates the formation of diffusion coating in a subsequent copper electroplating process. 然后按照常规方法进行显影,形成将电镀填充焊料的开口4,如图1C所示。 Then developed in a conventional manner, an opening 4 is formed, as shown in FIG 1C is filled with solder plated.

在电镀焊料前,先用罗门哈斯电子级电镀液将铜电镀形成一层铜层5, 厚度为5um。 Before the solder plating, the plating first with Rohm and Haas Electronic grade copper electroplating solution to form a copper layer 5, a thickness of 5um. 在特定的滚压条件形成的干膜光刻胶轮廓下,电镀液将渗透到干膜光刻胶轮廓的边缘角落,在此称为"渗镀",如图4B中的9所示, 渗镀的厚度为l〜2um。 At a dry film photoresist profile specific rolling conditions of formation, the plating solution will penetrate into the dry film photoresist edge corner profile, referred to herein as "diffusion coating", as shown in FIG 4B 9, seepage plating thickness l~2um.

然后再电镀镍层6,厚度为liim,以防止铜扩散到焊料凸点中,再电镀共晶锡铅焊料,其中锡铅焊料为锡63%、铅37%。 Then nickel plating layer 6, the thickness of liim, to prevent the diffusion of copper into solder bumps, and then the eutectic tin-lead solder plating, tin-lead solder wherein tin 63%, lead 37%. 电镀锡铅焊料形成凸点7后,以该焊料凸点7为掩模刻蚀多余的凸点下金属铜,这时由于有1〜2 iim的电镀铜突出在底部,因此,在进行各向同性刻蚀时,如图5B所示,可以看出产生较小的底切IO,其深度只有l〜2um。 After plating tin-lead solder bumps 7 are formed, to the solder bump 7 of the metallic copper etching mask unwanted bump, then due to copper electroplating 1~2 iim projecting at the bottom, thus making each of the when isotropic etching, shown in Figure 5B, it can be seen to produce less undercutting IO, and so only the depth l~2um. 淀积助焊剂,并进行高温回流。 Deposition flux, and high-temperature reflow.

图6是该实施例的焊料凸点高温回流后形成的焊料球的剖面SEM图。 FIG 6 is a cross-sectional SEM view of a solder ball formed after the high temperature reflow solder bump embodiment of this embodiment. 从图中可以看出经过高温回流后的焊料球外观很好,且其机械性能优异, 能够满足如共晶锡铅焊料球的剪切力规格为大于35.4g/凸点的规格要求。 As can be seen from the figure through solder balls good appearance after the high temperature reflow, and excellent mechanical properties, such as shear force to meet the specifications of the eutectic tin-lead solder ball is larger than the specification 35.4g / bumps.

比较例 Comparative Example

以在12"的硅晶片上按照传统方法制作锡铅焊料凸点为例进行说明。 在已经形成了焊盘的晶片l上,釆用溅射方法形成凸点下金属铜层2, 厚度为3000A。 For the production of tin-lead solder bumps according to the conventional method in Example 12, "silicon wafer will be described. Has been formed on the wafer l pad, the under bump metal Bian copper layer formed by sputtering method, a thickness of 3000A .

采用旋涂法形成液体光刻胶膜,如LA卯OPM,厚度为60um,在预烘烤后进行曝光,形成如图3A所示的光刻胶轮廓。 Is formed by spin coating a liquid photoresist film, such as the OPM d LA, a thickness of 60um, prebaking after exposure, the resist profile is formed as shown in FIG Fig. 3A. 其中,3'是光刻胶层, 31'是曝光部分。 Wherein 3 'is a photoresist layer 31' is partially exposed.

从图3A中可以看出,曝光部分的侧边轮廓比较垂直。 As can be seen in FIG. 3A, the side profile of the exposed portion of the vertical comparison. 通过显影去除曝光部分的光刻胶后,形成开口4'并进行后烘烤。 After removing the photoresist by developing the exposed portions, after forming the openings 4 'and baked. 然后在开口4'中电镀铜层5',厚度为5ixm,再电镀形成一镍层6', 厚度为lixm,以防止铜扩散到焊料凸点中。 Then the opening 'electroplated copper layer 5 in' 4, a thickness of 5ixm, and then forming a plated nickel layer 6 ', having a thickness of lixm, to prevent the diffusion of copper into the solder bump. 液体光刻胶形成的膜由于与凸点下金属层的粘和非常好,因此在电镀铜的电镀液中不会产生渗镀。 Liquid photoresist film formed on the metal layer and the adhesive because the bump and is very good, so that no diffusion coating in a copper plating solution in the plating. 如图4A中的9'所示。 '9 shown in FIG. 4A.

再电镀共晶锡铅焊料形成焊料凸点7',其中锡铅焊料为Sn63。 Eutectic tin-lead solder electroplating and then forming solder bumps 7 ', which is a tin-lead solder Sn63. /0, Pb37%。 / 0, Pb37%. 电镀锡铅焊料形成凸点7'后,以该焊料凸点7'为掩模刻蚀多余的凸点下金属铜,如图5A所示,可以看出产生较大的底切10',其深度可以达至U5〜6y m。 ', The solder bumps 7 to the' electroplated tin-lead solder bumps 7 are formed as an etching mask the excess copper bumps, 5A, it can be seen a greater undercut 10 ', which depth may be up to U5~6y m.

采用干膜光刻胶的本发明的方案与采用液体光刻胶的比较例的方案进行比较,前者不仅产生的底切小和可以控制,而且得到的焊料球足够坚 Embodiment of the present invention employs a dry film photoresist is compared with solutions of Comparative Examples using a liquid photoresist, bottom former not only small and can be produced by cutting control, and to obtain sufficient solder balls Kennedy

固。 solid. ' '

由于干膜贴膜机台的费用是湿膜涂布机台的1/2,干膜贴膜工艺比较容易控制,干膜的原材料成本比湿膜便宜,因此采用本发明的方法可以显著降低制作成本,而且容易量产。 As the cost of a dry film laminator station is 1/2 of the wet film coating machine, a dry film process is relatively easy to control film, the dry film is cheaper than the raw material costs of the wet film, thus using the method of the present invention can significantly reduce production costs, and easy to mass production. 虽然通过以上实施例对本发明进行了较为详细的说明,但是本发明不仅仅限于以上实施例,在不脱离本发明构思的情况下,还可以包括更多其他等效实施例,而本发明的范围由所附的权利要求范围决定。 Although the above embodiments of the present invention has been described in detail, but the present invention is not limited to the above embodiments, without departing from the spirit of the present invention may further comprise additional other equally effective embodiments, the scope of the present invention by the appended claims range determination.

Claims (10)

1.一种焊料凸点的制作方法,依次包括如下步骤: 在已经形成有焊盘的晶片上溅射形成凸点下金属层; 形成干膜光刻胶层; 曝光、然后显影形成光刻胶的凸点开口图案; 在所述开口中先电镀铜层,然后电镀镍层;所述电镀过程中,采用渗镀方式使电镀液渗透到干膜光刻胶轮廓的边缘角落; 在所述开口中填充焊料凸点材料; 去除光刻胶; 以焊料凸点为掩模刻蚀凸点下金属层; 淀积助焊剂; 高温回流。 1. A method for fabricating solder bumps, in turn comprising the steps of: forming an under bump metal layer has been formed by sputtering on a wafer with a pad; dry film photoresist layer; exposed, and then developed to form a photoresist bump opening pattern; electroplated copper layer in the first opening, and a nickel plating layer; the electroplating process using a plating solution surface alloying manner to penetrate a dry film photoresist profile edge corner; the opening filling solder bump material; removing the photoresist; in the solder bumps as an etching mask bump metal layer; depositing a flux; high-temperature reflow.
2. 根据权利要求l所述的方法,其特征在于,所述的晶片是12〃晶片。 2. The method as claimed in claim l, wherein said wafer is a wafer 12〃.
3. 根据权利要求l所述的方法,其特征在于,所述的干膜光刻胶是Asahi CX-A240或TOK Ordyl P-50120。 3. The method as claimed in claim l, wherein said photoresist is a dry film Asahi CX-A240 or TOK Ordyl P-50120.
4. 根据权利要求l所述的方法,其特征在于,所述的干膜光刻胶层厚度为100〜140ii m。 4. The method as claimed in claim l, wherein said dry film photoresist layer having a thickness of 100~140ii m.
5. 根据权利要求4所述的方法,其特征在于,所述的干膜光刻胶层厚度为120〜140u m。 The method according to claim 4, characterized in that, the dry film photoresist layer having a thickness of 120~140u m.
6. 根据权利要求1〜5中的任一项所述的方法,其特征在于,所述的干膜光刻胶层是通过滚压形成。 6. A method according to any one of claims 1 ~ 5 of the preceding claims, characterized in that, the dry film photoresist layer is formed by rolling.
7. 根据权利要求6所述的方法,其特征在于,所述的滚压条件为压力0.2〜0.5mPa,温度为80〜105。 7. The method according to claim 6, wherein said rolling conditions are a pressure 0.2~0.5mPa, temperature of 80~105. C,速度为0.5〜1.5m/min。 C, speed 0.5~1.5m / min.
8. 根据权利要求7所述的方法,其特征在于,所述的滚压条件为压力0.2〜0.3mPa,温度为105。 8. The method according to claim 7, wherein said rolling conditions are a pressure 0.2~0.3mPa, temperature of 105. C,速度为lm/min。 C, a speed of lm / min.
9. 根据权利要求l所述的方法,其特征在于,所述的曝光采用g线光, 能量为200〜500mJ/cm2。 9. The method as claimed in claim l, wherein said exposure using g-line light, energy 200~500mJ / cm2.
10. 根据权利要求l所述的方法,其特征在于,所述溅射的凸点下金属为铜或钛。 10. A method as claimed in claim l, wherein said sputtering under bump metal is copper or titanium.
CNB2006101477884A 2006-12-22 2006-12-22 Method for making tin solder bump CN100561697C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2006101477884A CN100561697C (en) 2006-12-22 2006-12-22 Method for making tin solder bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2006101477884A CN100561697C (en) 2006-12-22 2006-12-22 Method for making tin solder bump

Publications (2)

Publication Number Publication Date
CN101207047A CN101207047A (en) 2008-06-25
CN100561697C true CN100561697C (en) 2009-11-18

Family

ID=39567118

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101477884A CN100561697C (en) 2006-12-22 2006-12-22 Method for making tin solder bump

Country Status (1)

Country Link
CN (1) CN100561697C (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101882596B (en) 2009-05-08 2012-06-06 中芯国际集成电路制造(上海)有限公司 Method for etching metal layer
CN102496584A (en) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 Method for forming solder bump
CN102496580B (en) * 2011-12-19 2016-02-03 南通富士通微电子股份有限公司 Method of forming a solder bump
CN110225667A (en) * 2013-09-11 2019-09-10 花王株式会社 The manufacturing method of resin mask layer detergent composition and circuit substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW508779B (en) 2001-11-02 2002-11-01 Taiwan Semiconductor Mfg Manufacturing method of soldering bump
CN1416311A (en) 2001-10-29 2003-05-07 富士通株式会社 Method of foming adhesion adhesion structure between electrodes and adhesion structure between electrodes
CN1689150A (en) 2002-10-09 2005-10-26 飞思卡尔半导体公司 Method for eliminating voiding in plated solder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1416311A (en) 2001-10-29 2003-05-07 富士通株式会社 Method of foming adhesion adhesion structure between electrodes and adhesion structure between electrodes
TW508779B (en) 2001-11-02 2002-11-01 Taiwan Semiconductor Mfg Manufacturing method of soldering bump
CN1689150A (en) 2002-10-09 2005-10-26 飞思卡尔半导体公司 Method for eliminating voiding in plated solder

Also Published As

Publication number Publication date
CN101207047A (en) 2008-06-25

Similar Documents

Publication Publication Date Title
US6388203B1 (en) Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6732913B2 (en) Method for forming a wafer level chip scale package, and package formed thereby
CN1606155B (en) Pipe core with pillar structures and manufacturing method thereof
US5376584A (en) Process of making pad structure for solder ball limiting metallurgy having reduced edge stress
US6501185B1 (en) Barrier cap for under bump metal
US5293006A (en) Solder bump including circular lip
KR100339190B1 (en) Barrier layers for electroplated snpb eutectic solder joints
US6232212B1 (en) Flip chip bump bonding
US20120012642A1 (en) Interconnections for flip-chip using lead-free solders and having reaction barrier layers
TWI460836B (en) Conductive pillar for semiconductor substrate and method of manufacture
US8476769B2 (en) Through-silicon vias and methods for forming the same
KR101344553B1 (en) Method and structure for adhesion of intermetallic compound (imc) on cu pillar bump
EP0815593B1 (en) Solder bump fabrication methods and structure including a titanium barrier layer
CN102820290B (en) Connector package design of integrated circuits
US8441124B2 (en) Cu pillar bump with non-metal sidewall protection structure
US20020093107A1 (en) Wafer level package incorporating dual stress buffer layers for i/o redistribution
TWI449140B (en) Cu pillar bump with non-metal sidewall spacer and metal top cap
US6077726A (en) Method and apparatus for stress relief in solder bump formation on a semiconductor device
US6888255B2 (en) Built-up bump pad structure and method for same
US20030222352A1 (en) Under-bump metallugical structure
US10056312B2 (en) Integrated circuit packages and methods for forming the same
US7323406B2 (en) Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
US5943597A (en) Bumped semiconductor device having a trench for stress relief
US9607936B2 (en) Copper bump joint structures with improved crack resistance
JP4704679B2 (en) Under bump metal of semiconductor element

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
GR01 Patent grant
C14 Grant of patent or utility model
TR01 Transfer of patent right

Effective date of registration: 20111201

Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18

Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation

Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation

Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18

Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation

ASS Succession or assignment of patent right

Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING

Effective date: 20111201

C41 Transfer of patent application or patent right or utility model