JP5277788B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5277788B2
JP5277788B2 JP2008208825A JP2008208825A JP5277788B2 JP 5277788 B2 JP5277788 B2 JP 5277788B2 JP 2008208825 A JP2008208825 A JP 2008208825A JP 2008208825 A JP2008208825 A JP 2008208825A JP 5277788 B2 JP5277788 B2 JP 5277788B2
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insulating film
copper
electrode
semiconductor device
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勝 川上
哲理 青柳
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Sony Corp
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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a connection failure in flip chip connection by forming a large number of bumps by aligning heights. <P>SOLUTION: This semiconductor device has a semiconductor chip 10, a plurality of electrode pads 11 formed on a main surface 10S of the semiconductor chip, an insulating film 21 formed on the main surface 10S of the semiconductor chip and covering the respective electrode pads 11, openings 24 formed at the insulating film 21 on the respective electrode pads 11, and the bumps 12 connected to the respective electrode pads 11 via the respective openings 24 in the insulating film 21. The bumps 12 have copper electrodes 13 connected to the electrode pads 11 via the openings 24, metallic connecting layers 14 formed on surfaces of the copper electrodes 13, and barrier layers 15 formed at sides of the copper electrodes 13 and the metallic connecting layers 14 and at inner surfaces of the openings 24, and the respective copper electrodes 13 are formed equal in height, and the respective metallic connecting layers 14 are formed equal in thickness. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、半導体装置およびその製造方法に関し、特にはチップオンチップ接続のバンプを備えた半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having bumps for chip-on-chip connection and a manufacturing method thereof.

携帯機器の小型化、低消費電力化、低コスト化のために、複数チップを一つのパッケージに搭載したＳｉＰ（System in package）が広く用いられている。チップの接続方式には、従来より、ワイヤ接続、フリップチップ接続が用いられているが、チップ間の伝送速度の点でＳｏＣ（System on chip）より劣ることがデメリットとして挙げられる。   In order to reduce the size, power consumption, and cost of portable devices, SiP (System in package) in which a plurality of chips are mounted in one package is widely used. Conventionally, wire connection and flip chip connection are used as chip connection methods. However, the chip connection method is inferior to SoC (System on chip) in terms of transmission speed between chips.

フリップチップ接続方式では、チップに接続用バンプを形成し、基板もしくは他のチップとバンプを介して物理的かつ電気的に接続させる。
特に、図７に示すように、上側チップ１０１と下側チップ１０２同士を接続させるＣｏＣ（Chip on Chip）接続では、基板配線を介さずに上側チップ１０１と下側チップ１０２間を電気的に接続するため、配線長、容量の低減が可能である。
加えて、上側チップ１０１、下側チップ１０２のそれぞれに、数千個の径が数十μｍのバンプ１１１、１１２を配置し、対向するバンプ１１１、１１２同士を接続している。このため、基板接続型のフリップチップ接続と比較して、バンド幅を飛躍的に増加させることが可能となる。この結果、ＣｏＣ接続は伝送速度向上が可能となり、従来のＳｉＰのデメリットを克服できる。
また、上側チップ１０１、下側チップ１０２間には封止樹脂１２１が充填されている。 In the flip chip connection method, bumps for connection are formed on a chip and are physically and electrically connected to a substrate or another chip via the bumps.
In particular, as shown in FIG. 7, in the CoC (Chip on Chip) connection in which the upper chip 101 and the lower chip 102 are connected to each other, the upper chip 101 and the lower chip 102 are electrically connected without passing through the substrate wiring. Therefore, the wiring length and capacity can be reduced.
In addition, thousands of bumps 111 and 112 having a diameter of several tens of μm are arranged on each of the upper chip 101 and the lower chip 102, and the bumps 111 and 112 facing each other are connected to each other. Therefore, it is possible to dramatically increase the bandwidth as compared with the substrate connection type flip chip connection. As a result, the CoC connection can improve the transmission speed and overcome the disadvantages of the conventional SiP.
A sealing resin 121 is filled between the upper chip 101 and the lower chip 102.

上記フリップチップ接続のバンプ材料には、スズ（Ｓｎ）、金（Ａｕ）、銅（Ｃｕ）などが用いられており、バンプ形成プロセスは主にセミアディティブ法が主流である。
このセミアディティブ法は、シード層を形成した後、このシード層上にレジスト膜を形成する。そして、バンプ形成位置のレジスト膜に開口部を形成するパターニングを行う。次いで、開口部内のシード層上に、電気めっき（電解めっき）法で金属層とはんだ層を形成した後、レジスト膜を除去する。さらに、余剰なシード層を除去するという工程を順に行い、金属層とはんだ層からなるバンプを形成する方法である（例えば、特許文献１、非特許文献１参照。）。 Tin (Sn), gold (Au), copper (Cu), etc. are used as the bump material for the flip chip connection, and the semi-additive method is mainly used as the bump forming process.
In this semi-additive method, after forming a seed layer, a resist film is formed on the seed layer. Then, patterning for forming an opening in the resist film at the bump forming position is performed. Next, after forming a metal layer and a solder layer on the seed layer in the opening by an electroplating (electrolytic plating) method, the resist film is removed. Further, a process of removing an excessive seed layer is performed in order to form a bump made of a metal layer and a solder layer (see, for example, Patent Document 1 and Non-Patent Document 1).

しかし、電解めっきで、数千個ものバンプとなるめっき層を形成しているため、めっき形成領域の全域の電流密度を均一にすることは困難である。そのため、めっき形成領域の電流密度が不均一になって、バンプの高さにばらつきを生じていた。このバンプの高さばらつきは、例えば２．５μｍ程度になっていた。
また、上記プロセスでは、余剰なシード層を除去した後、各金属層とはんだ層をフラックス層で被覆してはんだ層のリフロー処理を行い、はんだ層表面を曲面に形成している。このリフロー処理を行っても、初めに形成された金属層とはんだ層の高さが部分的に異なっているため、リフロー後の金属層とはんだ層を合わせたバンプの高さにばらつきを生じていた。 However, since a plating layer that becomes thousands of bumps is formed by electrolytic plating, it is difficult to make the current density in the entire plating formation region uniform. For this reason, the current density in the plating formation region becomes non-uniform, resulting in variations in bump height. The bump height variation was, for example, about 2.5 μm.
In the above process, after removing the excess seed layer, each metal layer and the solder layer are covered with a flux layer, and the solder layer is reflowed to form a curved solder surface. Even when this reflow treatment is performed, the height of the bump formed by combining the metal layer and the solder layer after reflowing varies because the height of the metal layer and the solder layer formed at the beginning are partially different. It was.

特開２００５−５１１２８号公報JP 2005-51128 A Takayuki Ezaki, Kazuhiro Kondo, Hiroshi Ozaki, Naoto Sasaki,Hitoshi Yonenura, Masaki Kitano, Shuji Tanaka, Teruo Hirayama著 「A 160Gb/s Interface Design Configuration for Multichips LSI」2004 IEEE International Solid-State Circuits Conference ２００４年Takayuki Ezaki, Kazuhiro Kondo, Hiroshi Ozaki, Naoto Sasaki, Hitoshi Yonenura, Masaki Kitano, Shuji Tanaka, Teruo Hirayama "A 160Gb / s Interface Design Configuration for Multichips LSI" 2004 IEEE International Solid-State Circuits Conference 2004

解決しようとする問題点は、電解めっきで多数のバンプを形成したとき、バンプの高さがばらついていたため、フリップチップ接続させた場合、接続が不完全なバンプが生じて、接続不良が発生していた点である。   The problem to be solved is that when a large number of bumps were formed by electrolytic plating, the bump heights varied, so when flip chip connection was made, bumps that were incompletely connected resulted in poor connection. It was a point.

本発明は、高さをそろえて多数のバンプを形成することを可能とし、フリップチップ接続での接続不良を解消することを可能にする。   The present invention makes it possible to form a large number of bumps with the same height, and to eliminate connection failure in flip chip connection.

本発明の半導体装置は、半導体チップと、前記半導体チップの主面に形成された複数の電極パッドと、前記半導体チップの主面に形成されていて前記各電極パッドを被覆する絶縁膜と、前記各電極パッド上の前記絶縁膜に形成された開口部と、前記絶縁膜上に前記各
開口部を通じて前記各電極パッドに接続されたバンプを有し、前記バンプは、前記開口部内に埋め込まれるとともに外周部が前記絶縁膜上に形成された銅電極と、前記銅電極上面に形成された金属接続層と、前記銅電極の側部から前記開口部の側壁を含む内面にかけて連続的に形成されたバリア層を有し、前記各銅電極は同等の高さに形成され、前記各金属接続層は同等の厚さに形成されている。 The semiconductor device of the present invention includes a semiconductor chip, a plurality of electrode pads formed on the main surface of the semiconductor chip, an insulating film formed on the main surface of the semiconductor chip and covering the electrode pads, An opening formed in the insulating film on each electrode pad, and a bump connected to the electrode pad through the opening on the insulating film, the bump being embedded in the opening copper electrode outer peripheral portion is formed on the insulating film, and a metal connection layer formed on the copper electrode top surface, successively formed from the side of the copper electrode over the inner surface including a side wall of the opening The copper electrodes are formed to have the same height, and the metal connection layers are formed to have the same thickness.

本発明の半導体装置では、バンプを形成する銅電極は同等の高さに形成され、またバンプを形成する金属接続層は同等の厚さに形成されていることから、各バンプは同等の高さに形成されている。また銅電極および金属接続層の側部にバリア層が形成されていることから、たとえ金属接続層を形成した後に金属接続層をリフロー処理することがあっても、バリア層によって金属接続層の流れ出しが抑えられる。このため、金属接続層を含む各バンプの高さは、同等な高さとなっている。   In the semiconductor device according to the present invention, the copper electrodes for forming the bumps are formed at the same height, and the metal connection layers for forming the bumps are formed at the same thickness, so that each bump has the same height. Is formed. In addition, since the barrier layer is formed on the sides of the copper electrode and the metal connection layer, even if the metal connection layer is reflowed after the metal connection layer is formed, the barrier layer causes the metal connection layer to flow out. Is suppressed. For this reason, the height of each bump including the metal connection layer is equivalent.

本発明の半導体装置の製造方法は、半導体チップの主面に複数の電極パッドを形成する工程と、前記半導体チップの主面に前記各電極パッドを被覆する第１絶縁膜を形成する工程と、前記電極パッド上の前記第１絶縁膜に第１開口部を形成する工程と、前記第１絶縁膜の表面に前記各第１開口部が埋め込まれる第２絶縁膜を形成する工程と、前記電極パッド上の前記第２絶縁膜に前記第１開口部よりも大きい第２開口部を形成し、該第２開口部の下部に連続する前記第１開口部を再び開口する工程と、前記第１、第２開口部の側壁を含む内面および前記第２絶縁膜の表面にバリア層を形成する工程と、前記バリア層を介して前記第１、第２開口部の内部が埋め込まれる銅膜を形成する工程と、化学的機械研磨によって前記第２絶縁膜上の前記銅膜および前記バリア層を除去して、前記第１、第２開口部内に前記バリア層を介して前記銅膜からなる銅電極を形成する工程と、前記第２絶縁膜を除去する工程と、無電解めっきによって前記銅電極上に金属接続層を形成する工程を有する。 The method for manufacturing a semiconductor device of the present invention includes a step of forming a plurality of electrode pads on a main surface of a semiconductor chip, a step of forming a first insulating film covering the electrode pads on the main surface of the semiconductor chip, Forming a first opening in the first insulating film on the electrode pad; forming a second insulating film in which the first opening is embedded in a surface of the first insulating film; and the electrode Forming a second opening larger than the first opening in the second insulating film on the pad, and re-opening the first opening continuously below the second opening; Forming a barrier layer on the inner surface including the sidewall of the second opening and the surface of the second insulating film, and forming a copper film in which the inside of the first and second openings is embedded via the barrier layer And performing the chemical mechanical polishing on the second insulating film Removing the film and the barrier layer to form a copper electrode made of the copper film in the first and second openings via the barrier layer; removing the second insulating film; Forming a metal connection layer on the copper electrode by electrolytic plating;

本発明の半導体装置の製造方法では、第１、第２開口部内を埋め込むように銅膜を形成した後、化学的機械研磨によって第２絶縁膜上の銅膜およびバリア層を除去して、第１、第２開口部内にバリア層を介して銅膜からなる銅電極が形成される。したがって、各銅電極は、第１、第２開口部内を満たすように、表面が平坦な、均一な高さに形成される。
また、無電解めっきによって、各銅電極上に金属接続層を形成しているため、金属接続層は均一な厚さに形成される。通常、無電解めっきは、電解めっきのように電流密度の差が生じることがないので、めっき成長が、半導体チップの全域において均一になる。
たとえ金属接続層を形成した後に金属接続層をリフロー処理することがあっても、バリア層によって金属接続層の流れ出しが抑えられるので、金属接続層を含む各バンプの高さは、同等な高さが維持される。
よって、銅電極および金属接続層で形成される複数のバンプは、高さが同等なものに形成される。 In the semiconductor device manufacturing method of the present invention, after forming the copper film so as to fill the first and second openings, the copper film and the barrier layer on the second insulating film are removed by chemical mechanical polishing, 1. A copper electrode made of a copper film is formed in the second opening through a barrier layer. Therefore, each copper electrode is formed in a uniform height with a flat surface so as to fill the first and second openings.
Moreover, since the metal connection layer is formed on each copper electrode by electroless plating, the metal connection layer is formed with a uniform thickness. Normally, electroless plating does not cause a difference in current density unlike electrolytic plating, so that plating growth is uniform over the entire area of the semiconductor chip.
Even if the metal connection layer may be reflowed after the metal connection layer is formed, the flow of the metal connection layer is suppressed by the barrier layer, so the height of each bump including the metal connection layer is the same height. Is maintained.
Therefore, the plurality of bumps formed of the copper electrode and the metal connection layer are formed to have the same height.

本発明の半導体装置は、複数のバンプの全ては高さが同等なものに形成されているため、別の半導体装置に形成されたバンプとフリップチップ接続させた場合に全てのバンプで確実に接続ができるので、接続不良が発生しなくなるという利点がある。
よって、フリップチップ接続における歩留まりの向上、信頼性の向上が図れる。 In the semiconductor device of the present invention, all of the plurality of bumps are formed to have the same height. Therefore, when the bump formed on another semiconductor device is flip-chip connected, all the bumps are securely connected. Therefore, there is an advantage that connection failure does not occur.
Therefore, it is possible to improve yield and reliability in flip chip connection.

本発明の半導体装置の製造方法は、全バンプの高さが同等なものに形成されるため、別の半導体装置に形成されたバンプとフリップチップ接続させた場合に全てのバンプで確実に接続ができるので、接続不良が発生しなくなるという利点がある。
よって、フリップチップ接続における歩留まりの向上、信頼性の向上が図れる半導体装置を製造できる。 Since the semiconductor device manufacturing method of the present invention is formed so that all bumps have the same height, all bumps can be securely connected when flip-chip connected to bumps formed on another semiconductor device. Therefore, there is an advantage that connection failure does not occur.
Therefore, it is possible to manufacture a semiconductor device that can improve yield and reliability in flip-chip connection.

本発明の半導体装置に係る一実施の形態を、図１に示したバンプ部平面図およびバンプおよびその周辺部の縦断面図によって説明する。   One embodiment of a semiconductor device according to the present invention will be described with reference to a plan view of a bump portion shown in FIG. 1 and a longitudinal sectional view of the bump and its peripheral portion.

図１に示すように、半導体チップ１０を有する。この半導体チップ１０は、詳細は図示していないが、通常の半導体チップであり、例えば、半導体基板に集積回路素子およびこの集積回路素子に接続する配線が形成され、絶縁膜からなる保護膜により被覆されたものである。
この半導体チップ１０の主面１０Ｓには、上記集積回路素子（図示せず）、上記配線（図示せず）等に接続された、複数の電極パッド１１が形成されている。
図面では、代表して一つの電極パッド１１を示したが、本発明の半導体装置１では、半導体チップ１０の主面１０Ｓに例えば数千個の上記電極パッド１１が形成されている。
上記電極パッド１１は、例えばアルミニウム電極で形成されている。もちろん、アルミニウム以外の金属電極、例えば、銅電極、銅合金電極、アルミニウム合金電極等であってもよい。 As shown in FIG. 1, a semiconductor chip 10 is provided. Although not shown in detail, the semiconductor chip 10 is a normal semiconductor chip. For example, an integrated circuit element and wiring connected to the integrated circuit element are formed on a semiconductor substrate and covered with a protective film made of an insulating film. It has been done.
A plurality of electrode pads 11 connected to the integrated circuit element (not shown), the wiring (not shown) and the like are formed on the main surface 10S of the semiconductor chip 10.
In the drawing, one electrode pad 11 is shown as a representative, but in the semiconductor device 1 of the present invention, for example, several thousand electrode pads 11 are formed on the main surface 10S of the semiconductor chip 10.
The electrode pad 11 is made of, for example, an aluminum electrode. Of course, a metal electrode other than aluminum, for example, a copper electrode, a copper alloy electrode, an aluminum alloy electrode, or the like may be used.

上記半導体チップ１０の主面１０Ｓには、上記各電極パッド１１を被覆する絶縁膜２１が形成されている。この絶縁膜２１は、例えば、下層に形成された酸化シリコン膜２２と、その酸化シリコン膜２２上に形成された窒化シリコン膜２３とからなる。
上記各電極パッド１１上の上記絶縁膜２１には、開口部２４が形成されている。 On the main surface 10S of the semiconductor chip 10, an insulating film 21 that covers the electrode pads 11 is formed. The insulating film 21 includes, for example, a silicon oxide film 22 formed in a lower layer and a silicon nitride film 23 formed on the silicon oxide film 22.
Openings 24 are formed in the insulating film 21 on the electrode pads 11.

上記絶縁膜２１には、上記各開口部２４を通じて上記各電極パッド１１に接続されたバンプ１２が形成されている。
上記バンプ１２は、上記開口部２４を通じて上記電極パッド１１に接続する銅電極１３と、この銅電極１３表面に形成された金属接続層１４と、上記銅電極１３および上記金属接続層１４の側部および上記開口部２４の内面に形成されたバリア層１５を有する。
上記金属接続層１４は、スズ、金、ニッケルのいずれかで形成されている。
上記バリア層１５は、例えば、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜の少なくとも１種で形成されている。例えば、絶縁膜２１との密着性をよくするためのチタン膜と、このチタン膜表面に形成されたタンタル膜もしくは窒化タンタル膜との積層膜で形成することもできる。この場合、タンタル膜、窒化タンタル膜が主としてバリア層の機能を有する。このバリア層の機能としては、絶縁膜２１中の酸素が銅電極１３中に拡散して銅電極１３が酸化されるのを防止するとともに、銅電極１３の銅が絶縁膜２１中に拡散するのを防止する。
そして、上記各銅電極１３は同等の高さに形成されていて、上記各金属接続層１４は同等の厚さに形成されている。
上記のように半導体装置１が構成されている。 Bumps 12 connected to the electrode pads 11 through the openings 24 are formed on the insulating film 21.
The bump 12 includes a copper electrode 13 connected to the electrode pad 11 through the opening 24, a metal connection layer 14 formed on the surface of the copper electrode 13, and side portions of the copper electrode 13 and the metal connection layer 14. And a barrier layer 15 formed on the inner surface of the opening 24.
The metal connection layer 14 is formed of any one of tin, gold, and nickel.
The barrier layer 15 is formed of, for example, at least one of a titanium film, a titanium nitride film, a tantalum film, and a tantalum nitride film. For example, it can be formed of a laminated film of a titanium film for improving adhesion to the insulating film 21 and a tantalum film or a tantalum nitride film formed on the surface of the titanium film. In this case, the tantalum film and the tantalum nitride film mainly function as a barrier layer. As a function of this barrier layer, oxygen in the insulating film 21 is prevented from diffusing into the copper electrode 13 to oxidize the copper electrode 13, and copper in the copper electrode 13 is diffused into the insulating film 21. To prevent.
The copper electrodes 13 are formed with the same height, and the metal connection layers 14 are formed with the same thickness.
The semiconductor device 1 is configured as described above.

本発明の半導体装置１では、各バンプ１２を形成する銅電極１３は同等の高さに形成され、また各バンプ１２を形成する金属接続層１４は同等の厚さに形成されていることから、各バンプ１２は同等の高さに形成されている。また銅電極１３および金属接続層１４の側部にバリア層１５が形成されていることから、たとえ金属接続層１４を形成した後に金属接続層１４をリフロー処理しても、バリア層１５によって金属接続層１４の流れ出しが抑えられる。このため、金属接続層１４を含む各バンプ１２の高さは、同等な高さとなっている。   In the semiconductor device 1 of the present invention, the copper electrodes 13 that form the bumps 12 are formed to have the same height, and the metal connection layers 14 that form the bumps 12 are formed to have the same thickness. Each bump 12 is formed at the same height. Further, since the barrier layer 15 is formed on the sides of the copper electrode 13 and the metal connection layer 14, even if the metal connection layer 14 is reflowed after the metal connection layer 14 is formed, the metal connection is performed by the barrier layer 15. The outflow of the layer 14 is suppressed. For this reason, the height of each bump 12 including the metal connection layer 14 is equivalent.

次に、上記半導体装置１を用いたフリップチップ接続の一例を以下に説明する。
図２に示すように、上記半導体装置１に形成されたバンプ１２（１２−１）と、本発明の構成を有する上記半導体装置１とは別の半導体装置２に形成されたバンプ１２（１２−２）とを対向させる。そして、一方の半導体装置、例えば半導体装置２を矢印方向にフェースダウンしてバンプ１２−１、１２−２同士を接続させる。なお、図面では、フェースダウンする状態を示した。
この場合、バンプ１２（１２−１）は全て高さが同等であり、バンプ１２（１２−２）も全て高さが同等であるから、全ての対向するバンプ１２−１、１２−２同士の接続が確実にできる。
したがって、接続不良が発生しなくなるという利点がある。
よって、フリップチップ接続における歩留まりの向上、信頼性の向上が図れる。
また図示はしていないが、半導体装置１、２間には封止樹脂が充填される。 Next, an example of flip chip connection using the semiconductor device 1 will be described below.
As shown in FIG. 2, bumps 12 (12-1) formed on the semiconductor device 1 and bumps 12 (12-) formed on a semiconductor device 2 different from the semiconductor device 1 having the configuration of the present invention. 2). Then, one of the semiconductor devices, for example, the semiconductor device 2 is faced down in the direction of the arrow to connect the bumps 12-1 and 12-2. In the drawing, the face-down state is shown.
In this case, all the bumps 12 (12-1) have the same height, and all the bumps 12 (12-2) have the same height. Connection can be made reliably.
Therefore, there is an advantage that connection failure does not occur.
Therefore, it is possible to improve yield and reliability in flip chip connection.
Although not shown, a sealing resin is filled between the semiconductor devices 1 and 2.

上記接続例では、半導体装置１、２間の接続を示したが、上記半導体装置１と回路基板のバンプ（図示せず）との接続であっても同様な効果が期待できる。   In the above connection example, the connection between the semiconductor devices 1 and 2 is shown, but the same effect can be expected even when the semiconductor device 1 is connected to a bump (not shown) of the circuit board.

次に、本発明の半導体装置の製造方法に係る一実施の形態を、図３に示したフローチャートおよび図４〜図６に示したバンプおよびその周辺部の製造工程断面図によって説明する。この製造方法は、前記図１を参照して説明した半導体装置１を製造する工程の一例である。   Next, an embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to a flowchart shown in FIG. 3 and bumps shown in FIG. 4 to FIG. This manufacturing method is an example of a process for manufacturing the semiconductor device 1 described with reference to FIG.

図３に示すように、「始め：前工程完成ウエハの用意」Ｓ１で、前工程を終了した完成ウエハを用意する。図４〜図６では、一例として、一つのバンプの形成領域に着目して、その断面を示す。
また図示はしていないが、ウエハに形成された半導体チップは、通常の半導体チップであり、例えば、半導体基板に集積回路素子およびこの集積回路素子に接続する配線が形成され、保護膜により被覆されたものである。 As shown in FIG. 3, in “Start: Preparation of Completed Previous Process Wafer” S <b> 1, a completed wafer that has completed the previous process is prepared. In FIGS. 4 to 6, as an example, a cross section is shown focusing on one bump formation region.
Although not shown, the semiconductor chip formed on the wafer is a normal semiconductor chip. For example, an integrated circuit element and wiring connected to the integrated circuit element are formed on a semiconductor substrate and covered with a protective film. It is a thing.

図４（１）に示すように、上記半導体チップ１０の主面１０Ｓには、上記集積回路素子（図示せず）、上記配線（図示せず）等に接続された、複数の電極パッド１１が形成されている。
図面では、代表して一つの電極パッド１１を示したが、上記半導体チップ１０の主面１０Ｓに、例えば数百個ないし数千個の上記電極パッド１１が形成されている。
上記電極パッド１１は、例えばアルミニウム電極で形成されている。もちろん、アルミニウム以外の金属電極、例えば、銅電極、銅合金電極、アルミニウム合金電極等であってもよい。 As shown in FIG. 4A, the main surface 10S of the semiconductor chip 10 has a plurality of electrode pads 11 connected to the integrated circuit element (not shown), the wiring (not shown), and the like. Is formed.
In the drawing, one electrode pad 11 is shown as a representative, but for example, hundreds to thousands of the electrode pads 11 are formed on the main surface 10S of the semiconductor chip 10.
The electrode pad 11 is made of, for example, an aluminum electrode. Of course, a metal electrode other than aluminum, for example, a copper electrode, a copper alloy electrode, an aluminum alloy electrode, or the like may be used.

次に、上記半導体チップ１０の表面に上記各電極パッド１１を被覆する第１絶縁膜２１（前記図１を参照して説明した絶縁膜２１に相当するため、同一符号付与した。）を形成する。この第１絶縁膜２１は、以下のように形成する。例えば、酸化シリコン膜２２を形成した後、その酸化シリコン膜２２上に窒化シリコン膜２３を形成する。この窒化シリコン膜２３は、後の工程での酸化シリコン膜のエッチング時のエッチングストッパとしても機能する。また上記酸化シリコン膜２２は、上記窒化シリコン膜２３の応力を緩和する。   Next, a first insulating film 21 (corresponding to the insulating film 21 described with reference to FIG. 1 is given the same reference numeral) is formed on the surface of the semiconductor chip 10 so as to cover the electrode pads 11. . The first insulating film 21 is formed as follows. For example, after the silicon oxide film 22 is formed, a silicon nitride film 23 is formed on the silicon oxide film 22. The silicon nitride film 23 also functions as an etching stopper when the silicon oxide film is etched in a later process. The silicon oxide film 22 relieves stress on the silicon nitride film 23.

次いで、通常のレジスト塗布技術およびリソグラフィ技術等によって、上記電極パッド１１上に開口部を有するレジストマスク（図示せず）を上記第１絶縁膜２１上に形成した後、それをエッチングマスクに用いて、上記第１絶縁膜２１をエッチングする。その結果、上記電極パッド１１上の上記第１絶縁膜２１に第１開口部２４（前記図１を参照して説明した開口部２４に相当するため、同一符号付与した。）が形成される。
上記エッチング後に上記レジストマスクを除去する。 Next, a resist mask (not shown) having an opening on the electrode pad 11 is formed on the first insulating film 21 by a normal resist coating technique and a lithography technique, and then used as an etching mask. Then, the first insulating film 21 is etched. As a result, a first opening 24 (corresponding to the opening 24 described with reference to FIG. 1 is given the same reference numeral) is formed in the first insulating film 21 on the electrode pad 11.
The resist mask is removed after the etching.

次に、図３に示すように、「絶縁膜の形成」工程Ｓ２を行う。
この工程では、図４（２）に示すように、上記第１絶縁膜２１上に、上記各第１開口部２４が埋め込まれる第２絶縁膜２５を形成する。
上記第２絶縁膜２５は、その後に形成されるバンプの高さと同一の膜厚、もしくは、それより厚い膜厚とする。上記第２絶縁膜２５は次工程以降のめっき、化学的機械研磨（ＣＭＰ）後に除去できる材料で形成する。そのような材料は、例えば酸化シリコン膜がある。 Next, as shown in FIG. 3, an “insulating film formation” step S2 is performed.
In this step, as shown in FIG. 4B, a second insulating film 25 in which the first openings 24 are embedded is formed on the first insulating film 21.
The second insulating film 25 has the same film thickness as the bump formed later or a film thickness larger than that. The second insulating film 25 is formed of a material that can be removed after plating and chemical mechanical polishing (CMP) in the subsequent steps. An example of such a material is a silicon oxide film.

次に、図３に示すように、「レジストマスクの形成」工程Ｓ３を行う。
この工程では、図４（３）に示すように、上記第２絶縁膜２５上にレジスト塗布技術によりレジスト膜４１を形成する。次いで、リソグラフィ技術（例えば露出、現像、ベーキング等）によって、上記第１開口部２４上方に、例えば第１開口部２４より大きい口径のレジスト開口部４２を形成する。 Next, as shown in FIG. 3, a “resist mask formation” step S3 is performed.
In this step, as shown in FIG. 4C, a resist film 41 is formed on the second insulating film 25 by a resist coating technique. Next, a resist opening 42 having a larger diameter than, for example, the first opening 24 is formed above the first opening 24 by a lithography technique (for example, exposure, development, baking, etc.).

次に、図３に示すように、「第２開口部の形成」工程Ｓ４を行う。
この工程では、図５（４）に示すように、上記レジスト膜４１をエッチングマスクに用いて、上記第２絶縁膜２５に第２開口部２６を形成する。このとき、第２絶縁膜２５に埋め込まれた上記第１開口部２４も再び開口される。したがって、上記第２開口部２６の下部に連続して上記第１開口部２４が形成される。
なお、図面は、第２開口部２６を形成し、第１開口部２４を再び開口している途中の状態を示している。 Next, as shown in FIG. 3, a “second opening formation” step S <b> 4 is performed.
In this step, as shown in FIG. 5D, the second opening 26 is formed in the second insulating film 25 using the resist film 41 as an etching mask. At this time, the first opening 24 embedded in the second insulating film 25 is also opened again. Accordingly, the first opening 24 is formed continuously below the second opening 26.
The drawing shows a state in which the second opening 26 is formed and the first opening 24 is being opened again.

次に、図３に示すように、「バリア層・シード層の形成」工程Ｓ５を行う。
この工程では、図５（５）に示すように、上記第１、第２開口部２４、２６の内面および上記第２絶縁膜２５の表面にバリア層１５を形成する。
上記バリア層１５は、例えば、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜の少なくとも１種で形成される。例えば、絶縁膜２１との密着性をよくするためのチタン膜と、このチタン膜表面に形成されたタンタル膜もしくは窒化タンタル膜との積層膜で形成することもできる。この場合、タンタル膜、窒化タンタル膜が主としてバリア層の機能を有する。このバリア層の機能としては、絶縁膜２１中の酸素が後に形成される銅電極中に拡散して銅電極が酸化されるのを防止するとともに、後に形成される銅電極の銅が絶縁膜２１、半導体チップ１０等に拡散するのを防止する。
さらに、上記バリア層１５の表面にめっきのシード層（図示せず）を形成する。このシード層には、例えば銅を用いる。
上記密着層、バリア層１５、シード層等の成膜は、例えば化学気相成長（ＣＶＤ）法、スパッタ法等のステップカバレッジに優れた成膜方法で行うことが好ましい。 Next, as shown in FIG. 3, a “barrier layer / seed layer formation” step S5 is performed.
In this step, as shown in FIG. 5 (5), the barrier layer 15 is formed on the inner surfaces of the first and second openings 24 and 26 and the surface of the second insulating film 25.
The barrier layer 15 is formed of at least one of a titanium film, a titanium nitride film, a tantalum film, and a tantalum nitride film, for example. For example, it can be formed of a laminated film of a titanium film for improving adhesion to the insulating film 21 and a tantalum film or a tantalum nitride film formed on the surface of the titanium film. In this case, the tantalum film and the tantalum nitride film mainly function as a barrier layer. As a function of the barrier layer, oxygen in the insulating film 21 is prevented from diffusing into a copper electrode to be formed later to oxidize the copper electrode, and copper in the copper electrode to be formed later is used as the insulating film 21. The diffusion to the semiconductor chip 10 or the like is prevented.
Further, a plating seed layer (not shown) is formed on the surface of the barrier layer 15. For example, copper is used for the seed layer.
The adhesion layer, the barrier layer 15, the seed layer, and the like are preferably formed by a film formation method having excellent step coverage such as a chemical vapor deposition (CVD) method or a sputtering method.

次に、図３に示すように、「銅膜の形成」工程Ｓ６を行う。
この工程では、図５（６）に示すように、上記バリア層１５を介して上記第１、第２開口部２４、２６の内部が埋め込まれる銅膜１６を形成する。この銅膜１６は、例えば上記銅のシード層をめっき種として電解めっきにより形成する。ここでは、電解めっきを用いることができる。それは、各第２開口部２６において、めっき膜の膜厚にばらつきが生じてもかまわないからである。要するに、上記第１、第２開口部２４、２６の内部を完全に埋め込むことができればよい。もちろん、他の成膜方法によって、銅膜１６を形成することも可能である。 Next, as shown in FIG. 3, a “copper film formation” step S6 is performed.
In this step, as shown in FIG. 5 (6), the copper film 16 in which the insides of the first and second openings 24 and 26 are embedded via the barrier layer 15 is formed. The copper film 16 is formed, for example, by electrolytic plating using the copper seed layer as a plating seed. Here, electrolytic plating can be used. This is because the thickness of the plating film may vary in each second opening 26. In short, it is only necessary that the inside of the first and second openings 24 and 26 can be completely embedded. Of course, the copper film 16 can also be formed by other film forming methods.

次に、図３に示すように、「平坦化」工程Ｓ７を行う。
この工程では、図６（７）に示すように、化学的機械研磨（ＣＭＰ）によって上記第２絶縁膜２５上の上記銅膜１６（シード層も含む）および上記バリア層１５を除去して、上記第１、第２開口部２４、２６内に上記バリア層１５を介して上記銅膜１６（上記銅のシード層も含む）からなる銅電極１３を形成する。
なお、図面は、銅膜１６を研磨していく途中の状態を示した。 Next, as shown in FIG. 3, a “flattening” step S7 is performed.
In this step, as shown in FIG. 6 (7), the copper film 16 (including the seed layer) and the barrier layer 15 on the second insulating film 25 are removed by chemical mechanical polishing (CMP). A copper electrode 13 made of the copper film 16 (including the copper seed layer) is formed in the first and second openings 24 and 26 via the barrier layer 15.
The drawing shows a state where the copper film 16 is being polished.

例えば上記銅膜１６のＣＭＰ条件は、一例として、研磨パッドに発泡ポリウレタン樹脂パッドを用い、スラリーに過酸化水素（Ｈ2 Ｏ2 ）が添加されたシリカ含有スラリーを用いる。また、研磨圧力を２１０ｇ／ｃｍ2 、研磨定盤の回転数を３０ｒｐｍ、研磨ヘッドの回転数を３０ｒｐｍ、スラリーの供給流量を２００ｃｃ／ｍｉｎ、研磨液の温度を２５℃〜３０℃に設定した。 For example, as the CMP conditions for the copper film 16, for example, a foamed polyurethane resin pad is used as a polishing pad and a silica-containing slurry to which hydrogen peroxide (H 2 O 2 ) is added is used as a slurry. The polishing pressure was set to 210 g / cm 2 , the polishing platen rotation speed was set to 30 rpm, the polishing head rotation speed was set to 30 rpm, the slurry supply flow rate was set to 200 cc / min, and the polishing liquid temperature was set to 25 ° C. to 30 ° C.

また、例えばタンタル膜、窒化チタン膜、窒化タンタル膜等からなるバリア層１５のＣＭＰ条件は、一例として、研磨パッドに発泡ポリウレタン樹脂パッドを用い、スラリーに過酸化水素（Ｈ2 Ｏ2 ）が添加されたシリカ含有スラリーを用い、研磨圧力を１４０ｇ／ｃｍ2 、研磨定盤の回転数を３０ｒｐｍ、研磨ヘッドの回転数を３０ｒｐｍ、スラリーの供給流量を２００ｃｃ／ｍｉｎ、研磨液の温度を２５℃〜３０℃に設定した。 For example, the CMP conditions of the barrier layer 15 made of, for example, a tantalum film, a titanium nitride film, a tantalum nitride film, etc., use a foamed polyurethane resin pad as the polishing pad and add hydrogen peroxide (H 2 O 2 ) to the slurry. Using the silica-containing slurry thus prepared, the polishing pressure was 140 g / cm 2 , the polishing plate rotation speed was 30 rpm, the polishing head rotation speed was 30 rpm, the slurry supply flow rate was 200 cc / min, and the polishing liquid temperature was 25 ° C. Set to 30 ° C.

このようにして、図６（８）に示すように、上記第１、第２開口部２４、２６内に銅電極１３が形成されるので、銅電極１３表面を含む上記第２絶縁膜２５表面は平坦化されるため、各銅電極１３の高さを均一にすることができる。すなわち、各銅電極１３の高さは銅膜１６（前記図５（６）、図６（７）等を参照）を形成するめっき膜厚のばらつきの影響を受けない。また銅電極１３は、ＣＭＰ時のディッシング等の影響を受けたとしても、高さ数十ｎｍの範囲でのばらつきに抑えることが可能であり、従来のようなμｍ単位のばらつきにはならない。したがって、銅電極１３の高さばらつきの大幅な改善が得られる。   In this way, as shown in FIG. 6 (8), since the copper electrode 13 is formed in the first and second openings 24 and 26, the surface of the second insulating film 25 including the surface of the copper electrode 13 Is flattened, the height of each copper electrode 13 can be made uniform. That is, the height of each copper electrode 13 is not affected by variations in the plating film thickness for forming the copper film 16 (see FIGS. 5 (6), 6 (7), etc.). Further, even if the copper electrode 13 is affected by dishing or the like during CMP, it can be suppressed to variations within a range of several tens of nanometers in height. Accordingly, a significant improvement in the height variation of the copper electrode 13 can be obtained.

次に、図３に示すように、「第２絶縁膜の除去」工程Ｓ８を行う。
この工程では、上記図６（８）に示すように、第２絶縁膜２５を除去する。第２絶縁膜２５が酸化シリコン膜の場合、フッ酸系薬液を使用し、ウエットエッチングにより除去する。その場合、第１絶縁膜２１の窒化シリコン膜２３がエッチングストッパ膜となる。
なお、図面は、第２絶縁膜２５をエッチングする直前の状態を示した。 Next, as shown in FIG. 3, a “removal of the second insulating film” step S8 is performed.
In this step, as shown in FIG. 6 (8), the second insulating film 25 is removed. When the second insulating film 25 is a silicon oxide film, a hydrofluoric acid chemical solution is used and removed by wet etching. In that case, the silicon nitride film 23 of the first insulating film 21 becomes an etching stopper film.
The drawing shows a state immediately before the second insulating film 25 is etched.

次に、図３に示すように、「無電解めっきによって金属接続層の形成」工程Ｓ９を行う。
この工程では、図６（９）に示すように、上記銅電極１３の銅を無電解めっき（例えば置換めっき、もしくは化学めっき）によって、上記銅電極１３の上層部に金属接続層１４を形成する。
上記金属接続層１４は、スズ、金、ニッケルのいずれかで形成する。
なお、金（Ａｕ）、ニッケル（Ｎｉ）を形成する場合、さらに、上記銅電極１３の表面の酸化防止のために、めっき液中に防食剤もしくは酸化防止剤を添加しても良い。
また、上記金属接続層１４は、無電解めっきによって、スズ鉛合金、スズ銀合金等のはんだで形成することもできる。
以上のようにして、各電極パッド１１上に接続するバンプ１２が形成される。 Next, as shown in FIG. 3, a “metal connection layer formation by electroless plating” step S9 is performed.
In this step, as shown in FIG. 6 (9), a metal connection layer 14 is formed on the upper layer of the copper electrode 13 by electroless plating (for example, displacement plating or chemical plating) of the copper electrode 13. .
The metal connection layer 14 is made of tin, gold, or nickel.
When gold (Au) or nickel (Ni) is formed, an anticorrosive or antioxidant may be added to the plating solution to prevent oxidation of the surface of the copper electrode 13.
Further, the metal connection layer 14 can also be formed with a solder such as a tin lead alloy or a tin silver alloy by electroless plating.
As described above, bumps 12 connected to each electrode pad 11 are formed.

以上のプロセスを行うことによって、図３に示す「バンプの完成により終了」工程Ｓ１０によって、上記バンプ形成プロセスが終了する。   By performing the above process, the above bump forming process is completed in the “finished upon completion of bump” step S10 shown in FIG.

さらに、上記の製造工程により形成したバンプを有する半導体装置同士を、例えば前記図２によって説明したように、フリップチップ接続することで、チップオンチップ（ＣｏＣ）構造が完成となる。   Furthermore, the chip-on-chip (CoC) structure is completed by flip-chip connecting the semiconductor devices having bumps formed by the above manufacturing process, as described with reference to FIG.

本発明の半導体装置の製造方法では、第１、第２開口部２４、２６内を埋め込むように銅膜１６を形成した後、化学的機械研磨によって第２絶縁膜２６上の銅膜１６およびバリア層１５を除去する。これによって、第１、第２開口部２４、２６内にバリア層１５を介して銅膜１６からなる銅電極１３が形成される。したがって、各銅電極１３は、第１、第２開口部２４、２６部内を満たすように、表面が平坦な、均一な高さに形成される。
また、無電解めっきによって、各銅電極１３の上層部に金属接続層１４を形成しているため、金属接続層は均一な厚さに形成される。通常、無電解めっきは、電解めっきのように電流密度の差が生じることがないので、めっき成長が、半導体チップ１０の全域において均一になる。 In the method of manufacturing a semiconductor device according to the present invention, after the copper film 16 is formed so as to fill the first and second openings 24 and 26, the copper film 16 and the barrier on the second insulating film 26 are formed by chemical mechanical polishing. Layer 15 is removed. As a result, the copper electrode 13 made of the copper film 16 is formed in the first and second openings 24 and 26 via the barrier layer 15. Accordingly, each copper electrode 13 is formed to have a flat and uniform height so as to fill the first and second openings 24 and 26.
Moreover, since the metal connection layer 14 is formed in the upper layer part of each copper electrode 13 by electroless plating, the metal connection layer is formed in a uniform thickness. Normally, electroless plating does not cause a difference in current density unlike electrolytic plating, so that plating growth is uniform over the entire area of the semiconductor chip 10.

また、上記金属接続層１４を上記はんだやスズで形成した場合に、金属接続層１４を形成した後にリフロー処理しても、バリア層１５によって金属接続層１４の流れ出しが抑えられるので、金属接続層１４を含む各バンプ１２の高さは、同等な高さに維持される。これは、上記バリア層１５に対して、はんだやスズの濡れ性がよくないため、リフロー時に外側に流れ出そうとするはんだやスズがバリア層１５によって流れ出すのを阻止されるためである。
したがって、銅電極１３および金属接続層１４で形成される複数のバンプ１２は、高さが同等なものに形成される。 Further, when the metal connection layer 14 is formed of the solder or tin, even if the metal connection layer 14 is formed and the reflow process is performed, the barrier layer 15 prevents the metal connection layer 14 from flowing out. The height of each bump 12 including 14 is maintained at an equivalent height. This is because the solder and tin wettability with respect to the barrier layer 15 is not good, and the barrier layer 15 prevents the solder and tin from flowing out during reflow.
Therefore, the plurality of bumps 12 formed by the copper electrode 13 and the metal connection layer 14 are formed to have the same height.

上記のように全バンプ１２の高さが同等に形成されるため、本発明の製造方法により形成された別の半導体装置のバンプとフリップチップ接続させた場合に、全てのバンプで確実に接続できるので、接続不良が発生しなくなるという利点がある。
よって、フリップチップ接続における歩留まりの向上、信頼性の向上が図れる半導体装置を製造できる。 Since all the bumps 12 are formed with the same height as described above, all bumps can be reliably connected when flip-chip connected to bumps of another semiconductor device formed by the manufacturing method of the present invention. Therefore, there is an advantage that connection failure does not occur.
Therefore, it is possible to manufacture a semiconductor device that can improve yield and reliability in flip-chip connection.

また、従来技術ではウエットエッチングによりシード層を除去していたため、バンプの下部に形成されているシード層がサイドエッチングされることになる。一方、上記半導体装置１の製造方法では、ＣＭＰ技術により、第２絶縁膜２６上のシード層を銅膜１６とともに除去するため、バンプ１２の下部のシード層はエッチングされない。
特に、上記従来技術のサイドエッチングの問題から、従来技術では数十μｍ以下の微細バンプの形成が困難であった。しかしながら、本発明では、現状技術の流用でサブミクロンオーダー、またはそれ以下の径のバンプ１２の形成が可能となる。 Further, since the seed layer is removed by wet etching in the conventional technique, the seed layer formed under the bump is side-etched. On the other hand, in the method for manufacturing the semiconductor device 1, the seed layer on the second insulating film 26 is removed together with the copper film 16 by the CMP technique, so the seed layer below the bump 12 is not etched.
In particular, due to the problem of side etching in the prior art, it has been difficult to form fine bumps of several tens of μm or less in the prior art. However, in the present invention, it is possible to form bumps 12 having a diameter of submicron order or less by utilizing the state of the art.

本発明の半導体装置に係る一実施の形態を示したバンプの要部平面図およびバンプおよびその周辺部の縦断面図である。It is the principal part top view of the bump which showed one Embodiment concerning the semiconductor device of this invention, and the longitudinal cross-sectional view of a bump and its peripheral part. 本発明の半導体装置のフリップチップ接続の一例を示した概略構成断面図である。1 is a schematic cross-sectional view showing an example of flip-chip connection of a semiconductor device of the present invention. 本発明の半導体装置の製造方法に係る一実施の形態を示したフローチャートである。3 is a flowchart showing an embodiment of the method for manufacturing a semiconductor device of the present invention. 本発明の半導体装置の製造方法に係る一実施の形態を示したバンプおよびその周辺部の製造工程断面図である。It is manufacturing process sectional drawing of the bump which showed one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention, and its peripheral part. 本発明の半導体装置の製造方法に係る一実施の形態を示したバンプおよびその周辺部の製造工程断面図である。It is manufacturing process sectional drawing of the bump which showed one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention, and its peripheral part. 本発明の半導体装置の製造方法に係る一実施の形態を示したバンプおよびその周辺部の製造工程断面図である。It is manufacturing process sectional drawing of the bump which showed one Embodiment which concerns on the manufacturing method of the semiconductor device of this invention, and its peripheral part. 従来のチップオンチップ接続の一例を示した概略構成断面図である。It is schematic structure sectional drawing which showed an example of the conventional chip-on-chip connection.

符号の説明Explanation of symbols

１…半導体装置、１０…半導体チップ、１０Ｓ…半導体チップの主面、１１…電極パッド、１２…バンプ、１３…銅電極、１４…金属接続層、１５…バリア層、２１…絶縁膜、２４…開口部   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Semiconductor chip, 10S ... Main surface of semiconductor chip, 11 ... Electrode pad, 12 ... Bump, 13 ... Copper electrode, 14 ... Metal connection layer, 15 ... Barrier layer, 21 ... Insulating film, 24 ... Aperture

Claims (6)

半導体チップと、
前記半導体チップの主面に形成された複数の電極パッドと、
前記半導体チップの主面に形成されていて前記各電極パッドを被覆する絶縁膜と、
前記各電極パッド上の前記絶縁膜に形成された開口部と、
前記絶縁膜上に前記各開口部を通じて前記各電極パッドに接続されたバンプを有し、
前記バンプは、
前記開口部内に埋め込まれるとともに外周部が前記絶縁膜上に形成された銅電極と、
前記銅電極上面に形成された金属接続層と、
前記銅電極の側部から前記開口部の側壁を含む内面にかけて連続的に形成されたバリア層を有し、
前記各銅電極は同等の高さに形成され、
前記各金属接続層は同等の厚さに形成されている
半導体装置。 A semiconductor chip;
A plurality of electrode pads formed on the main surface of the semiconductor chip;
An insulating film formed on the main surface of the semiconductor chip and covering the electrode pads;
An opening formed in the insulating film on each electrode pad;
Bumps connected to the electrode pads through the openings on the insulating film,
The bump is
A copper electrode embedded in the opening and having an outer peripheral portion formed on the insulating film;
A metal connection layer formed on the upper surface of the copper electrode;
Has a barrier layer which is continuously formed from the side of the copper electrode over the inner surface including a side wall of said opening,
Each copper electrode is formed to an equivalent height,
Each said metal connection layer is formed in the equivalent thickness. Semiconductor device. 前記バリア層は、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜の少なくとも１種で形成されている
請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the barrier layer is formed of at least one of a titanium film, a titanium nitride film, a tantalum film, and a tantalum nitride film. 前記金属接続層は、スズ、金、ニッケルのいずれかで形成されている
請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the metal connection layer is formed of any one of tin, gold, and nickel. 半導体チップの主面に複数の電極パッドを形成する工程と、
前記半導体チップの主面に前記各電極パッドを被覆する第１絶縁膜を形成する工程と、
前記電極パッド上の前記第１絶縁膜に第１開口部を形成する工程と、
前記第１絶縁膜の表面に前記各第１開口部が埋め込まれる第２絶縁膜を形成する工程と、
前記電極パッド上の前記第２絶縁膜に前記第１開口部よりも大きい第２開口部を形成し、該第２開口部の下部に連続する前記第１開口部を再び開口する工程と、
前記第１、第２開口部の側壁を含む内面および前記第２絶縁膜の表面にバリア層を形成する工程と、
前記バリア層を介して前記第１、第２開口部の内部が埋め込まれる銅膜を形成する工程と、
化学的機械研磨によって前記第２絶縁膜上の前記銅膜および前記バリア層を除去して、前記第１、第２開口部内に前記バリア層を介して前記銅膜からなる銅電極を形成する工程と、
前記第２絶縁膜を除去する工程と、
無電解めっきによって前記銅電極上に金属接続層を形成する工程を有する
半導体装置の製造方法。 Forming a plurality of electrode pads on the main surface of the semiconductor chip;
Forming a first insulating film covering each electrode pad on the main surface of the semiconductor chip;
Forming a first opening in the first insulating film on the electrode pad;
Forming a second insulating film in which each of the first openings is embedded in a surface of the first insulating film;
Forming a second opening larger than the first opening in the second insulating film on the electrode pad, and reopening the first opening continuous to the lower portion of the second opening;
Forming a barrier layer on the inner surface including the side walls of the first and second openings and the surface of the second insulating film;
Forming a copper film in which the inside of the first and second openings is embedded via the barrier layer;
Removing the copper film and the barrier layer on the second insulating film by chemical mechanical polishing to form a copper electrode made of the copper film in the first and second openings via the barrier layer; When,
Removing the second insulating film;
A method for manufacturing a semiconductor device, comprising: forming a metal connection layer on the copper electrode by electroless plating. 前記バリア層は、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜の少なくとも
１種で形成する
請求項４記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4, wherein the barrier layer is formed of at least one of a titanium film, a titanium nitride film, a tantalum film, and a tantalum nitride film. 前記金属接続層は、スズ、金、ニッケルのいずれかで形成する
請求項４記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4, wherein the metal connection layer is formed of any one of tin, gold, and nickel.
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