CN100592479C - 具有最优化应力效应的双沟槽的晶体管结构及其形成方法 - Google Patents

具有最优化应力效应的双沟槽的晶体管结构及其形成方法 Download PDF

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Publication number
CN100592479C
CN100592479C CN200580034575A CN200580034575A CN100592479C CN 100592479 C CN100592479 C CN 100592479C CN 200580034575 A CN200580034575 A CN 200580034575A CN 200580034575 A CN200580034575 A CN 200580034575A CN 100592479 C CN100592479 C CN 100592479C
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China
Prior art keywords
stress
semiconductor
feature
transistor structure
transistor
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Expired - Fee Related
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CN200580034575A
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English (en)
Chinese (zh)
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CN101124668A (zh
Inventor
陈建
迈克尔·D·特纳
詹姆斯·E·瓦谢克
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
CN200580034575A 2004-10-29 2005-10-25 具有最优化应力效应的双沟槽的晶体管结构及其形成方法 Expired - Fee Related CN100592479C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/977,266 US7276406B2 (en) 2004-10-29 2004-10-29 Transistor structure with dual trench for optimized stress effect and method therefor
US10/977,266 2004-10-29

Publications (2)

Publication Number Publication Date
CN101124668A CN101124668A (zh) 2008-02-13
CN100592479C true CN100592479C (zh) 2010-02-24

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CN200580034575A Expired - Fee Related CN100592479C (zh) 2004-10-29 2005-10-25 具有最优化应力效应的双沟槽的晶体管结构及其形成方法

Country Status (6)

Country Link
US (1) US7276406B2 (enExample)
JP (1) JP2008519434A (enExample)
KR (1) KR20070069184A (enExample)
CN (1) CN100592479C (enExample)
TW (1) TWI433264B (enExample)
WO (1) WO2006050051A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7670895B2 (en) 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US7491622B2 (en) 2006-04-24 2009-02-17 Freescale Semiconductor, Inc. Process of forming an electronic device including a layer formed using an inductively coupled plasma
US7528078B2 (en) 2006-05-12 2009-05-05 Freescale Semiconductor, Inc. Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
JP2007329295A (ja) * 2006-06-08 2007-12-20 Hitachi Ltd 半導体及びその製造方法
DE102006046377A1 (de) * 2006-09-29 2008-04-03 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Isoliergräben, die unterschiedliche Arten an Verformung hervorrufen
WO2008042144A2 (en) * 2006-09-29 2008-04-10 Advanced Micro Devices, Inc. A semiconductor device comprising isolation trenches inducing different types of strain
US7829407B2 (en) 2006-11-20 2010-11-09 International Business Machines Corporation Method of fabricating a stressed MOSFET by bending SOI region
US7737498B2 (en) * 2008-05-07 2010-06-15 International Business Machines Corporation Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices
US8084822B2 (en) * 2009-09-30 2011-12-27 International Business Machines Corporation Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices
US20110084324A1 (en) * 2009-10-09 2011-04-14 Texas Instruments Incorporated Radiation hardened mos devices and methods of fabrication
US8815671B2 (en) 2010-09-28 2014-08-26 International Business Machines Corporation Use of contacts to create differential stresses on devices
US8460981B2 (en) 2010-09-28 2013-06-11 International Business Machines Corporation Use of contacts to create differential stresses on devices
CN102446971A (zh) * 2011-09-08 2012-05-09 上海华力微电子有限公司 一种提高晶体管载流子迁移率的pmos结构
TWI565070B (zh) * 2013-04-01 2017-01-01 旺宏電子股份有限公司 半導體結構
US10801833B2 (en) * 2018-04-09 2020-10-13 The Boeing Company Strain sensitive surfaces for aircraft structural analysis and health monitoring
CN114496903A (zh) * 2022-02-10 2022-05-13 广东省大湾区集成电路与系统应用研究院 一种半导体结构及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482715B2 (en) * 2000-12-16 2002-11-19 Samsung Electronics Co., Ltd. Method of forming shallow trench isolation layer in semiconductor device
CN1469443A (zh) * 2002-06-27 2004-01-21 �뵼��Ԫ����ҵ�������ι�˾ 给出具有高沟道密度的半导体器件的低成本方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691230A (en) * 1996-09-04 1997-11-25 Micron Technology, Inc. Technique for producing small islands of silicon on insulator
US6524929B1 (en) * 2001-02-26 2003-02-25 Advanced Micro Devices, Inc. Method for shallow trench isolation using passivation material for trench bottom liner

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482715B2 (en) * 2000-12-16 2002-11-19 Samsung Electronics Co., Ltd. Method of forming shallow trench isolation layer in semiconductor device
CN1469443A (zh) * 2002-06-27 2004-01-21 �뵼��Ԫ����ҵ�������ι�˾ 给出具有高沟道密度的半导体器件的低成本方法

Also Published As

Publication number Publication date
TW200627582A (en) 2006-08-01
CN101124668A (zh) 2008-02-13
WO2006050051A2 (en) 2006-05-11
US7276406B2 (en) 2007-10-02
WO2006050051A3 (en) 2007-04-26
JP2008519434A (ja) 2008-06-05
KR20070069184A (ko) 2007-07-02
TWI433264B (zh) 2014-04-01
US20060091461A1 (en) 2006-05-04

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