Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
  • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
  • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
  • H01L21/0274—Photolithographic processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/40—Crystalline structures
  • H10D62/405—Orientations of crystalline planes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0167—Manufacturing their channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0188—Manufacturing their isolation regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• the present disclosures relate generally to semiconductor devices, and more particularly, to a transistor structure and method of making a transistor structure with dual trench for optimized stress effect on a ⁇ 100> SOI substrate.
• FIG. 1 is a top view of a CMOS transistor 10 illustrating a channel direction and width direction as is known in the art.
• CMOS transistor 10 includes an active region 12 and a gate electrode 14, with an underlying gate dielectric (not shown).
• Active region 12 is characterized by a width dimension W extending in a width direction, the width direction being indicated by reference numeral 16.
• active region 12 comprises any suitable semiconductor material.
• Gate electrode 14 is characterized by a length dimension L extending in a channel direction, the channel direction being indicated by reference numeral 18.
• a method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate.
• a first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film.
• a second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench.
• the presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a ⁇ 100> or ⁇ 110> semiconductor-on-insulator substrate.
• Figure 1 is a top view of a CMOS transistor illustrating a channel direction and width direction as is known in the art
• Figure 2 is a table view of stress response characteristics for various channel orientations and device types
• Figures 3-7 are cross-sectional views of a semiconductor device manufactured using a dual trench process for optimizing stress effect according to one embodiment of the present disclosure
• Figure 8 is a flow diagram view of a dual trench process for optimizing stress effect according to one embodiment of the present disclosure
• Figure 9 is a top view of semiconductor device structure, including a CMOS transistor structure with a controlled stress feature in a width direction manufactured using a dual trench process according to one embodiment of the present disclosure
• Figure 10 is a top view of semiconductor device structure, including a CMOS transistor structure with a controlled stress feature in a width direction manufactured using a dual trench process according to another embodiment of the present disclosure
• Figure 11 is a top view of semiconductor device structure, including a CMOS transistor structure with a controlled stress feature in a width direction manufactured using a dual trench process according to yet another embodiment of the present disclosure.
• Figure 12 is a top view of semiconductor device structure, including a CMOS transistor structure with a controlled stress feature in a width direction manufactured using a dual trench process according to still another embodiment of the present disclosure.
• the embodiments of the present disclosure provide a solution to put differential stress on different devices (N-type and P-type) and different orientations (width direction or length direction) to optimize and maximize the stress benefits of a ⁇ 100> SOI substrate.
• the embodiments of the present disclosure make use of trench isolation and a corresponding nitride deposition in selective areas to address a dual (248nm/193nm) photo process and differential stress effects, as discussed herein.
• a dual trench process for SOI comprises forming a nitride layer at the bottom of a desired trench area to prevent trench liner induced compressive stress and thus enabling differential stress on a specific device and orientation.
• this method also enables a 248nm and 193nm dual trench photo process by providing for an optimized reflectivity for both wavelengths.
• Figure 2 is a table view of stress response sensitivity characteristics for various channel orientations and device types.
• the table is based on short channel device behavior.
• the table 20 of Figure 2 includes columns of channel orientation 22, device type 24, favorable channel stress 26, and favorable width stress 28.
• an NMOS device performs best under tensile stress in the channel direction.
• the NMOS device performance has a relatively small sensitivity to stress in width direction.
• a PMOS device performs best under compressive stress in the channel direction and under tensile stress in width direction.
• an NMOS device performs best under tensile stress in the channel direction and has a relatively small sensitivity to stress in width direction.
• a PMOS device performance demonstrates a relatively small sensitivity to stress in the channel direction and does respond favorably to small compressive stress in the width direction.
• FIGS 3-7 are cross-sectional views of a semiconductor device manufactured using a dual trench process for optimizing stress effects according to one embodiment of the present disclosure.
• semiconductor device 30 includes a semiconductor-on insulator- substrate, for example, a ⁇ 100> SOI substrate as is known in the art.
• the SOI substrate includes a silicon substrate (not shown), a buried oxide (BOX) 32 overlying the silicon substrate, and silicon layer 34 overlying the BOX 32.
• Overlying silicon layer 34 is a thermal oxide 36, for example, a pad oxide.
• Overlying pad oxide 36 is a silicon nitride layer 38.
• the BOX 32 has a thickness on the order of 1350 - 2000 angstroms and the silicon layer 34 has a thickness on the order of 700 - 1100 angstroms.
• Pad oxide 36 has a thickness on the order of 90-150 angstroms.
• silicon nitride layer 38 has a thickness on the order of 1000 - 1200 angstroms. In one embodiment, the silicon nitride layer 38 has a thickness in the range of 1050 - 1160 angstroms.
• a first trench etch is performed to form first trench 40.
• a first photo process is used, hi one embodiment, the first photo process includes, for example, a 248 nm DUV (deep ultra violet) patterning process.
• an etch step is carried out to form the first trench 40.
• a stressor/anti-reflective coating (ARC) film deposition is performed subsequent to the first trench etch.
• Forming the stressor/ARC film 42 includes selectively depositing a dual use film. That is, the stressor/ARC film can comprise any suitable film that can perform the dual use of 1) a stressor and 2) an ARC film.
• the stressor/ARC film comprises, for example, a nitride.
• selective deposition of the stressor/ARC film 42 includes depositing the film over the exposed portions of silicon nitride layer 38 and a bottom of the first trench 40.
• a possible alternative is to form sidewall spacers in opening 40 as a diffusion barrier instead of deposited layer 42. In such case, it may also be beneficial to extend opening 40 into BOX layer 32 before forming the sidewall spacers, wherein the sidewall spacers block the silicon/BOX interface.
• a second trench etch is performed to form second trench 44.
• a second photo process is used, hi one embodiment, the second photo process includes, for example, a 193 nm DUV (deep ultra violet) patterning process.
• an etch step is carried out to form the second trench 44.
• the bottom of the second trench is free of any stressor/ARC film.
• trench liners (46,48) are formed in respective first and second trenches
• Trench liners (46,48) include thermally grown liners for driving out defects, and for protecting top corners of the silicon in respective trenches.
• trench liner 46 extends from a top of the silicon 34 within the second trench and completely down to the buried oxide 32.
• the trench liner 48 is prevented from growing on the silicon 34 within the first trench and completely down to the buried oxide 32. Accordingly, a portion of silicon 34 within the first trench 40 remains protected by the stressor/ARC film 42.
• Figure 8 is a flow diagram view 50 of a dual trench process for optimizing stress effect according to one embodiment of the present disclosure.
• Initial processing takes place in step indicated by reference numeral 52.
• a first trench photo is performed, as discussed herein above with reference to Figure 4.
• a first trench etch is carried out to form a first trench, further as discussed herein above with reference to Figure 4.
• a selective dual use (stressor/ ARC) film deposition is carried out, for example, as discussed herein above with reference to Figure 5.
• a second trench photo is performed, as discussed herein above with reference to Figure 6.
• a second trench etch is carried out to form a second trench, further as discussed herein above with reference to Figure 6.
• continued processing is carried out according to the particular requirements of the semiconductor device to be manufactured. For example, continued processing could include formation of trench liners as discussed herein above with reference to Figure 7.
• Figure 9 is a top view of semiconductor device structure 70, including CMOS transistor structures 72 and 74, wherein structure 72 includes a controlled stress feature in a width direction manufactured using a dual trench process according to one embodiment of the present disclosure as discussed herein above.
• CMOS transistor structures 72 and 74 represent a PFET device and an NFET device, respectively.
• CMOS transistor structures 72 and 74 include active semiconductor regions 76 and 78, respectively.
• the active semiconductor regions comprise silicon.
• optimization of PFET CMOS transistor 76 includes the addition of a first stress modifier feature indicated by reference numeral 80 and second stress modifier and capacitive reduction features (82,84), wherein the features provide a modification of stresses in the width direction.
• the first stress modifier feature comprises a dual use stressor/ARC film external to active semiconductor region 76.
• formation of the first stress modifier feature 80 is accomplished via the first trench etch and stressor/ARC file deposition as discussed earlier herein with reference to Figure 5.
• the first stress modifier feature includes nitride.
• stress modifier and capacitive reduction features (82,84) are internal to the active semiconductor area 76, extending between source and drain regions of active area 76. Portions of active area 76 underlie a gate electrode 86 and an associated gate dielectric (not shown). A portion of the stress modifier and capacitive reduction features (82,84) also underlie the gate electrode 86 and associated gate dielectric (not shown). Gate electrode 86 is characterized by a length dimension L extending in a channel direction.
• stress modifier and capacitive reduction features (82,84) are formed subsequent to removal of active semiconductor material by the second trench etch, as discussed earlier herein, further as discussed herein above with reference to Figures 6 and 7.
• Stress modifier and capacitive reduction features are further characterized by an absence of the dual use stressor/ ARC film lining a bottom of a respective trench, further wherein a trench sidewall liner of the respective trenches extends fully within the respective trench, from a top of the active layer material down to an underlying buried oxide.
• each further includes a trench fill material.
• the particular trench fill material is selected according to a desired additional stress modification for a particular transistor application, with respect to either compressive or tensile stress modification.
• the trench fill material includes oxide for providing a compressive stress modification
• the trench fill material includes a nitride for providing a tensile stress modification.
• PFET CMOS transistor 72 further includes contacts
• Figure 9 further illustrates PFET CMOS transistor 72 with a notch 89 according to another embodiment of the present disclosure. That is, PFET CMOS transistor 72 includes a notch 89 in active region 76. Notch 89 is disposed at one end of active region 76, wherein the notch spans across a portion of the channel region of PFET CMOS transistor 72. With its presence, notch 89 reduces a total width dimension of the active region 76 for addressing various chip functionality issues and/or problems as may be required for a given CMOS transistor application.
• Figure 9 still further illustrates a top view of NFET CMOS transistor 74, wherein transistor 74 includes an active region 78 that underlies a gate electrode 90 and an associated gate dielectric (not shown). Active region 78 is characterized by a width dimension W extending in a width direction and comprises semiconductor material. Gate electrode 90 is characterized by a length dimension L extending in a channel direction. Transistor 74 also includes contacts 92 for making contact with source and drain regions, 91 and 93, respectively of active semiconductor region 78. Note that active region 78 is also surrounded by the first stress modifier feature 80 that is comprised of a dual use stressor/ ARC film. Formation of the first stress modifier feature 80 surrounding active region 78 is accomplished during the first trench etch and stressor/ ARC file deposition as discussed earlier herein with reference to Figure 5.
• Figure 10 is a top view of semiconductor device structure 100, including CMOS transistor structures 72 and 74, wherein structure 72 includes a controlled stress feature in a width direction manufactured using a dual trench process according to another embodiment of the present disclosure as discussed herein above.
• structure 72 further includes third stress modifier and capacitive reduction features 102, wherein the features provide a further modification of stresses in the width direction of structure 72.
• Third stress modifier and capacitive reduction features 102 are disposed at opposite ends of active area 76, and more particularly, along the edges of the active area that extend in the channel direction.
• the third stress modifier and capacitive reduction features 102 are formed subsequent to removal of active semiconductor material by the second trench etch, as discussed earlier herein with reference to Figures 6 and 7.
• Stress modifier and capacitive reduction features 102 are further characterized by an absence of the dual use stressor/ARC film lining a bottom of a respective trench, further wherein a trench sidewall liner of the respective trenches extends fully within the respective trench, from a top of the active layer material down to an underlying buried oxide.
• each also includes a trench fill material.
• the particular trench fill material is selected according to a desired additional stress modification for a particular transistor application, with respect to either compressive or tensile stress modification.
• the trench fill material includes oxide for providing a compressive stress modification.
• the trench fill material includes a nitride for providing a tensile stress modification.
• Figure 11 is a top view of semiconductor device structure 110, including CMOS transistor structures 72 and 74, wherein structure 72 includes a controlled stress feature in a width direction manufactured using a dual trench process according to yet another embodiment of the present disclosure.
• structure 72 further includes alternate stress modifier and capacitive reduction features (112,114), wherein the features provide a further modification of stresses in the width direction of structure 72.
• Stress modifier and capacitive reduction features (112,114) are disposed across active area 76, and more particularly, fully across the active area and extending in the channel direction. Coupling portions of the active area that are separated by the stress modifier and capacitive reduction features (112,114) can be accomplished using an overlying metallization, for example, a metallization on the contact level or an overlying metal interconnect level.
• stress modifier and capacitive reduction features (112,114) are formed subsequent to removal of active semiconductor material by the second trench etch, as discussed earlier herein with reference to Figures 6 and 7.
• Stress modifier and capacitive reduction features (112,114) are further characterized by an absence of the dual use stressor/ARC film lining a bottom of a respective trench, further wherein a trench sidewall liner of the respective trenches extends fully within the respective trench, from a top of the active layer material down to an underlying buried oxide.
• each also includes a trench fill material.
• the particular trench fill material is selected according to a desired additional stress modification for a particular transistor application, with respect to either compressive or tensile stress modification.
• the trench fill material includes oxide for providing a compressive stress modification
• the trench fill material includes a nitride for providing a tensile stress modification.
• Figure 12 is a top view of semiconductor device structure 116, including CMOS transistor structures 118 and 120 with a controlled stress feature in a channel direction manufactured using a dual trench process according to still another embodiment of the present disclosure.
• the embodiment of Figure 12 is similar to the embodiment discussed herein above with respect to Figure 9 with the following differences as discussed below.
• the starting substrate comprising a ⁇ 110> SOI substrate
• a more compressive stress is desired to provide favorable channel stress.
• stress modifier and capacitive reduction features 122 are formed subsequent to removal of active semiconductor material by the second trench etch, as discussed earlier herein, with reference to Figures 6 and 7.
• Stress modifier and capacitive reduction features 122 are further characterized by an absence of the dual use stressor/ARC film lining a bottom of a respective trench, further wherein a trench sidewall liner of the respective trenches extends fully within the respective trench, from a top of the active layer material down to an underlying buried oxide.
• stress modifier and capacitive reduction features 122 for the channel direction are contained within respective portions of the source/drain regions of the active area 76 alone, without extending fully across the channel region nor underlying gate electrode 86 and an associated gate dielectric (not shown).
• the particular trench fill material is selected according to a desired additional stress modification for a particular transistor application, with respect to either compressive or tensile stress modification.
• the trench fill material includes oxide for providing a compressive stress modification.
• the trench fill material includes a nitride for providing a tensile stress modification.
• the method includes using a selective nitride deposition in a dual trench process.
• the selective nitride deposition not only enables the dual (248nm/193nm) dual photo process, but also provides differential stress on NFET and PFET devices and on width and channel directions to obtain a maximized stress effect on a ⁇ 100> crystal orientation SOI substrate. That is, the nitride deposition step enables the 248nm/193nm dual trench photo process and also provides a selective trench stress manipulation.
• the embodiments of present disclosure concurrently provide for addressing the different ARC requirements of both 248nm and 193nm photo processes while achieving an optimized stress effect at the same time.
• the dual trench approach e.g. a dual mask approach
• a dual trench approach enables providing an optimized stress (i.e., providing the most beneficial stresses) for both NFET and PFET devices concurrently in both width and channel directions. Accordingly, a performance improvement for the corresponding transistor structure on the order of approximately 5-7% is expected.
• a normal active area and trench patterning at the edge of the active area are patterned using a 248 nm mask and then etched.
• a thin nitride layer e.g., SiN
• SiN silicon
• one or more fully enclosed cutout patterns are patterned using a 193nm photo process.
• the PFET device alone is provided with high compressive stress in a width direction, hi addition, the NFET device (i.e., in both width and channel directions) and the PFET device (i.e., in a channel direction) will get less compressive or tensile stress, which is optimal for both the NFET and PFET devices.
• differential and optimized stress effect tailoring stress for specific devices on an SOI substrate, for example, , an ⁇ 100> SOI substrate.
• differential and optimized stress tailoring includes .providing more or less stress, tensile or compressive, to different areas and/or regions, as discussed herein.
• the embodiments of the present disclosure are applicable to SOI products requiring high performance and/or low dynamic power.
• the embodiments further provide method for obtaining a desired performance advantage that is simpler to implement than more complicated methods of using SiGe stressors or C-SiGe channels, etc.
• the disclosure has been described with reference to various embodiments.
• one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present embodiments as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present embodiments.
• the present embodiments can apply to semiconductor device technologies where carrier mobility is crucial to the device performance.

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• 2004
  • 2004-10-29 US US10/977,266 patent/US7276406B2/en not_active Expired - Fee Related
• 2005
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