CN100568199C - 管理多处理器操作 - Google Patents

管理多处理器操作 Download PDF

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Publication number
CN100568199C
CN100568199C CNB2005800406226A CN200580040622A CN100568199C CN 100568199 C CN100568199 C CN 100568199C CN B2005800406226 A CNB2005800406226 A CN B2005800406226A CN 200580040622 A CN200580040622 A CN 200580040622A CN 100568199 C CN100568199 C CN 100568199C
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CN
China
Prior art keywords
processor
line
shared memory
cache
cache line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CNB2005800406226A
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English (en)
Chinese (zh)
Other versions
CN101065736A (zh
Inventor
S·L·布林尼克
许育诚
L·米拉博
R·D·兰金
宋正中
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International Business Machines Corp
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International Business Machines Corp
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Publication of CN101065736A publication Critical patent/CN101065736A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Saccharide Compounds (AREA)
  • Hardware Redundancy (AREA)
CNB2005800406226A 2004-11-30 2005-11-11 管理多处理器操作 Expired - Fee Related CN100568199C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/001,476 US7418557B2 (en) 2004-11-30 2004-11-30 Managing multiprocessor operations
US11/001,476 2004-11-30

Publications (2)

Publication Number Publication Date
CN101065736A CN101065736A (zh) 2007-10-31
CN100568199C true CN100568199C (zh) 2009-12-09

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ID=35645753

Family Applications (1)

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CNB2005800406226A Expired - Fee Related CN100568199C (zh) 2004-11-30 2005-11-11 管理多处理器操作

Country Status (9)

Country Link
US (2) US7418557B2 (enExample)
EP (1) EP1839156B1 (enExample)
JP (1) JP4641545B2 (enExample)
CN (1) CN100568199C (enExample)
AT (1) ATE402444T1 (enExample)
DE (1) DE602005008477D1 (enExample)
IL (1) IL183470A (enExample)
MX (1) MX2007006350A (enExample)
WO (1) WO2006058826A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7536694B2 (en) * 2004-11-30 2009-05-19 International Business Machines Corporation Exception handling in a multiprocessor system
US7937709B2 (en) * 2004-12-29 2011-05-03 Intel Corporation Synchronizing multiple threads efficiently
JP2006227856A (ja) * 2005-02-17 2006-08-31 Hitachi Ltd アクセス制御装置及びそれに搭載されるインターフェース
US7818056B2 (en) * 2005-03-24 2010-10-19 Cardiac Pacemakers, Inc. Blending cardiac rhythm detection processes
JP4831599B2 (ja) * 2005-06-28 2011-12-07 ルネサスエレクトロニクス株式会社 処理装置
US7849362B2 (en) * 2005-12-09 2010-12-07 International Business Machines Corporation Method and system of coherent design verification of inter-cluster interactions
JP2007219571A (ja) * 2006-02-14 2007-08-30 Hitachi Ltd 記憶制御装置及びストレージシステム
WO2012014285A1 (ja) * 2010-07-27 2012-02-02 富士通株式会社 割込制御方法、マルチコアプロセッサシステム、および割込制御プログラム
JP5745868B2 (ja) * 2011-01-18 2015-07-08 トヨタ自動車株式会社 マルチプロセッサシステム
JP5614419B2 (ja) 2012-02-29 2014-10-29 富士通株式会社 情報処理装置、制御方法および制御プログラム
WO2013159288A1 (en) * 2012-04-25 2013-10-31 Intel Corporation Method and system for maintaining release consistency in shared memory programming
US9135175B2 (en) * 2012-12-21 2015-09-15 Oracle International Corporation Distributed cache coherency directory with failure redundancy
CN103745315A (zh) * 2013-12-31 2014-04-23 太原理工大学 重点项目行政执法监察联动管理方法及系统
US10310982B2 (en) * 2016-12-15 2019-06-04 International Business Machines Corporation Target cache line arbitration within a processor cluster
US10339064B2 (en) * 2017-03-29 2019-07-02 International Business Machines Corporation Hot cache line arbitration
US10915445B2 (en) 2018-09-18 2021-02-09 Nvidia Corporation Coherent caching of data for high bandwidth scaling
CN114327920B (zh) * 2022-03-16 2022-06-21 长沙金维信息技术有限公司 用于多处理器系统的硬件资源共享方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1226705A (zh) * 1998-02-17 1999-08-25 国际商业机器公司 具有独立实现优化高速缓存操作的高速缓存相关协议
CN1231443A (zh) * 1998-02-17 1999-10-13 国际商业机器公司 垂直高速缓冲的伪精确i－高速缓存的包括性
US6751705B1 (en) * 2000-08-25 2004-06-15 Silicon Graphics, Inc. Cache line converter

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08202622A (ja) * 1995-01-31 1996-08-09 Fujitsu Ltd 分散型メモリ構成のキャッシュ制御方法
US5930821A (en) * 1997-05-12 1999-07-27 Integrated Device Technology, Inc. Method and apparatus for shared cache lines in split data/code caches
US6314526B1 (en) * 1998-07-10 2001-11-06 International Business Machines Corporation Resource group quorum scheme for highly scalable and highly available cluster system management
US6467050B1 (en) * 1998-09-14 2002-10-15 International Business Machines Corporation Method and apparatus for managing services within a cluster computer system
JP3676934B2 (ja) * 1998-12-15 2005-07-27 株式会社日立製作所 プロセッサおよびマルチプロセッサシステム
US6622260B1 (en) * 1999-12-30 2003-09-16 Suresh Marisetty System abstraction layer, processor abstraction layer, and operating system error handling
US6772298B2 (en) * 2000-12-20 2004-08-03 Intel Corporation Method and apparatus for invalidating a cache line without data return in a multi-node architecture
US6859866B2 (en) * 2001-10-01 2005-02-22 International Business Machines Corporation Synchronizing processing of commands invoked against duplexed coupling facility structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1226705A (zh) * 1998-02-17 1999-08-25 国际商业机器公司 具有独立实现优化高速缓存操作的高速缓存相关协议
CN1231443A (zh) * 1998-02-17 1999-10-13 国际商业机器公司 垂直高速缓冲的伪精确i－高速缓存的包括性
US6751705B1 (en) * 2000-08-25 2004-06-15 Silicon Graphics, Inc. Cache line converter

Also Published As

Publication number Publication date
US7650467B2 (en) 2010-01-19
US20080168238A1 (en) 2008-07-10
IL183470A0 (en) 2007-09-20
US20060117147A1 (en) 2006-06-01
IL183470A (en) 2011-03-31
WO2006058826A1 (en) 2006-06-08
ATE402444T1 (de) 2008-08-15
EP1839156A1 (en) 2007-10-03
DE602005008477D1 (de) 2008-09-04
CN101065736A (zh) 2007-10-31
EP1839156B1 (en) 2008-07-23
US7418557B2 (en) 2008-08-26
JP2008522264A (ja) 2008-06-26
MX2007006350A (es) 2007-06-19
JP4641545B2 (ja) 2011-03-02

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Granted publication date: 20091209

Termination date: 20181111