CN100550382C - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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CN100550382C
CN100550382C CNB2006101431378A CN200610143137A CN100550382C CN 100550382 C CN100550382 C CN 100550382C CN B2006101431378 A CNB2006101431378 A CN B2006101431378A CN 200610143137 A CN200610143137 A CN 200610143137A CN 100550382 C CN100550382 C CN 100550382C
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刘学锋
R·M·拉塞尔
金成东
D·D·库尔鲍
A·J·约瑟夫
L·D·兰泽若蒂
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Abstract

一种结构包括单晶片，具有在第一厚度的第一区域中形成的第一子集电极和在与第一厚度不同的第二厚度的第二区域中形成的第二子集电极。还旨在一种方法，该方法包括提供包括第一层的衬底并且在第一层中形成第一掺杂区域。该方法还包括在第一层上形成第二层并且在第二层中形成第二掺杂区域。第二掺杂区域以不同于第一掺杂区域的深度形成。该方法还包括在第一层中形成第一通孔并且在第二层中形成第二通孔以连接第一通孔到表面。

Description

半导体结构及其制造方法
技术领域
本发明一般涉及半导体结构及其制造方法，更具体地说涉及在毫米波范围内工作的芯片上PIN二极管以及其使用双外延工艺的制造方法。
背景技术
如毫米波器件(f＞30GHz)的高频应用要求多功能电路具有不同类型的器件用于最优化操作。例如，在先进的微波器件中，通信发射电路和雷达系统使用异质结双极晶体管(HBT)。但是，在此器件中，接收电路包括基于III-V族材料的场效应晶体管(FET)，如高电子迁移率晶体管(HEMT)，以最小化噪声指数并且因此提高了接收器灵敏度。如果所有的子系统功能都使用常规的器件工艺技术完成，以将所有相关的先进器件集成到相同的衬底上，会降低这样的多功能电路器件的性能。
在当前公知的制造工艺中，通过外延生长技术在高电阻或绝缘衬底上制造高速三接线端器件和如PIN二极管等的微波二极管。在一种常规工艺中，通过共享NPN C-B结构处理常规芯片上PIN二极管。然而，这引起了器件整体性能的问题。例如，使用单晶片技术的公知工艺不能为高性能NPN(二极管)器件提供薄膜集电极并且为高击穿电压器件提供厚膜集电极。
顺便说一个具体实例，已公知，在衬底的第一表面中注入第一导电率的HBT子集电极区域。然后在衬底的第一表面中注入第一导电率的PIN二极管区域并且与HBT子集电极区域隔开。下一步，在HBT子集电极区域和PIN二极管区域上的i层上选择生长第二导电率的HBT基极/PIN二极管层。然后，在HBT基极/PIN二极管层上选择生长第一导电率的HBT发射极层。然后通过用多晶硅填充在HBT子集电极区域和PIN二极管区域之间的边界处的深沟槽和浅沟槽制造隔离区域，其中深沟槽隔离区域延伸到衬底。下一步，在PIN二极管区域上蚀刻掉HBT发射极层，并且形成到HBT发射极层，HBT基极层，HBT子集电极区域，PIN二极管阳极区域和PIN二极管阴极区域的导电接触。从而，在单工艺中，在同一衬底上制造HBT和PIN二极管。
上述技术的目的是在器件之间使用公共的i层并且使用改进的工艺技术以使在没有损害器件的任何性能下在同一晶片上生长所有结构。虽然上面描述的工艺期望在单个衬底上制造每一个电路(即，消除对使用分离衬底然后在模块中连接衬底的需要)，但是仍存在一些限制。列举一个，例如，因为NPN性能的要求，PIN二极管i层不能自由地调整以获得期望的T/R开关速度。
发明内容
在本发明的第一方面中，一种结构包括单晶片，具有在第一厚度的第一区域中形成的第一子集电极和与第一厚度不同的第二厚度的第二区域中形成的第二子集电极。
在本发明的第二方面中，一种多电路结构，包括：在具有第一厚度的第一区域中形成的远侧子集电极和在第二区域中形成的近侧子集电极。第二子集电极区域的厚度小于第一区域的厚度。远侧子集电极形成高击穿电压器件并且近侧子集电极结构形成高性能NPN器件。
在本发明的另一方面中，一种形成结构的方法包括提供包括第一层的衬底并且在第一层中形成第一掺杂区域。该方法还包括在第一层上形成第二层并且在第二层中形成第二掺杂区域。第二掺杂区域以不同于第一掺杂区域的深度形成。
附图说明
图1-13根据本发明示出了用于形成图13中示出的最终结构的工艺步骤；
图14示出了本发明的示意性实施例，比较浓度与深度的曲线；
图15根据本发明示出了表1中示出的PIN二极管射频特性的代表曲线。
具体实施方式
本发明涉及半导体结构及制造方法。在一个实施例中，本发明更具体地说涉及在晶片上结合极高击穿和极高性能NPN(即双极)器件而不损害任一器件的性能即最优化这两个器件的结构和方法。在一个实施例中，该制造方法使用双外延工艺用于在毫米波范围内工作的芯片上PIN二极管；尽管如高击穿NPN HBT，变容二极管，无源器件，肖特基二极管的其它器件也期望用于本发明中。通过执行本发明，使用同一晶片，可以制造具有薄集电极的高性能NPN并且可以制造具有厚膜集电极的高击穿电压器件。另外，在本发明中，第二子集电极可以用作高击穿器件的通孔(reachthrough)将子集电极与表面接触。本发明的系统和方法与已有的BiCMOS技术完全兼容。
参考图1，示出了包括在衬底10上形成的衬垫氧化物12的初始结构。在一个实施例中，衬底可以是硅，虽然同样可以使用如III-V化合物半导体衬底或SOI的其它材料。虽然对本发明的理解并不关键，但是衬底10约为700μm厚，本发明也旨在其它厚度。衬垫氧化物12具有在50
Figure C20061014313700071
和150之间的厚度；虽然，本发明也旨在其它厚度。可以通过常规的沉积或生长工艺形成衬垫氧化物层12。
在图2中，在衬垫氧化物12上形成光致抗蚀剂14。在图3中，曝光光致抗蚀剂14以向下面的层打开窗口16。在如使用旋涂玻璃技术的公知的半导体光致抗蚀剂工艺中形成窗口16。因此，对从事此具体步骤的本领域的技术人员没必要再对光致抗蚀剂工艺进行描述。
在图3中，在光致抗蚀剂12中打开窗口16后，制造方法继续用公知的掺杂剂掺杂如离子注入暴露的下面的层。在一个示意性实施例中，用于集电极的掺杂元素可以包括如砷(As)或锑(Sb)。在一个实施中，以普通能量水平和剂量进行掺杂，例如，能量范围约20-60keV和剂量为1E15到5E16。可以使用如深N+的离子注入工艺形成子集电极18，延伸到下面的层。
参考图4，使用常规工艺剥离光致抗蚀剂层12。在此工艺步骤中，还可以使用常规工艺剥离，例如蚀刻衬垫氧化物12。在一个实施例中，剥离工艺除去在上述掺杂工艺期间出现的任何注入损伤。
在图5中，在衬底10上形成外延(epi)层20，并且在图6中，在外延层20上形成光致抗蚀剂层22。在一个实施例中，在光致抗蚀剂层22形成之前，可以在外延层20上形成衬垫氧化物层。在常规制造工艺中，光致抗蚀剂层22曝露于光以打开窗口24。
在图7中，使用如磷，砷或锑的掺杂剂进行离子注入工艺以形成通孔，如在区域26中所示。通孔用作导电通道以连接远侧子集电极18到表面。远侧子集电极18可以形成例如最终结构中的PIN二极管阴极或高击穿NPN HBT的子集电极。然后使用常规工艺剥离光致抗蚀剂层22(以及，在实施例中，衬垫氧化物层)。在此剥离工艺期间可以修复来自离子注入工艺的任何损伤。
在图8中，以任意常规方式，在外延层20上形成衬垫氧化物层28和另一光致抗蚀剂层30。例如，在前一步中，可以热生长或沉积衬垫氧化物层28。在常规半导体工艺步骤中，在光致抗蚀剂层30中打开窗口32，远离子集电极18。
在图9中，使用如磷，砷或锑的掺杂剂进行常规离子注入工艺。此掺杂剂工艺在外延层20中形成集电极34。使用常规工艺剥离光致抗蚀剂层30，其后剥离衬垫氧化物28。在一个实施例中，此剥离工艺可以除去在上述掺杂工艺期间发生的任何注入损伤。
在图10中，在结构上形成第二外延层36。更具体地说，在集电极34和外延层20上形成外延层36。优选第二外延层36具有与外延层20不同的厚度。第一和第二外延层两者都可以制成具有宽的厚度弹性以提供器件的可调。在本发明的一个实施例中，外延层36约为0.4μm并且更优选0.3μm到1μm的范围，其小于通常在1-3μm范围的外延层20的厚度。在任何情况下，可以形成任何厚度的第二外延层36以调整器件，因此提供在已知制造方法之上的优点。
通过制造具有期望的厚度的第二外延层36，可以在单个晶片上制造用于高性能NPN器件的薄膜集电极和用于高击穿电压器件的厚膜集电极。通过具有薄膜集电极和厚膜集电极，可以最优化高性能NPN器件和高击穿电压器件的性能。
在图11中，在常规工艺中形成浅沟槽隔离结构38和深沟槽隔离结构40。形成浅沟槽隔离结构38和深沟槽隔离结构40用于器件隔离目的。可选地，隔离结构可以包括硅的原地氧化(“LOCOS”)结构。
在图12中，在第二外延层36中形成第二通孔42。第二通孔42用作导电通道以连接集电极或第一通孔到表面用于接触。通过如磷，砷或锑的核素的离子注入形成通孔。通孔注入的能量范围和剂量范围分别为从50-100KeV和从1e15到5e16。应该适当对准用于连接第一通孔的第二通孔以消除不对准引起的高电阻。
仍参考图12，在外延层36上以如LTE，LPCVD，CVD等的常规外延方式选择生长P+膜46，以形成高性能NPN HBT基极和PIN二极管阳极。这里没有示出其它工艺细节但是本领域的技术人员应该明白。例如，可以使用氧化物层以在CVD工艺期间保护外延层36。在沉积P+膜后还可以形成氮化物膜以保护HBT，PIN等不被FET工艺侵害。当制造接触时，可以打开氮化物膜。
完成集成电路要求剩下的工艺步骤包括这样的步骤，如形成高性能NPN发射极层，形成钝化部件，形成互连金属化等，其执行在技术上已公知。例如，在图13中，在P+膜46上用CVD工艺沉积层间介质层48优选包括BPSG。在实施例中，沉积层间介质层48以将器件与随后沉积的覆盖金属层电绝缘。以常规方式在层间介质层48中形成钨接触50，连接到P+膜46和通孔42。与通孔接触的钨接触50形成器件的N+接线端并且与P+膜接触的钨接触50形成器件的P+接线端。
在图13的实施例中，器件的远侧子集电极18部分可以用于形成高击穿电压器件。在实施例中，高击穿电压器件可以包括NPN HBT晶体管，PIN二极管，变容二极管，无源器件，肖特基二极管及类似器件。结构一侧的集电极34，另一方面可以用于形成在比高击穿电压器件的集电极层更薄的集电极层上形成的高性能NPN器件，从而最优化这两个器件的性能。
表1示出了根据本发明的实施例的PIN二极管的射频响应性能。该性能包括，例如，正向模式下的插入损耗(db)和反向模式下的隔离(db)性能。图14是表1中示出的PIN二极管的掺杂分布的图示。在表1中示出的性能包括三个样品的六个GHz范围，从2GHz到100GHz。
表1
第一外延层厚度   0.8um   1.5um   2um
  f(GHz) 插入损耗(dB) 隔离(dB) 插入损耗(dB) 隔离(dB) 插入损耗(dB) 隔离(dB)
  2   -0.95619   -41.655   -1.8966   -46.062   -2.0015   -47.39
  10   -0.9178   -27.369   -1.8354   -31.502   -1.9403   -33.357
  30   -0.90873   -17.318   -1.8049   -21.279   -1.9479   -24.743
  60   -0.84959   -11.172   -1.6497   -15.282   -1.8269   -19.863
  80   -0.67746   -8.8834   -1.3988   -12.876   -1.6191   -17.252
  100   -0.65171   -7.2844   -1.301   -11.384   -1.5227   -16.151
图15是根据本发明的表1中的结果的图示。
虽然参考实施例的实例描述了本发明，但是应该明白，这里使用的术语是描述和示意性的术语，而不是限制性术语。可以在不脱离本发明的范围和精神下，在所附权利要求范围内进行改变。因此，虽然这里参考特殊的材料和实施例对本发明进行了描述，但是本发明没有旨在限制于这里具体的公开；相反，本发明延伸到所有功能等同的结构，方法和使用，这些都在所附权利要求范围内。

Claims (23)

1.一种半导体结构，包括单晶片，具有在第一厚度的第一区域中形成的第一子集电极和在与所述第一厚度不同的第二厚度的第二区域中形成的第二子集电极，其中所述第二区域在所述第一区域之上；
从所述第一子集电极延伸到所述第二区域的表面的通孔和从所述第二子集电极延伸到所述第二区域的表面的通孔；
在所述第二区域中形成的浅隔离结构，以及深隔离结构，其中所述深隔离结构穿过所述第一区域和所述第二区域延伸到下面的衬底；
在所述第二区域上形成的P+膜；以及
从所述P+膜延伸到层间介质层的表面的金属接触，其中所述层间介质层形成在所述P+膜上。
2.根据权利要求1的结构，其中所述第一子集电极形成高击穿电压器件。
3.根据权利要求2的结构，其中所述第二子集电极形成高性能NPN器件。
4.根据权利要求2的结构，其中所述高击穿电压器件为PIN二极管。
5.根据权利要求2的结构，其中所述高击穿电压器件是NPN HBT晶体管，变容二极管，无源器件和肖特基二极管中的一种。
6.根据权利要求1的结构，其中所述第一区域的厚度范围在1μm到3μm。
7.根据权利要求1的结构，其中所述第二区域的厚度为0.3μm到1μm。
8.根据权利要求1的结构，还包括在所述第二区域上形成的层间介质层。
9.根据权利要求1的结构，其中所述金属接触延伸到接触所述第一子集电极的通孔。
10.根据权利要求9的结构，其中延伸到接触所述第一子集电极的所述通孔的所述金属接触形成N+接线端。
11.根据权利要求1的结构，其中接触所述P+膜的所述金属接触形成P+接触。
12.一种多电路结构，包括：
第一子集电极，在具有第一厚度的第一区域中形成；
第二子集电极，在厚度小于所述第一区域的第二区域中形成；
从所述第一子集电极延伸到所述第二区域的表面的通孔和从所述第二子集电极延伸到所述第二区域的表面的通孔；
在所述第二区域中形成的浅隔离结构，以及深隔离结构，其中所述深隔离结构穿过所述第一区域和所述第二区域延伸到下面的衬底；
在所述第二区域上形成的P+膜；以及
从所述P+膜延伸到层间介质层的表面的金属接触，其中所述层间介质层形成在所述P+膜上，
其中所述第二区域在所述第一区域之上，且所述第一子集电极形成高击穿电压器件并且所述第二子集电极形成高性能NPN器件。
13.根据权利要求12的结构，其中所述高击穿电压器件是高击穿NPNHBT，PIN二极管，变容二极管，无源器件或肖特基二极管。
14.根据权利要求12的结构，其中所述第一区域的厚度范围在1μm到3μm。
15.根据权利要求12的结构，其中所述第二区域的厚度为0.3-1μm。
16.根据权利要求12的结构，还包括在所述第二区域上形成的层间介质层。
17.根据权利要求12的结构，其中延伸到接触所述第一子集电极的所述通孔的所述金属接触形成N+接线端。
18.根据权利要求12的结构，其中接触所述P+膜的所述金属接触形成P+接线端。
19.一种形成半导体结构的方法，包括如下步骤：
提供包括第一区域的衬底；
在所述第一区域中形成第一子集电极；
在所述第一区域中且在所述第一子集电极上形成第一通孔；
在所述第一区域上形成第二区域；
在所述第二区域中形成第二子集电极，其中所述第二子集电极以不同于所述第一子集电极的深度形成；以及
在所述第二区域中且在所述第二子集电极和所述第一通孔上形成第二通孔，所述第二通孔用于连接所述第一通孔并且作为用于包括所述第二子集电极的器件的通孔；
在所述第二区域中形成浅隔离结构，且形成深隔离结构，其中所述深隔离结构穿过所述第一区域和所述第二区域延伸到下面的衬底；
在所述第二区域上形成P+膜；以及
形成从所述P+膜延伸到层间介质层的表面的金属接触，其中所述层间介质层形成在所述P+膜上。
20.根据权利要求19的方法，还包括在所述第二区域上形成层间介质层。
21.根据权利要求19的方法，其中所述第一区域位于所述衬底的上部并且所述第二区域是外延膜。
22.根据权利要求20的方法，其中所述层是外延膜。
23.根据权利要求19的方法，其中所述第一子集电极是用于PIN二极管或高击穿NPN HBT子集电极的阴极板并且所述第二子集电极是用于高性能双极晶体管的子集电极。
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