CN107680966B - 自对准与非自对准的异质接面双极晶体管的共同整合 - Google Patents

自对准与非自对准的异质接面双极晶体管的共同整合 Download PDF

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CN107680966B
CN107680966B CN201710650270.0A CN201710650270A CN107680966B CN 107680966 B CN107680966 B CN 107680966B CN 201710650270 A CN201710650270 A CN 201710650270A CN 107680966 B CN107680966 B CN 107680966B
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hbt
emitter
epitaxial
semiconductor structure
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CN107680966A (zh
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V·贾殷
刘岂之
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GlobalFoundries US Inc
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Abstract

本发明涉及自对准与非自对准的异质接面双极晶体管的共同整合，是关于半导体结构，且更特别的是，关于自对准与非自对准的异质接面双极晶体管的共同整合和制法。该结构包括在相同晶圆上以不同外延基极分布整合的至少两个异质接面双极晶体管(HBT)装置。该至少两个HBT装置中的第二装置的本质基极外延是用作该至少两个HBT装置中的第一装置的外质基极。

Description

自对准与非自对准的异质接面双极晶体管的共同整合
技术领域
本发明是有关于半导体结构，且更特别的是，有关于自对准与非自对准的异质接面双极晶体管的共同整合和制法。
背景技术
异质接面双极晶体管(HBT)为一种双极接面晶体管(BJT)，其于发射极和基极区或于基极和集电极区是使用不同的半导体材料，由此建立异质接面。HBT可处理极高频率的讯号，达数百GHz。HBT常使用于射频(RF)系统，以及需要高功率效率的应用，例如手机中的RF功率放大器。
由于不同的优化要求，有极优良低噪声放大器(LNA)和极优良功率放大器(PA)硅锗HBT的BiCMOS技术难以在同一个晶圆上整合。例如，LNA装置需要高电流增益beta，低Rb(基极电阻)及低Ccb(集电极-基极电容)用于低噪声指数(NF)及高增益。自对准发射极/基极整合方案用于LNA为较佳，因为它产生较低的Rb及较低的Ccb。在LNA技术中，通常使用产生高Rb及高基极电流(低beta)的植入外质基极结构。另一方面，PA装置需要低Cbe(基极-发射极电容)及高BVceo(就给定beta而言)。在此等PA实作中，需要宽发射极且发射极-基极的自对准不是必要的。因此，在当前整合方案中，只能优化一个装置的效能，而另一装置的效能大多受限。
发明内容
在本发明的态样中，一种结构，其包含在相同晶圆上以不同外延(epitaxial)基极分布整合的至少两个异质接面双极晶体管(HBT)装置。该至少两个HBT装置中的第二装置的本质基极外延是用作该至少两个HBT装置中的第一装置的外质基极。
在本发明的态样中，一种结构，其包含：形成于衬底上的第一异质接面双极晶体管(HBT)装置，以及形成于该衬底上的第二HBT装置。该第一HBT装置包含：由该衬底形成的集电极区；有形成于该集电极区上方开口中的第一分布的自对准外延基极；以及邻近该外延基极具有该第一分布的自对准发射极区。该第二HBT装置包含：由该衬底形成的集电极区；有与该第一分布不同的第二分布的外延基极，其形成于该集电极区上方的开口中；以及邻近该外延基极具有该第二分布的发射极区。
在本发明的态样中，一种方法，其包含下列步骤：以非选择性外延成长用于第一装置的第一硅锗基极；成长用于第二装置的第二硅锗基极，该第一硅锗基极及该第二硅锗基极有不同的基极分布；形成用于该第一装置的发射极窗口及底切(undercut)于该第一硅锗基极上面；使外质基极在该底切内连结至用于第一装置的本质基极；形成用于该第二装置的发射极窗口；以及同时形成用于该第一装置及该第二装置的发射极。
附图说明
以下用本发明的示范具体实施例的非限定性实施例，以参考多个图示的方式描述本发明。
图1根据本发明的态样表示起始结构和各个制程。
图2根据本发明的态样表示第一装置的基极区的开口和各个制程。
图3根据本发明的态样表示除数个其他材料层的外在开口内的基极材料和各个制程。
图4根据本发明的态样表示第二装置的基极区的基极开口及间隔体形成和各个制程。
图5根据本发明的态样表示除数个其他层的外在第二装置的开口内的基极材料和各个制程。
图6根据本发明的态样表示第一装置的发射极开口及底切和各个制程。
图7根据本发明的态样表示侧壁间隔体形成以及在第一装置的开口中的成长，和第二装置的发射极开口。
图8根据本发明的态样表示第一装置及第二装置的发射极和各个制程。
图9根据本发明的态样表示各自有接触的两个HBT装置和制程。
主要组件符号说明
10 结构
12 衬底
14 浅沟槽隔离(STI)结构
16 氧化物材料
18 多晶材料
20 窗口或开口
22 低温外延材料
24 氧化物材料
26 多晶材料
28 开口
30 间隔体
32 低温外延材料
34 氧化物材料
36 氮化物材料
38 发射极窗口或开口
40 底切
42 发射极间隔体
42' 另一间隔体
44 半导体材料
46 氧化物材料
48 发射极窗口或开口
50 发射极材料
52 氮化物材料
54、56 发射极
100 结构
110 发射极区
110'、110” 接触
115 集电极区
115'、115” 接触
120 衬底。
具体实施方式
本发明是有关于半导体结构，且更特别的是，有关于自对准与非自对准的异质接面双极晶体管的共同整合和制法。更特别的是，本发明提供一种优化两个NPN装置的整合方案，例如，低噪声放大器(LNA)及功率放大器(PA)装置。在具体实施例中，例如，LNA及PA装置有优化的硅锗基极分布。除了优化PA及LNA的硅锗基极分布以外，也根据LNA及PA装置的特定需要，特别优化彼等的整合方案(亦即，发射极/基极整合方案)。描述于本文的整合方案也可应用于其他应用，例如，高fT及高fmax装置或PA装置以及高效能(HP)装置等等。HP装置通常有极高fT/fmax用于自动雷达、光学通讯应用系统等等。
在更特定的具体实施例中，两个HBT装置在同一个晶圆上以两个不同硅锗外延基极分布及两个不同整合方案整合。例如，一个装置的本质基极外延可用作第二装置的外质基极高分子。更特别的是，在具体实施例中，双重优化可以是使用非选择性外延作为LNA装置的升高外质基极层的部份的结果。在具体实施例中，例如，外延分布可在基极中的掺杂、厚度及锗含量态样不同。该装置也可具有相同的发射极(同时形成)以及相同或不同的集电极。此外，一个HBT(例如，LNA装置)可具有自对准发射极/基极整合，然而，另一个HBT(例如，PA装置)可具有非自对准发射极/基极整合。
可用使用许多不同工具、许多方法制造本发明的双重整合方案。然而，一般而言，该方法及工具是用来形成有微米及纳米级尺寸的结构。用来制造本发明的双重整合方案的该方法(亦即技术)是选自集成电路(IC)技术。例如，该结构建立于晶圆上以及实现于晶圆上面用光微影制程(photolithographic process)图案化的材料膜中。特别是，该双重整合方案的制造使用以下三个基本建造区块：(i)沉积材料薄膜于衬底上，(ii)用光微影成像法施加图案化屏蔽于薄膜上面，以及(iii)对于该屏蔽选择性地蚀刻薄膜。
图1根据本发明的态样表示结构和各个制程。如同图示于本文的所有附图，该整合方案根据本发明的态样表示用于LNA装置(在“A”面上)及PA装置(在“B”面上)的制程。本领域技术人员应了解，也可考虑利用本文所述整合方案的其他装置。
在具体实施例中，结构10包括形成于衬底12的浅沟槽隔离(STI)结构14。在具体实施例中，例如，衬底12可为硅，绝缘体上覆硅(SOI)或碳化硅。衬底12在STI结构14之间的区域可形成HBT(例如，LNA装置及PA装置)的集电极区。在具体实施例中，集电极植入物在该装置之间可能相同。为了形成STI结构14，例如，形成阻剂于衬底12上面且暴露于能量(光)以形成与STI结构14对应的开口。通过该开口，用现有蚀刻制程，例如，反应性离子蚀刻法(RIE)，于衬底12中形成沟槽。该阻剂用现有剥除剂(stripant)或氧气灰化法(oxygenashing)移除，然后沉积氧化物材料于沟槽中，接着是化学机械研磨(CMP)。
仍参考图1，形成氧化物材料16于STI结构14和衬底12的暴露表面上面。在具体实施例中，氧化物材料16可用现有化学气相沉积(CVD)制程沉积有约100埃至约400埃的厚度；然而本文也考虑其他的厚度。沉积多晶材料(poly material)18于氧化物材料16上面。在具体实施例中，多晶材料18可用现有CVD制程沉积有约100埃至约400埃的厚度；然而本文也考虑其他的厚度。
在图2中，形成穿过在装置的LNA面(例如，“A”面)上的氧化物材料16及多晶材料18的窗口或开口20，以暴露底下衬底12的表面。在具体实施例中，开口20的制作是通过形成屏蔽或阻剂于多晶材料18上且使它暴露于能量以形成开口，接着是蚀刻(RIE)制程以移除在装置的LNA面上的氧化物材料16及多晶材料18。然后，该阻剂可用现有剥除剂或氧气灰化法移除。如图2所示，装置的PA面(例如，“B”面)不会经受任何蚀刻制程，因为它仍被阻剂保护。
在图3中，形成低温外延材料22于开口20(在衬底12的暴露表面上)内以及多晶材料18在衬底的LNA面及PA面上的暴露表面。本领域技术人员应了解，低温外延材料22为非选择性材料，它会在装置的LNA面(例如，“A”面)上成长为衬底12上的单晶硅锗；然而，低温外延材料22会在多晶材料18及任何介电材料的表面上成长为多晶或非晶材料。在具体实施例中，低温外延材料22可为本领域技术人员所现有的其他半导体材料。低温外延材料22可成长至约300埃至约3000埃的厚度；然而由本发明也可考虑其他的厚度。
在具体实施例中，硅锗材料22会形成LNA装置的基极区，它可加以优化。例如，硅锗材料22可具有不同的锗浓度以得到特定的beta，例如，高beta。例如，锗浓度可在约5％至40％之间。此外或者是，硅锗材料22可具有高基极掺杂物以便提供LNA装置的低基极电阻。例如，基极硼掺杂可高达5E20/cm3。
仍参考图3，在具体实施例中，依序沉积氧化物材料24及多晶材料26于低温外延材料22上面，例如，单晶硅锗与多晶材料。在具体实施例中，氧化物材料24与多晶材料26分别用现有沉积制程沉积，例如，CVD。氧化物材料24与多晶材料26可各自沉积至约200埃的厚度；然而本文也考虑其他的厚度。
请参考图4，形成开口28于PA面(例如，“B”面)上的基极区中。在具体实施例中，开口28用现有微影(lithography)及蚀刻制程形成，如本文所述，以暴露衬底12的表面。在具体实施例中，衬底的LNA面(例如，“A”面)在形成开口28期间仍用阻剂保护。视需要间隔体30形成于开口28的侧壁上。在具体实施例中，间隔体30为用现有共形沉积制程(conformaldeposition process)形成的氮化物材料，接着是各向异性蚀刻制程(anisotropicetching process)以移除水平表面的间隔体材料。
在图5中，低温外延材料32形成于开口30(在衬底12的暴露表面上)内以及多晶材料26在衬底的LNA面及PA面上的暴露表面。如前述，低温外延材料32为会在衬底12上成长为单晶半导体材料的非选择性材料；然而，低温外延材料32会在多晶材料及任何介电材料的表面上成长为多晶或非晶材料，例如，暴露STI区14的氧化物材料。以此方式，第二装置(例如，PA装置)的本质基极外延是用作第一装置(例如，LNA装置)的外质高分子基极。在具体实施例中，低温外延材料32可为其他半导体材料。
在具体实施例中，硅锗材料32会形成PA装置的基极区，它可针对低电容及高崩溃电压加以优化。例如，硅锗(半导体)材料32可具有不同的锗浓度以得到用于高BVceo的特定beta。此外或者是，硅锗材料32可具有基极掺杂物或浓度以便提供PA装置的低基极及/或发射极电容，以及不同的厚度以调整崩溃电压。例如，在PA的硅锗中的锗浓度可在约5％至25％之间，以及NPN结构的基极掺杂物可为浓度高达2E20/cm3的硼。此外，例如，低温外延材料32可为比LNA装置的材料22厚些的层，例如，成长至300埃以上至约3000埃的厚度，以提高崩溃电压。以此方式，此时有可能至少两个HBT装置在同一个晶圆上以不同的外延基极分布整合。再者，非选择性外延，例如，低温外延材料32，可用作LNA装置的升高外质基极层的一部份。
仍参考图5，在具体实施例中，依序沉积氧化物材料34及氮化物材料36于低温外延材料32上面，例如，单晶硅锗及多晶材料。在具体实施例中，氧化物材料34及氮化物材料36分别用现有沉积制程沉积，例如，CVD。氧化物材料34与氮化物材料36可各自沉积至约200埃的厚度；然而本文也考虑其他的厚度。在具体实施例中，层34及36在“A”及“B”上可具有相同的厚度。再者，层34及36可沉积于“B”面上的整个结构，包括在间隔体30外的区域。
如图6所示，形成发射极窗口或开口38于该结构的LNA面上，例如，“A”面。在具体实施例中，发射极窗口或开口38用现有微影及蚀刻制程形成，例如，RIE，其中氧化物材料24是用作蚀刻中止层。该结构的PA面，例如，“B”面，在蚀刻制程期间仍被阻剂或屏蔽材料保护。在具体实施例中，形成发射极间隔体42于发射极窗口或开口38的侧壁上。发射极间隔体42在移除阻剂材料后可形成。在具体实施例中，发射极间隔体42为用共形沉积制程形成的氮化物材料，接着是各向异性蚀刻制程以移除该结构的水平表面的发射极材料。
在发射极间隔体42形成后，可于氧化物材料24中形成与发射极窗口或开口38对准的底切40。底切40可用氧化物材料24的湿蚀刻制程形成以暴露底下的半导体材料22，例如，低温外延材料。蚀刻时间可决定，例如，底切40具有不同的尺寸，例如，约500埃至约3000埃之间。
请参考图7，用选择性外延成长制程在底切40中形成半导体材料44，例如，硅材料，以使升高的外质基极链接至在该结构的LNA区上(例如，“A”面)的本质基极。本领域技术人员应了解，半导体材料44会成长于低温外延材料22(例如，硅锗)的暴露表面上而填满底切40。再者，本领域技术人员应了解，半导体材料44由于选择性成长条件而不会成长于该结构的LNA区及PA区两者的上表面上的氮化物材料36上。此外，在外质基极与本质基极之间的氧化物层减少装置的Ccb导致更高的效益。
进一步如图7所示，在半导体材料44形成后，毯式沉积(blanket deposit)氧化物材料46及附加氮化物材料于结构上，且特别的是，于半导体材料44上面。该氮化物材料会使发射极间隔体42延伸至半导体材料44。该氮化物材料会经受各向异性蚀刻制程以形成另一间隔体42'以及移除该结构的水平表面的任何多余材料。
仍参考图7，如前述，使用现有微影及蚀刻制程，例如，RIE，形成发射极窗口或开口48于该结构的PA面上，例如，“B”面。发射极窗口或开口48会暴露低温外延材料32的表面。
如图8所示，移除开口38(及其他表面)的氧化物材料(例如，氧化物材料46)，接着是沉积发射极材料50于开口38、48中。在具体实施例中，发射极材料50可原位掺杂多晶硅，例如，掺杂砷及磷的多晶硅。形成氮化物材料52于发射极材料50上面。在具体实施例中，发射极材料50及氮化物材料52可用共形沉积制程沉积，例如，CVD，接着是图案化制程以同时形成LNA装置的发射极54与PA装置的发射极56。该图案化制程可为现有微影及蚀刻制程，如本文所述，以形成LNA的发射极54与PA的发射极56。
仍参考图8，该结构随后经受植入制程以形成NPN结构。在具体实施例中，该植入制程为P型植入，例如，硼。该植入物可具有大于1E14的剂量。此外，在具体实施例中，可添加锗或碳以减少硼的扩散。制程继续对于LNA装置及PA装置的外质基极接触及集电极接触使用相同的蚀刻制程(例如，用于这两个装置的同一个屏蔽)。
因此，此时本领域技术人员应了解，描述于本文的方法形成两个硅锗外延基极分布是通过以非选择性外延成长第一硅锗基极，沉积牺牲基极氧化物层以及多晶硅或非晶硅层，以及建立用于第二型NPN(例如，PA装置)的窗口。该方法更包含：成长第二硅锗基极，形成用于第一型NPN(例如，LNA装置)的发射极窗口，以及蚀刻用于选择性外延的空腔或底切以使外质基极连结至用于第一型NPN的本质基极。可形成用于第二型NPN(例如，PA装置)的发射极窗口，其中同时形成用于这两种NPN(例如，PA与LNA)的发射极。在具体实施例中，第二型装置(例如，PA)的本质基极外延可为第一型装置(例如，LNA)的外质基极。
此外，提供如表1所示的特征如下。
表1
Figure BDA0001367873950000091
图9根据本发明的态样表示各自有接触的两个HBT装置和制程。更特别的是，图9的结构100表示在“A”面上的发射极在上装置(emitter up device)与在“B”面上的集电极在上装置(collector up device)。在具体实施例中，该发射极在上装置包括在衬底120上方的发射极区110，以及集电极区115在衬底120内；然而，该集电极在上装置包括在衬底120内的发射极区110以及在衬底120上方的集电极区115。在具体实施例中，该发射极在上装置有自对准发射极及基极区，以及该集电极在上装置有非自对准集电极及基极区。该结构的发射极区、集电极区及其余结构可用已描述于本文的方法制造使得对于了解该制程的本领域技术人员不需要多作解释。
仍参考图9，在发射极在上装置中，接触110'是接触在衬底120上方的发射极区110，以及接触115'接触在发射极区110的一侧上的集电极区115。同样，在集电极在上装置中，接触115”是接触在衬底120上方的集电极区115，以及接触110”接触在集电极区115的一侧上的发射极区110。接触110'、110”、115'及115”可用已描述于本文的现有微影、蚀刻及沉积制程制造使得对于了解该制程的本领域技术人员不需要多作解释。
上述方法是使用于集成电路芯片的制造。所得集成电路芯片可由制造者以原始晶圆形式(raw wafer form，也就是具有多个未封装芯片的单晶圆)、作为裸晶粒(bare die)或已封装的形式来销售。在后者情形下，芯片装在单芯片封装体中(例如，塑料载体(plastic carrier)，具有固定至主板或其他更高层载体的引脚(lead))，或多芯片封装体中(例如，具有表面互连件(surface interconnection)或内嵌互连件(buriedinterconnection)其一或两者兼具的陶瓷载体)。然后，在任何情形下，芯片与其他芯片、离散电路组件及/或其他信号处理装置整合成为(a)中间产品(例如，主板)，或(b)最终产品中的其一者的一部分。该最终产品可为包括集成电路芯片的任何产品，从玩具及其他低端应用到有显示器、键盘或其他输入设备及中央处理器的先进计算机产品不等。
已提出本发明的各种具体实施例的说明是为了说明而非旨在穷尽或限定所揭示的具体实施例。本领域技术人员明白在不脱离所揭示具体实施例的精神及范畴下仍有许多修改及变体。选择使用于本文的术语以最佳地解释该具体实施例的原理，实际应用或优于出现于市上的技术的技术改善，或致能其他本领域技术人员了解揭示于本文的具体实施例。

Claims (19)

1.一种半导体结构，包含在相同晶圆上以不同外延基极分布整合的至少两个异质接面双极晶体管(HBT)装置，其中，该至少两个HBT装置中的第二装置的本质基极外延是用作该至少两个HBT装置中的第一装置的外质基极，该至少两个HBT装置的该第一装置及该第二装置有相同的发射极材料，且氮化物材料直接沉积于该第一装置及该第二装置的相同的该发射极材料上面。
2.如权利要求1所述的半导体结构，其中，该不同外延基极分布为两个不同的硅锗外延基极分布。
3.如权利要求1所述的半导体结构，其中，该至少两个HBT装置包括功率放大器与低噪声放大器。
4.如权利要求1所述的半导体结构，其中，于底切中形成半导体材料，以使升高的外质基极连结至在该第一装置上的本质基极。
5.如权利要求4所述的半导体结构，其中，该第二装置的该外延基极为硅锗材料，以及该第一装置的该外质基极为多晶材料。
6.如权利要求1所述的半导体结构，其中，该至少两个HBT装置中的第一装置包括自对准发射极/基极整合。
7.如权利要求6所述的半导体结构，其中，该至少两个HBT装置中的该第二装置包括非自对准发射极/基极整合。
8.如权利要求1所述的半导体结构，其中：
该不同外延基极分布有不同的掺杂物浓度用于该至少两个HBT装置的该第一装置及该第二装置；
该不同外延基极分布有不同的锗含量用于该至少两个HBT装置的该第一装置及该第二装置；以及
该不同外延基极分布有不同的厚度用于该至少两个HBT装置的该第一装置及该第二装置。
9.如权利要求1所述的半导体结构，其中，该至少两个HBT装置包括有自对准发射极及基极区的发射极在上装置以及有非自对准集电极及基极区的集电极在上装置。
10.如权利要求1所述的半导体结构，其中，该至少两个HBT有不同的集电极区。
11.一种半导体结构，包含：
形成于衬底上的第一异质接面双极晶体管(HBT)装置，该第一HBT装置包含：
由该衬底形成的集电极区；
形成于该集电极区上方的开口中的具有第一外延基极分布的自对准外延基极；以及
邻近具有该第一外延基极分布的该自对准外延基极的自对准发射极区；
形成于该衬底上的第二HBT装置，该第二HBT装置包含：
由该衬底形成的集电极区；
具有与该第一外延基极分布不同的第二外延基极分布的外延基极，其形成于该集电极区上方的开口中；以及
邻近具有该第二外延基极分布的该外延基极的发射极区，
其中，该第一HBT装置及该第二HBT装置有相同的发射极材料，且氮化物材料直接沉积于该第一HBT装置及该第二HBT装置的相同的该发射极材料上面。
12.如权利要求11所述的半导体结构，其中，该第二HBT装置包括非自对准发射极/基极整合。
13.如权利要求11所述的半导体结构，其中，该第一及该第二外延基极分布为两个不同的硅锗外延基极分布。
14.如权利要求13所述的半导体结构，其中，该第一及该第二外延基极分布有不同的掺杂物浓度。
15.如权利要求13所述的半导体结构，其中，该第一及该第二外延基极分布有不同的厚度，以及该第一及该第二外延基极分布有不同的锗含量。
16.如权利要求11所述的半导体结构，其中，该第一HBT装置的集电极区与该第二HBT装置的该集电极区不同。
17.如权利要求11所述的半导体结构，其中，该第二HBT装置的本质基极外延为该第一HBT装置的外质基极。
18.如权利要求17所述的半导体结构，其中，该第二HBT装置的该外延基极为硅锗材料，以及该第一HBT装置的该外质基极为多晶材料。
19.一种制造半导体结构的方法，包含下列步骤，
以非选择性外延成长用于第一装置的第一硅锗基极；
成长用于第二装置的第二硅锗基极，该第一硅锗基极及该第二硅锗基极有不同的基极分布；
形成用于该第一装置的发射极窗口及底切于该第一硅锗基极上面；
使外质基极在该底切内连结至用于第一装置的本质基极；
形成用于该第二装置的发射极窗口；
同时形成用于该第一装置及该第二装置的发射极，其中，该第一装置及该第二装置有相同的发射极材料；以及
直接沉积氮化物材料于该第一装置及该第二装置的相同的该发射极材料上面。
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