CN100533403C - 高速缓冲存储器管理系统和方法 - Google Patents
高速缓冲存储器管理系统和方法 Download PDFInfo
- Publication number
- CN100533403C CN100533403C CNB2004800427711A CN200480042771A CN100533403C CN 100533403 C CN100533403 C CN 100533403C CN B2004800427711 A CNB2004800427711 A CN B2004800427711A CN 200480042771 A CN200480042771 A CN 200480042771A CN 100533403 C CN100533403 C CN 100533403C
- Authority
- CN
- China
- Prior art keywords
- data
- cache memory
- group
- storage
- processor unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (34)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2004/022878 WO2006019374A1 (en) | 2004-07-14 | 2004-07-14 | Cache memory management system and method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1961295A CN1961295A (zh) | 2007-05-09 |
CN100533403C true CN100533403C (zh) | 2009-08-26 |
Family
ID=35907684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800427711A Expired - Fee Related CN100533403C (zh) | 2004-07-14 | 2004-07-14 | 高速缓冲存储器管理系统和方法 |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1769360A4 (zh) |
JP (1) | JP5071977B2 (zh) |
KR (1) | KR101158949B1 (zh) |
CN (1) | CN100533403C (zh) |
WO (1) | WO2006019374A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103430162A (zh) * | 2011-03-04 | 2013-12-04 | 美光科技公司 | 与从第一接口到第二接口的操作性转变相关联的设备、电子装置和方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9001138B2 (en) * | 2011-08-29 | 2015-04-07 | Intel Corporation | 2-D gather instruction and a 2-D cache |
WO2014127832A1 (en) * | 2013-02-22 | 2014-08-28 | Telefonaktiebolaget L M Ericsson (Publ) | Media distribution network with media burst transmission capabilities |
CN107153617B (zh) * | 2016-03-04 | 2023-04-07 | 三星电子株式会社 | 用于利用缓冲器高效访问纹理数据的高速缓存体系结构 |
US10181176B2 (en) * | 2016-03-04 | 2019-01-15 | Samsung Electronics Co., Ltd. | Efficient low-power texture cache architecture |
US11042962B2 (en) | 2016-04-18 | 2021-06-22 | Avago Technologies International Sales Pte. Limited | Hardware optimisation for generating 360° images |
US10209887B2 (en) | 2016-12-20 | 2019-02-19 | Texas Instruments Incorporated | Streaming engine with fetch ahead hysteresis |
JP2020004247A (ja) * | 2018-06-29 | 2020-01-09 | ソニー株式会社 | 情報処理装置、情報処理方法およびプログラム |
CN110569204B (zh) * | 2019-07-23 | 2023-01-20 | 广东工业大学 | 基于fpga和ddr3 sdram的可配置图像数据缓存系统 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5410649A (en) | 1989-11-17 | 1995-04-25 | Texas Instruments Incorporated | Imaging computer system and network |
JPH1083347A (ja) * | 1996-09-06 | 1998-03-31 | Fujitsu Ltd | キャッシュメモリ装置 |
JPH10116191A (ja) * | 1996-10-14 | 1998-05-06 | Hitachi Ltd | 圧縮命令用バッファを備えたプロセッサ |
JP3104643B2 (ja) * | 1997-05-07 | 2000-10-30 | 株式会社セガ・エンタープライゼス | 画像処理装置及び画像処理方法 |
DE69815482T2 (de) * | 1997-12-24 | 2004-04-29 | Texas Instruments Inc., Dallas | Computer Anordnung mit Prozessor und Speicher-Hierarchie und sein Betriebsverfahren |
JP3365293B2 (ja) * | 1998-02-12 | 2003-01-08 | 株式会社日立製作所 | Dram,ロジック混載lsiを使ったキャッシュメモリ及びそれを用いたグラフィックスシステム |
US6560674B1 (en) * | 1998-10-14 | 2003-05-06 | Hitachi, Ltd. | Data cache system |
US6825848B1 (en) * | 1999-09-17 | 2004-11-30 | S3 Graphics Co., Ltd. | Synchronized two-level graphics processing cache |
US6812929B2 (en) * | 2002-03-11 | 2004-11-02 | Sun Microsystems, Inc. | System and method for prefetching data from a frame buffer |
US6957305B2 (en) * | 2002-08-29 | 2005-10-18 | International Business Machines Corporation | Data streaming mechanism in a microprocessor |
-
2004
- 2004-07-14 CN CNB2004800427711A patent/CN100533403C/zh not_active Expired - Fee Related
- 2004-07-14 WO PCT/US2004/022878 patent/WO2006019374A1/en not_active Application Discontinuation
- 2004-07-14 EP EP04757053A patent/EP1769360A4/en not_active Withdrawn
- 2004-07-14 JP JP2007521441A patent/JP5071977B2/ja not_active Expired - Fee Related
- 2004-07-14 KR KR1020067023350A patent/KR101158949B1/ko active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103430162A (zh) * | 2011-03-04 | 2013-12-04 | 美光科技公司 | 与从第一接口到第二接口的操作性转变相关联的设备、电子装置和方法 |
CN103430162B (zh) * | 2011-03-04 | 2016-08-31 | 美光科技公司 | 与从第一接口到第二接口的操作性转变相关联的设备、电子装置和方法 |
US9529736B2 (en) | 2011-03-04 | 2016-12-27 | Micron Technology, Inc. | Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface |
Also Published As
Publication number | Publication date |
---|---|
EP1769360A1 (en) | 2007-04-04 |
JP2008507028A (ja) | 2008-03-06 |
CN1961295A (zh) | 2007-05-09 |
KR101158949B1 (ko) | 2012-07-06 |
JP5071977B2 (ja) | 2012-11-14 |
KR20070038955A (ko) | 2007-04-11 |
WO2006019374A1 (en) | 2006-02-23 |
EP1769360A4 (en) | 2008-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10181176B2 (en) | Efficient low-power texture cache architecture | |
US8724914B2 (en) | Image file generation device, image processing device, image file generation method, image processing method, and data structure for image files | |
US6492991B1 (en) | Method and apparatus for controlling compressed Z information in a video graphics system | |
EP2113103B1 (en) | Dynamic configurable texture cache for multi-texturing | |
US6856320B1 (en) | Demand-based memory system for graphics applications | |
JP2008276798A (ja) | タイルリニアホストテクスチャストレージ | |
US7580042B2 (en) | Systems and methods for storing and fetching texture data using bank interleaving | |
CN100533403C (zh) | 高速缓冲存储器管理系统和方法 | |
US7151544B2 (en) | Method for improving texture cache access by removing redundant requests | |
WO2003050759A1 (fr) | Appareil de traitement d'images et procede associe | |
US7725623B2 (en) | Command transfer controlling apparatus and command transfer controlling method | |
WO2003058557A1 (en) | Eeficient graphics state management for zone rendering | |
CN107153617B (zh) | 用于利用缓冲器高效访问纹理数据的高速缓存体系结构 | |
US7170512B2 (en) | Index processor | |
CN110276444A (zh) | 基于卷积神经网络的图像处理方法及装置 | |
US20180004443A1 (en) | Accessing encoded blocks of data in memory | |
KR20060116916A (ko) | 텍스쳐 캐쉬 및 이를 구비한 3차원 그래픽 시스템, 그리고그것의 제어 방법 | |
US6314490B1 (en) | Method and apparatus for memory addressing | |
US7589738B2 (en) | Cache memory management system and method | |
US10706607B1 (en) | Graphics texture mapping | |
JP2003323339A (ja) | メモリアクセス装置、半導体デバイス、メモリアクセス制御方法、コンピュータプログラム及び記録媒体 | |
JPH09259041A (ja) | キャッシュメモリ制御方式 | |
KR102701852B1 (ko) | 버퍼를 이용하여 텍스처 데이터에 액세스하는 방법 및 장치 | |
JP2000276588A (ja) | キャッシュメモリ装置及びプロセッサ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: IDT CO.,LTD. Free format text: FORMER OWNER: AOPUTIX CRYSTAL SILICON CO., LTD. Effective date: 20091016 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20091016 Address after: San Jose, California, USA Patentee after: IDT company Address before: california Patentee before: Silicon Optix Co., Ltd. |
|
ASS | Succession or assignment of patent right |
Owner name: QUALCOMM INC. Free format text: FORMER OWNER: INTEGRATED DEVICE TECHNOLOGY, INC. Effective date: 20130109 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130109 Address after: American California Patentee after: Qualcomm Inc. Address before: San Jose, California, USA Patentee before: IDT company |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090826 Termination date: 20180714 |
|
CF01 | Termination of patent right due to non-payment of annual fee |