EP1769360A4 - Cache memory management system and method - Google Patents
Cache memory management system and methodInfo
- Publication number
- EP1769360A4 EP1769360A4 EP04757053A EP04757053A EP1769360A4 EP 1769360 A4 EP1769360 A4 EP 1769360A4 EP 04757053 A EP04757053 A EP 04757053A EP 04757053 A EP04757053 A EP 04757053A EP 1769360 A4 EP1769360 A4 EP 1769360A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- management system
- cache memory
- memory management
- cache
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2004/022878 WO2006019374A1 (en) | 2004-07-14 | 2004-07-14 | Cache memory management system and method |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1769360A1 EP1769360A1 (en) | 2007-04-04 |
EP1769360A4 true EP1769360A4 (en) | 2008-08-06 |
Family
ID=35907684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04757053A Withdrawn EP1769360A4 (en) | 2004-07-14 | 2004-07-14 | Cache memory management system and method |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1769360A4 (en) |
JP (1) | JP5071977B2 (en) |
KR (1) | KR101158949B1 (en) |
CN (1) | CN100533403C (en) |
WO (1) | WO2006019374A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8806164B2 (en) | 2011-03-04 | 2014-08-12 | Micron Technology, Inc. | Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface |
US9001138B2 (en) * | 2011-08-29 | 2015-04-07 | Intel Corporation | 2-D gather instruction and a 2-D cache |
WO2014127832A1 (en) * | 2013-02-22 | 2014-08-28 | Telefonaktiebolaget L M Ericsson (Publ) | Media distribution network with media burst transmission capabilities |
CN107153617B (en) * | 2016-03-04 | 2023-04-07 | 三星电子株式会社 | Cache architecture for efficient access to texture data using buffers |
US10181176B2 (en) * | 2016-03-04 | 2019-01-15 | Samsung Electronics Co., Ltd. | Efficient low-power texture cache architecture |
US11042962B2 (en) | 2016-04-18 | 2021-06-22 | Avago Technologies International Sales Pte. Limited | Hardware optimisation for generating 360° images |
US10209887B2 (en) | 2016-12-20 | 2019-02-19 | Texas Instruments Incorporated | Streaming engine with fetch ahead hysteresis |
JP2020004247A (en) * | 2018-06-29 | 2020-01-09 | ソニー株式会社 | Information processing apparatus, information processing method, and program |
CN110569204B (en) * | 2019-07-23 | 2023-01-20 | 广东工业大学 | Configurable image data caching system based on FPGA and DDR3SDRAM |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0926600A1 (en) * | 1997-12-24 | 1999-06-30 | Texas Instruments Inc. | Computer system with processor and memory hierarchy and its operating method |
WO2001020460A1 (en) * | 1999-09-17 | 2001-03-22 | S3 Incorporated | Synchronized two-level graphics processing cache |
US20040044847A1 (en) * | 2002-08-29 | 2004-03-04 | International Business Machines Corporation | Data streaming mechanism in a microprocessor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5410649A (en) | 1989-11-17 | 1995-04-25 | Texas Instruments Incorporated | Imaging computer system and network |
JPH1083347A (en) * | 1996-09-06 | 1998-03-31 | Fujitsu Ltd | Cache memory device |
JPH10116191A (en) * | 1996-10-14 | 1998-05-06 | Hitachi Ltd | Processor equipped with buffer for compressed instruction |
JP3104643B2 (en) * | 1997-05-07 | 2000-10-30 | 株式会社セガ・エンタープライゼス | Image processing apparatus and image processing method |
JP3365293B2 (en) * | 1998-02-12 | 2003-01-08 | 株式会社日立製作所 | Cache memory using DRAM and logic embedded LSI and graphics system using the same |
US6560674B1 (en) * | 1998-10-14 | 2003-05-06 | Hitachi, Ltd. | Data cache system |
US6812929B2 (en) * | 2002-03-11 | 2004-11-02 | Sun Microsystems, Inc. | System and method for prefetching data from a frame buffer |
-
2004
- 2004-07-14 CN CNB2004800427711A patent/CN100533403C/en not_active Expired - Fee Related
- 2004-07-14 WO PCT/US2004/022878 patent/WO2006019374A1/en not_active Application Discontinuation
- 2004-07-14 EP EP04757053A patent/EP1769360A4/en not_active Withdrawn
- 2004-07-14 JP JP2007521441A patent/JP5071977B2/en not_active Expired - Fee Related
- 2004-07-14 KR KR1020067023350A patent/KR101158949B1/en active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0926600A1 (en) * | 1997-12-24 | 1999-06-30 | Texas Instruments Inc. | Computer system with processor and memory hierarchy and its operating method |
WO2001020460A1 (en) * | 1999-09-17 | 2001-03-22 | S3 Incorporated | Synchronized two-level graphics processing cache |
US20040044847A1 (en) * | 2002-08-29 | 2004-03-04 | International Business Machines Corporation | Data streaming mechanism in a microprocessor |
Non-Patent Citations (1)
Title |
---|
See also references of WO2006019374A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP1769360A1 (en) | 2007-04-04 |
JP2008507028A (en) | 2008-03-06 |
CN1961295A (en) | 2007-05-09 |
KR101158949B1 (en) | 2012-07-06 |
CN100533403C (en) | 2009-08-26 |
JP5071977B2 (en) | 2012-11-14 |
KR20070038955A (en) | 2007-04-11 |
WO2006019374A1 (en) | 2006-02-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20061121 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR |
|
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20080704 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
18W | Application withdrawn |
Effective date: 20080924 |