JP3365293B2 - Cache memory using DRAM and logic embedded LSI and graphics system using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a graphics system capable of high-speed processing and a cache memory.

[0002]

2. Description of the Related Art In real-time computer graphics, it is common to perform texture mapping when expressing patterns on the surface of an object.
What is texture mapping? Image data (texture) of various patterns to be attached to an object is stored in memory in advance, and when polygons forming the object are pixel-expanded to the display space (destination), This is a process of creating a display color by referring to the pixels of the texture corresponding to the position. This texture mapping is disclosed, for example, in Japanese Patent Laid-Open No. 6-309471. In this publication,
A mode in which the same texture pattern is stored in multiple memories and processed in parallel by multiple drawing processing units, and different texture patterns are stored in multiple memories, and one of the patterns can be selected and used by multiple drawing processing units. It is disclosed that the mode is switched to a processing mode by time division and used.

A data compression technique is known as a means for speeding up data transfer.

[0004]

However, when rendering processors are parallelized to speed up the processing, if each processor has its own memory element and performs the processing independently, a plurality of memory elements store the same contents. Therefore, the memory cannot be used effectively.

Also, unlike the parallelization of general general-purpose processors, in the case of graphics, as shown in FIG. 13, since each processor processes the adjacent destination pixel, the pixels of the texture required by each processor are also included. It's near. Furthermore, since a filter is generally used in texture mapping, the pixels of the texture referred to during mapping generally refer not to one pixel but to all the pixels included in the surrounding area (filter area), so that each processor The pixels of the required texture are overlapping.

As described above, in the processing such as texture mapping having a special locality in which all the processors require substantially the same data, the transfer between the memory and the cache which is effective in the method like the case of the general-purpose processor is performed. Is not done.

Further, it is necessary to refer to a plurality of texture pixels in order to perform the filtering process in the texture mapping, but if these pixels are not in the cache, these pixel values must be transferred from the memory. . When the texture is compressed and stored, the reference pixel may extend over a plurality of compression unit blocks, so that there is a possibility that each cache requests a plurality of blocks for the memory at the same time.

A first object of the present invention is to provide a graphics system capable of high-speed processing while effectively utilizing the memory.

Another object of the present invention is to provide a cache memory for smoothly performing the drawing processor.

[0010]

In order to achieve the above-mentioned object, according to the present invention, a CPU, a memory for storing a plurality of types of texture images, and a texture image in a figure generated based on a command sent from the CPU. Drawing processors for mapping, a plurality of cache memories connected to each drawing processor for storing texture images processed by the drawing processor, a memory and a plurality of cache memories, and a request from the cache memory According to the above, in the graphic processing system having a transfer device for transferring the texture image from the memory to the cache memory, the transfer device selects one of the requests from the plurality of cache memories, and the texture corresponding to this request is selected. Transfer images from memory to all cache memory And wherein the door.

When processing with a plurality of drawing processors,
Since the drawing processor processes neighboring pixels, a request may occur in the near future even if there is no request from the drawing processor at present. Therefore, if the texture is transferred to a cache memory that does not have a request, it is possible to deal with the case where the drawing processor makes a request in the near future, and it is possible to improve the efficiency of data transfer from the memory to the cache memory. it can.

In order to achieve the above object, the present invention is connected to a memory for storing data and a processor for performing processing based on the data stored in the memory,
In a cache memory having a storage unit for storing data read from a memory in response to a request from the processor, the storage unit stores data that is not requested by the processor and is transferred from the memory, and the stored data is the processor. The data is transferred to the processor when the data matches the data requested by the processor.

In other words, by comparing the data in the memory cache with the data requested by the processor, it is possible to store the data not requested by the drawing processor, and the data required in the near future. .

In order to achieve the above object, the present invention is connected to a memory for storing data and a processor for performing processing based on the data stored in this memory,
In a cache memory having a storage unit that stores data read from a memory in response to a request from a processor, the amount of information stored in the storage unit for reading data is less than that for reading data from the memory. And Thereby, the memory for storing the information to be read can be effectively used.

In order to achieve the above object, according to the present invention, a decompression unit that is connected to a processor and a memory that stores compressed texture data and that decompresses compressed texture data transferred from the memory is decompressed. It has a storage unit for storing the texture data and a filter calculation unit for performing the filtering process of the texture data. Thereby, a highly functional texture memory can be realized.

[0016]

DETAILED DESCRIPTION OF THE INVENTION A description will be given below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a graphics system according to the present invention. This system consists of a processing unit that performs graphics processing and a CR that displays the processing result.
It is composed of a display device such as a T display. Further, the processing unit is a main memory MM2000 that stores the CPU 1000 connected to the system bus, programs and data processed by the CPU 1000.
And a geometry processor 3000 for performing coordinate conversion,
A plurality of drawing processors 4000-1 to 4000-4, which generate pixel data to be displayed from the data sent from the geometry processor 3000, and each drawing processor 4
Multiple frame memories FM8000-1 to 8000- that respectively store the pixel data generated by 000-1 to 4000-4
4, DAC9000 that synthesizes pixel data stored in the frame memories FM8000-1 to 8000-4 and converts it into display data,
A texture memory 7000 that compresses and stores image data that is a texture, a plurality of texture caches 5000-1 to 5000 that have a decompression function and a filter calculation function that decompress the compressed image data and that are connected to each rendering processor. -4, and the texture memory 7 in each of the texture caches 5000-1 to 5000-4.
The texture memory manager 6000 for transferring the compressed image data stored in 000.

The CPU 1000 executes the application software stored in the main memory MM 200 and sends a graphics command for performing graphics processing to the geometry processor 3000. Geometry processor 30
00 performs geometric calculation for each figure such as coordinate conversion based on the sent graphic command to generate information necessary to generate pixels inside the figure, and draw processors 4000-1 to 4000. Send to -4. Each of the drawing processors 4000-1 to 4000-4 generates pixel data for display based on the information on the graphic sent from the geometry processor 3000 and the information on the image data attached to the graphic. Pixel data generated by each drawing processor 4000-1 to 4000-4 is connected to the frame memory FM8000-1 to 8000-
4 is stored. These frame memories FM8000-1 ~
Pixel data stored in 8000-4 is synchronized with the display cycle.
It is read by the DAC9000 and displayed on the display device 0000 such as a CRT display. The texture memory 7000 is
Image data, which is a plurality of texture images, is compressed and stored. Image data, which is each texture image, is compressed in advance by application software via the geometry processor 3000 and the texture memory manager 6000. Each texture cache 5000-1
The same image data is stored in ~ 5000-4,
This image data is a copy of a part of the image data which is one texture image stored in the texture memory 7000. Here, “duplication” means that the image data stored in the texture memory 7000 and the image data stored in the texture caches 5000-1 to 5000-4 are the same. Each of the rendering processors 4000-1 to 4000-2 reads image data from the texture caches 5000-1 to 5000-4 connected to it, but if the requested image data exists on the texture caches 5000-1 to 5000-4. If not, texture cache 5000-1
~ 5000-4 is the texture memory manager 6000
Request to transfer the image data requested by the image processor from the texture memory 7000. The texture memory manager 6000 selects a request issued from each of the texture caches 5000-1 to 5000-4, reads the image data corresponding to the selected request from the texture memory 7000, and all texture caches 5000-1 to 5000- 4 (broadcast). Each of the texture caches 5000-1 to 5000-4 decompresses the compressed image data sent from the texture memory manager 6000 and stores the decompressed image data, and the drawing processors 4000-1 to 4000-1.
Each of the drawing processors 4000-1 to 4000 is filtered by filtering the image data according to a request from the 4000-4.
Send to -4.

As described above, in the present system, texture mapping is performed by a plurality of drawing processors, and in this case, each drawing processor has a strong tendency to refer to image data which are textures close to each other as shown in FIG. That is, the image data referred to by a certain drawing processor is likely to be referred to by another drawing processor in the near future. Therefore, the texture memory manager broadcasts the image data requested by a certain texture cache to all the texture caches, so that the transfer efficiency can be improved.

Next, a unit (block) for handling image data which is a texture image will be described with reference to FIG. The minimum unit of the texture image is a pixel.

In this embodiment, a compression unit block for compression and decompression is composed of 4 × 4 pixels, and is used as a basic unit for compressing a texture image. Therefore, from the texture memory 7000 to the texture cache 500
Even when data is transferred to 0-1 to 5000-4, the (compressed) compression unit block becomes a unit, and the image data forming the same compression unit block is continuously texture textures 5000-1 to 5000- 4 will be transferred.

Further, the texture cache 5000-1
The unit for managing which part of which texture image in the texture memory 7000 is copied by the image data stored in ˜5000-4 is a management block, which is composed of 8 × 8 compression unit blocks, that is, 32 × 32 pixels. That is,
The texture caches 5000-1 to 5000-4 hold, for each management block, information on which address in the texture memory 7000 the data stored in the texture caches 5000-1 to 5000-4 is image data.

Next, the compression method of the texture image used in this embodiment will be described with reference to FIG. One pixel in the texture image before compression is Red, Green,
It is composed of Blue (blue) and Alpha (pixel transparency) data. In the following, these four colors will be referred to as R, G, B and A.

As described above, in the present embodiment, the compression unit is 4 × 4 pixels. This compression method is for each R, G,
For each of B and A, two pixels representing a 4 × 4 pixel color that is a compression unit (for example, the darkest pixel is the first color, and the lightest pixel is the second color) are determined, and this is determined. 4 with 2 pixels
Approximate the color of × 4 pixels. Therefore, the compression information is R, G,
Representative 2 pixel color of B and A (8bit x 4 (R, G, B, A)
X2) and a selection signal of 1 bit for each pixel (4 (pixels) x
4 (pixels)). Hereinafter, this selection signal will be referred to as S. With this compression method, 4 × 4 × 32 bi per compression unit before compression
Information with t = 512 bits is 2 × 32 bits + 16b after compression
It becomes 80 bits. This compression is performed by the CPU1000,
Any of the geometry processor 3000 or the like may be used.

Next, referring to FIG. 4, the texture memory (70
00) and a method of storing a compressed texture image will be described.

In this embodiment, the texture memory 7000 is used.
Consists of 5 SDRAM chips, each of which has 512 column × 2048 raw (column address 9bi
t, raw address 11bit) 4bank (bank address 2bi
t) Configure. Each bank has 1 raw activated last
Minute information is held in the sense amplifier, and it is 1 when accessing 1 column (8bit) information on the sense amplifier.
6 cycles are required since the sense amplifiers are replaced in other cycles. When the compression information described above is stored in the texture memory 7000, the first color R,
The 8 bits of each of G, B, and A and the first 8 bits of the selection signal S (16 bits) are stored in the same address of the five SDRAM chips constituting the texture memory 7000, and the rest are stored as continuous column addresses. That is, the first
The chips are the representative first color R8bit and the second color R8bit
Are stored in consecutive addresses. Similarly, G, B, and A are stored in the second to fourth chips. The fifth chip stores the first half 8 bits and the second half 8 bits of S at consecutive addresses.
In this way, the same compression unit is divided into R, G, B, A, and S and stored in the same address of five chips. still,
This SDRAM chip is 8bi for 1 column of the same raw at the same time
The information of t can be read and written. Using 32 × 32 pixels of the texture as a management block, information (80 bits, 16it for each chip) obtained by compressing the 4 × 4 pixels therein is stored at consecutive addresses as described above. Also,
As shown in FIG. 4, the addresses are continuous in the direction of the arrow. Next, referring to FIG. 5, the texture cache 5000-
The configuration of the memory modules in 1 to 5000-4 and the method of storing the decompressed texture image will be described. Each texture cache 5000 is composed of eight memory modules, of which four memory modules store the decompressed textures independently.
Each memory module is 8 colomn × 256 raw (co
8 banks (ban of lumn address 3bit, raw address 8bit)
k address 3 bits). In addition, these memory modules are simultaneously used for one column of the same raw (16B, 128b).
It is explained below as being able to read and write information).

The 32 × 32 pixels of the texture are used as a management block, and 4 × 4 pixels (compression unit block) in the management block are used as 4 blocks.
The lower left 2 × 2 pixels are divided into the first and fifth modules (hereinafter a module), the lower right 2 × 2 pixels are divided into the second and sixth modules (hereinafter b module), and the upper left 2 × 2 is divided. The pixel is stored in the third and seventh modules (hereinafter referred to as the c module), and the upper right 2 × 2 pixel is stored in the fourth and eighth modules (hereinafter referred to as the d module). Also,
The compression unit horizontal row in the management block is the first bank in order from the bottom.
It is stored at the same raw address from the 8th bank to the 8th bank, and column addresses are continuous from left to right.

Similarly to the texture memory 7000, each memory module of the texture cache 5000 also stores each b.
Ank has 1 raw worth of information that was activated immediately before and is stored in the sense amplifier.
One cycle is required to access (128-bit) information, and six cycles are required because the sense amplifiers are replaced otherwise.

Next, the texture memory 700 will be described with reference to FIG.
The meaning and correspondence between 0 and the (byte) address of the memory module of the texture cache 5000 will be described. First, in the texture memory 7000, the lower 3 bits
Is a DRAM chip selection signal, the next 9 bits is a column address, the next 2 bits is a bank selection signal, and the highest 11 bits is ra.
w address. Here, the chip selection signal is 3 bits because there are five chips.

The lower 4 bits are the address in the compression unit block, the next 6 bits are the address of the compression unit block in the management block, and the upper 15 bits.
Means the address of the management block in the entire texture memory 7000. The fact that the address in the compression unit block is 1 bit for the column address corresponds to reading one compression unit block in two cycles.

In the memory module of the texture cache 5000, the lower 4 bits are the column address and the next 2
bit is a module selection signal, the next 3 bits is a column address, the next 3 bits is a bank selection signal, and the upper 9 bits are a raw address. The meaning is that the lower 2 bits are the intra-pixel address, the next 2 bits are the pixel address within 2 × 2 pixels,
The next 2 bits are 2 × in the compression unit block (4 × 4 pixels)
The 2-pixel address, the next 6 bits are the compression unit block address in the management block, and the upper 9 bits are the address of the management block in the entire texture cache (5000). Here, the pixel address, the pixel address within 2 × 2 pixels, and the 2 × 2 pixel address within the compression unit are combined.
The fact that it is within the address in the column and the module selection signal means that one compression unit can be read in one cycle.

The texture data is transferred from the texture memory 7000 to the texture cache 5000 in units of compression unit blocks. Therefore, in order to facilitate the correspondence relationship between the memory module of the texture cache 5000 and the information of the texture memory 7000, the compression unit block address or more in the management block in the memory module of the texture cache 5000 is compressed in the management block in the texture memory 7000. It is desirable to match with the unit block address or more, but since the memory space of the texture memory 7000 is larger, 6 bits cannot be associated.

Therefore, when the address information of the texture memory 7000 is held in the texture cache 5000, the upper 6 bits are lost, and it becomes impossible to know which part of the texture memory 7000 the information in the texture cache 5000 is a copy of. . Therefore, it is necessary to save this information separately, and it is stored in the tag table in the texture cache 5000 described later.

FIG. 14 shows an outline of data management in the texture cache. As shown in this figure, by adding an effective bit to each compression unit block which is a unit of storage transfer, and managing by address in a management block unit composed of a plurality of compression unit blocks,
A storage area for holding this address can be saved.

Next, referring to FIG. 7, the texture cache 5
000 will be described. However, since each memory control unit has exactly the same shape, only the signal line name relating to the memory control unit_1 5200_1 is given.

The address conversion unit 5300 has an internal register and holds the address of the origin of the texture currently used in the texture memory 7000 and the information of the width of the texture for each level of the mipmap. The address conversion unit 5300 receives the address with the decimal part and the signal line rp from the drawing processor 4000 via the signal line rp_tc_adr.
When the mipmap level is received via _tc_lev, it is converted into an address in the texture memory 7000 based on the value of the internal register.

When the texture request signal rp_tc_req is asserted from the drawing processor 4000, when each of the memory control units 5200_1 to 5200_4 can accept the request rp
The drawing processor 4000 is notified that _tc_ack is asserted to accept the request.

The address converted by the address conversion unit 5300 is divided into an integer part and a decimal part, and the integer part is signal line 50.
01 and the like through each of the memory control units 5200_1 to 5200
In _4, the decimal part is sent to the filter calculation unit 5900.
Also, the minority part of the mipmap level is sent to the filter calculation unit 5900.

For the address received from the address conversion unit 5300, the memory controller_1 5200_1 first confirms whether or not there is data corresponding to the received address in the Bufs 5400_1L and 5400_1R.
The Bufs 5400_1L and 5400_1R are both required when performing mipmaps, and neither of them is always required. Signal line 5 if all necessary information is available
008 is asserted to notify the filter calculation unit 5900.

If the required information is not present in buf 5400_1L and 5400_1R, memory module 1 5400_1L and memory module 2 540
Check if there is no data corresponding to the address received in 0_1R. In this case, the memory controller_1 52
00_1 refers to the tag table 5500 to check whether or not there is data corresponding to the received address. In the tag table 5500, for each management block, information indicating at which address of the texture memory 7000 the management block is a copy of data (specifically, the upper 6 bits of the address in the texture memory 7000) and the designated compression block are really Information (valid bit) indicating whether it is a part of the management block is held.
When referring to the tag table 5500, the signal line 5002
The address of the compression unit block (specifically, 15 bits which is equal to or more than the compression unit block address in the management block in the texture memory 7000) and a read request signal are transmitted through the compression unit block.
100_1L and memory module 2 5100_1R
Signal of whether or not it is present.

If the memory module 1 5100_1
If there is data corresponding to the received address in the L and memory module 2 5100_1T, the memory control unit _15200_1 determines the memory module 1 5100_1
Luf and the memory module 25100_1R are accessed to read desired data, send data to the signal line 5009, and confirm that the signal line 5009 becomes valid. Buf 5400_
Signal line 5006 to notify 1L and 5400_1R
Assert. However, the data of the signal line 5009 is Buf
Since the signal line 5006 has 2 bits because it is written in either 5400_1L or 5400_1R, it is controlled which one is written.

In the case of mipmap, Buf5400_1L
May be decided to be high level and Buf5400_1R to be low level etc.
One of f5400_1L and 5400_1R is replaced with the other data. In order to save this waste, either one can take over the current level.
For this purpose, a signal line is required to inform the filter calculation unit 5900 which is at a high level and which is at a low level.

If the required information is the memory module 1L
5100_1L and memory module 1R 5100
If it does not exist in _1R, the information is transferred from the texture memory via the texture memory manager 6000. The operation at that time will be described below.

First, the memory controller_1 5200_1 sends the address of the requested data to the signal line 5003, asserts the request signal line 5004, and notifies that the request is issued. Request signals collected from all memory control units are ORed and sent to the texture memory manager 6000 as tmm_c_req. That is, tmm_c_req is asserted if any one of the memory control units issues a request. The address selection unit 5600 selects the largest number of the requested addresses from the addresses collected from all the requesting memory control units based on the request signal, and selects from tc_mm_adr the texture memory manager 6000. Send to. If the highest number of addresses is not unique, then any of the highest numbers of addresses may be selected. In this case, each memory control unit 5200_1-5
It is sufficient to give priority to 200_4.

When the texture memory manager 6000 receives a request, the texture memory manager 6000 stores the requested data in the texture memory 70.
00 to read all texture caches 50
Data is sent from tmm_c_data and addresses are sent from tmm_c_adr to 00_1 to 5000_4, and tmm_c_ack is asserted. The texture decompression unit 5800 receives 80-bit data from tmm_c_data in two 40-bit portions,
Decompress the compressed texture data. When tmm_c_ack is asserted, the memory control units 5200_1 to 5200_4 have a 1/4 portion (for example, 1/4) of the texture data that the texture decompression unit 5800 has decompressed an address from tmm_c_adr from the signal line 5007.
In the case of the memory control unit 5200_1, the compression unit is 16 × 16.
The lower left four pixels in the pixel, and the upper right four pixels in the case of the memory control unit 5200_4) are read. However, the data returned by the texture memory manager 6000 and the address thereof are not always the requested data and its address. In other words, it may be data and its address according to the request of another texture cache. Further, the requests may be different among the four memory control units in one texture cache. Memory control unit 5200
The next operation of _1 depends on whether or not the requested address and the returned address are the same.

If the requested address and the returned address are the same, the texture memory manager 6
From the signal line 5009 to the Buf
Transfer to 5400_1L and 5400_1R and connect to signal line 50
06 that the signal line 5009 is validated, and which Buf is the data to be written,
From signal line 5008 to Buf 5400_1L and 5400_
Filter operation unit 5900 indicates that the contents of 1R have been updated.
Tell.

At the same time, this data is transferred to the memory module 1L 5100_1L or the memory module 1R.
5100_1R and rewrite the tag table 5500. However, since the tag table 5500 is commonly used by the four memory control units, it is necessary to unify which of the left and right memory modules the information of the same compression unit block is written between the four memory control units. Basically, if one memory controller is reading, it is efficient to write to the other memory controller, but all four memory controllers read from the memory module on the same side. Not always
Here, the memory controller_1 5200_1 performs the arbitration.

If the requested address and the returned address are not the same, the texture memory manager 6
The data received from 000 is written in the memory module 1L 5100_1L or the memory module 1R 5100_1R as described above, but Buf 5400_1L.
And 5400_1R are not transferred.

For each memory control unit, the data of the requested address is Buf 5400_1L and 5400_1.
Is in R or memory module 5100_1L and 51
The time required to prepare the data at the requested address depends on whether it is in 00_1R or needs to be read from the texture memory. For this reason,
Each Buf must hold a pixel value of at least 2 × 2 pixels, but in order to buffer the time required to prepare the data at the required address for each memory control unit described above, Have multiple pairs of pixel values of × 2 pixels (F
It is preferable to use IFO) from the viewpoint of performance improvement.

Finally, the filter calculation unit performs a filtering process such as trilinear on the basis of the content of each buf by using the update signal 5008 of the content of the buf sent from each memory control unit as a trigger, and generates a pixel value from rp_tc_data. , Again rp_t
A signal that c_data is valid is sent from the rp_tc_abl to the drawing processor 4000.

Next, the address conversion operation of the address conversion unit 5300 will be described with reference to FIG.

The address conversion unit holds the address and the width (at each level when the mipmap is used) of the origin of the texture currently used in the internal register. The origin address is the address of the management block in the entire texture memory, and the lower 10 bits of the address in the texture memory at the origin are all set to 0 at the 10th to 24th bits of the address in the texture memory.
Depending on the texture coordinates sent from the drawing processor 4000 with rp_tc_adr (the coordinates have the form (x, y)) and the mipmap level sent with rp_tc_lev, the address and its A signal indicating whether the address is a high level or a low level of the mipmap and a request signal are provided to the filter calculation section 5900 in a positional relationship between the decimal part of the mipmap level and the pixel value sent from each memory control section through buf. It gives a signal indicating whether there is one. Here, the case of applying a linear filter will be described.
For example, when the level is 2.3, the pixel value obtained by performing the bilinear filter processing on the level 2 mipmap reduced to 1/4 and the bilinear filter processing on the level 3 mipmap reduced to 1/8 The pixel value obtained by applying is synthesized based on 0.3 of the decimal part. That is, the integer part of the level is used to select the mipmaps and the fractional part is used to determine the compositing ratio between mipmaps.

FIG. 8A shows one compression unit block. The 2 × 2 pixels that the four memory control units are in charge of in order from the left are a, b, c, and d. Now, considering bilinear filter processing that linearly interpolates four peripheral pixels, if the requested texture coordinates are near the center of the compression unit block, one pixel can be generated using only the information of one compression unit block. However, it can be seen that in the vicinity of the peripheral portion, information of 2 to 4 blocks is required to generate one pixel. Further, in the non-hatched area of FIG. 8A, one pixel can be generated by the information of 2 × 2 pixels handled by one memory control unit.
In the other regions, information of 2 × 2 regions which is handled by two to four memory control units is required to generate one pixel. When the different cases of the processing form until one pixel is generated are listed, there are 16 cases distinguished by hatching in FIG. 8A. However, since the integer grid point of the coordinates is located at the center of the pixel, the origin of the compression unit block is also the position shown in the figure, and the bottom half-pixel width area is located on the compression unit block located one below. It is considered that the leftmost 1/2 pixel width region is connected to the right of the left compression unit block.

FIG. 8B is a schematic representation of this in FIG. 8B. In FIG. 8B, the area of 2 × 2 pixels handled by each memory control unit is surrounded by a thick line, and the boundaries of the pixels are shown by thin lines. The lower left 4 × 4 pixel is the compression unit block in which the requested texture coordinate exists, and the other upper and right regions are part of the adjacent compression unit blocks. The alphabet attached to every 2 × 2 pixels is 2
The memory control unit in charge of the area of × 2 is shown.

An area where Dx = 0 means that the compression unit block including the requested texture coordinates belongs to a compression unit block whose origin is the same x coordinate. Similarly, Dx = 1 is a compression unit block whose x coordinate is one larger,
Dy = 0 is a compression unit block having the same y coordinate, Dy =
1 means that the y coordinate belongs to the compression unit block which is one larger. Further, square marks such as (1) and (2) mean that the four pixels around them are bilinearly filtered. However, one memory control unit is in charge of 2 × 2
When a pixel is a filter target, it is written in the upper left as in (3).

The formula for converting texture coordinates into addresses is shown below.

A = O + {(W + 31) / 32 × y / 32 + x / 32} × 64 + {8 × (y% 32 + Dy) / 4 + (x% 32 + Dx) / 4} (Equation 1) Here, A is The converted address, O is the origin address of the texture, W is the width of the texture, and Dx and Dy are the same as the symbols described above. For example, when the requested texture coordinate is in the area of Dx = 0, Dx Is replaced by 0. Further, 32 is the width and height of the management block, 4 is the width and height of the compression unit block, and 64 is the number of compression unit blocks in one management unit block. However, (y% 32 + Dy) or (x% 32 + D
When x) becomes 32, it means that the boundary of the control block has been exceeded. In this case, (y% 32 + Dy) or (x% 32 + Dx) is replaced with 0 and 1 is added to y / 32 or x / 32. I will.

For example, when the square mark is at the position (1), since the four peripheral pixels are both in the area of Dx = 0 and Dy = 0, the addresses for the memory control units c and d are as follows.

O + {(W + 31) / 32 × y / 32 + x /
32} × 64 + {8 × (y% 32 + 0) / 4 + (x% 32+
0) / 4} Further, when the square mark is located at the position (2), the peripheral four pixels are in the region of Dx = 0, Dy = 0 and Dx = 0, Dy =
Since it is divided into one area, the addresses of the memory control units c and d are as follows.

O + {(W + 31) / 32 × y / 32 + x /
32} × 64 + {8 × (y% 32 + 0) / 4 + (x% 32+
0) / 4} The addresses of the memory control units a and b at this time are as follows.

O + {(W + 31) / 32 × y / 32 + x /
32} × 64 + {8 × (y% 32 + 1) / 4 + (x% 32+
0) / 4} FIG. 8 (c) is a summary of the positions of the requested texture coordinates and the processing to be performed for the positions using this schematic diagram. In this figure, the pixel boundary line is omitted. Also, only the necessary alphabetical symbols are entered. From FIG. 8C, for example, the remainder obtained by dividing the x coordinate of the requested texture coordinate by 4 is 3.0 or more and less than 4.0, and the y coordinate is 4.
If the remainder divided by is not less than 3.0 and less than 4.0, the address of a is as follows.

O + {(W + 31) / 32 × y / 32 + x /
32} × 64 + {8 × (y% 32 + 1) / 4 + (x% 32+
1) / 4} The address of b is as follows.

O + {(W + 31) / 32 × y / 32 + x /
32} × 64 + {8 × (y% 32 + 1) / 4 + (x% 32+
The address of 0) / 4} C is as follows.

O + {(W + 31) / 32 × y / 32 + x /
32} × 64 + {8 × (y% 32 + 0) / 4 + (x% 32+
The address of 1) / 4} d is as follows.

O + {(W + 31) / 32 × y / 32 + x /
32} × 64 + {8 × (y% 32 + 0) / 4 + (x% 32+
0) / 4} In addition, the filter operation unit receives a 4-bit signal indicating which of the 16 cases is the address conversion unit 3
From 500, appropriate 4 pixel filtering is performed accordingly. In the above case, the lower left pixel of the 2 × 2 pixels sent from the memory control unit a is the upper right, and the lower right pixel of the 2 × 2 pixels sent from the memory control unit b is the upper left. , The upper left pixel of the 2 × 2 pixels sent from the memory controller c is the lower right pixel, and the upper right pixel of the 2 × 2 pixels sent from the memory controller d is the lower left pixel. .

Next, the configuration and operation of the memory controller will be described with reference to FIG.

The memory control unit includes a control unit 5210 and two Bu
Holds the address of data existing in f5400
BufAd_1 5240, BufAd_2 5250, a memory I / F 5220 for interfacing with a memory module,
5230 and two memory modules and sel 5260 which selects the data fetched from the texture memory manager 6000 and sends it to the Buf 5400. The data of the address requested by the address conversion unit 5300 is paired into two memories. Reference the modules and if they do not exist they are fetched from the texture memory and set in the Buf 5400.

The control unit 5210 uses the address conversion unit 5200.
When it is possible to accept the request from, the acceptance signal is sent to the address conversion unit through the signal line 5001. Further, when it is acceptable, the control unit 5210 prepares the request signal sent from the address conversion unit 5200 through the signal line 5001 and the requested data for the request address and sends it to the Buf 5400.

FIG. 12 shows the processing of the control unit 5210, which will be described in detail below.

First, the control unit 5210 has already set the Buf 5400.
BufAd_1 5 if the requested data does not exist in
240, BufAd_2 5250. if,
If it exists, it informs the filter operation section via the signal line 5008 that the data of buf is valid.

If it does not exist, it is next necessary to check whether the requested data is stored in the memory module. Information about which address data is stored in the memory module is held in the tag table 5500, and the control unit 5210 inquires the tag table 5500 through the signal line 5002 whether the memory module has requested data.

If any one of the memory modules (for example, the memory module 1R 5100_1R has request data) and the memory I / F 5230 can accept the request, the control unit 5210 sends the request to the memory I / F 5230 through the signal line rreq 5201. If a read request signal is not accepted, the control unit 5210 waits until it can be accepted.Whether it is acceptable or not is determined from the memory I / F 5230 to the control unit 52 through the signal line 5202.
Informed to 10.

When the memory I / F 5230 receives the read request signal, it reads the requested data from the memory module 1R 5100_1L according to the address received from the signal line 5001. When the reading of the request data is completed, the memory I / F 5230 loads the request data into the signal line 5203 and sends a data valid signal to the control unit 5210 through the signal line TC_dtenbl 5204. Upon receiving the data valid signal, the control unit 5210 sends sel from the signal line 5206.
A signal for selecting the data from the memory I / F 5230 is sent to the 5260, and the sel 5260 responds to the memory I / F 5230.
/ F 5230 data from signal line 5009 to Buf
Output to 5400. At the same time, the control unit 5210 issues a Buf specification and a content update request to the pair of Bufs 5400 from the signal line 5006, and the designated Buf is sel5260.
Update the contents with the data sent from. When the content of buf is updated, the control unit 5210 notifies the filter calculation unit via the signal line 5008 that the data of Buf 5400 is valid.

If the requested data does not exist in either of the memory modules, the memory controller_1 520
0_1 sends the address of the requested data to the signal line 5003, asserts the request signal line 5004 to inform that the request is issued, and tmm_c_ad is asserted when tmm_c_ack is asserted.
The 1/4 portion of the texture data decompressed by the texture decompression unit 5800 from r to the signal line 5007 is written in the memory module, and the tag table 5500 is rewritten.

Regarding writing to the memory module, when the memory I / F 5230 can accept the request, the control unit 5210 sends a write request signal to the memory I / F 5230 through the signal line wreq5208. If it cannot be accepted, the control unit 5210 waits until it can be accepted. The control unit 5210 has an internal buffer in order to temporarily hold the data to be written when the data cannot be accepted. Whether or not it can be accepted is determined from the memory I / F 5230 through the signal line 5202 to the controller 52.
Informed to 10.

The next operation of the memory controller 5200_1 differs depending on whether the requested address and the returned address are the same.

If the requested address and the returned address are the same, the control unit 5210 sends the texture memory manager 60 to the sel 5260 from the signal line 5206.
A signal for selecting data from 00 is sent, and sel5260 transfers data from the texture memory manager 6000 to Buf5400_1L and 5400_1L through the signal line 5009 in response to the signal, and the signal line 5006 enables the signal line 5009. , Which Buf is the data to be written, and signal line 500
8 notifies the filter calculation unit 5900 that the contents of Buf 5400_1L and 5400_1R have been updated.

If the requested address and the returned address are not the same, the texture memory manager 6
Data received from the memory module 1 5100_1L or the memory module 5 as described above.
Write to 100_1R, but Buf5400_1L and 54
No transfer to 00_1R is performed.

Next, the tag table 550 will be described with reference to FIG.
The configuration and operation of 0 will be described. Tag table 550
0 is designated as a frame address table 5520 for holding information (specifically, the upper 6 bits of the address in the texture memory 7000) of which address in the texture memory 7000 the management block is for each management block. It consists of a valid bit table 5530 holding information (valid bit) indicating whether or not the compressed block is really a part of the management block, and a tag table control unit 5510 for controlling reading and writing to these tables.

Here, two frame address tables 5520 and two effective bit tables 5530 are provided for each pair of memory modules.

The memory control unit 5200 makes the tag table 55
The operation when referring to 00 will be described.

The memory control unit 5200 makes the tag table 55
When referring to 00, the address of the compression unit block in the texture memory 7000 (specifically, 15 bits which is equal to or more than the compression unit block address in the management block in the texture memory 7000) and the read request signal are sent through the signal line 5002. The tag table control unit 5510 refers to the frame address table 5520 by using the lower 9 bits (management block address in the texture cache) of the address, and stores the upper 6 bits of the address and the frame address table 5520 in the texture memory 7000. Compare the upper 6 bits of the address.

When the comparison results are in agreement, it is expressed as K = 1, and when they are not in agreement, it is expressed as K = 0.

At the same time, the tag table control unit 5510
Is stored by referring to the effective bit table 5530 using the address of the compression unit block in the texture memory 7000 sent through the signal line 5502.
Get bit information (hereinafter referred to as V).

V is information (valid bit) indicating whether or not the designated compression unit block is a part of the management block indicated by the frame address table 5520. That is, when V = 1, the compression unit block is a part of the management block, and when D = 0, it is not a part of the management block.

The compression unit block is held in the memory module only when K = 1 and V = 0. At this time, the tag table control unit 5510 causes the signal line 50 to operate.
Through 02, it notifies the memory control unit 5200 that the compression unit block is held in the memory module, and otherwise notifies that it is not held.

Next, the operation when the memory control unit 5200 rewrites the tag table 5500 will be described.

The memory control unit 5200 makes the tag table 55
When 00 is rewritten, the address of the compression unit block in the texture memory 7000 (specifically, 15 bits which is equal to or more than the compression unit block address in the management block in the texture memory 7000) and a write request signal are sent through the signal line 5002.

The tag table control unit 5510 uses the lower 9 bits (texture cache management block address) of the address to generate a frame address table (552).
0) and compares the upper 6 bits of the address with the upper 6 bits of the address in the texture memory 7000 held in the frame address table 5520.

When the comparison results do not match, the upper 6 bits of the address in the texture memory 7000, which are held in the frame address table 5520, are set to the upper 6 bits of the address of the compression unit block newly stored in the memory module in the texture memory 7000. Valid bits corresponding to all the compression unit blocks (excluding only the compression unit block newly stored in the memory module this time) having the address used when rewriting and referring to the frame address table 5520 as the management block address in the texture cache Are all rewritten to V = 0. (The valid bit corresponding to the compression unit block newly stored in the memory module this time is set to V = 1.) When the comparison results match, the frame address table 5520 is not rewritten and is newly stored in the memory module this time. The valid bit corresponding to the compression unit block is rewritten to V = 1.

As described above, not all the addresses in the texture memory 7000 (upper memory) are held for each compression unit block which is a transfer unit, but for each management block in which the compression unit blocks are grouped into 8 × 8 or the like. Hold on,
The capacity of the tag table can be reduced by having an effective bit for each compression unit block which is a transfer unit.

Next, the structure and operation of the texture memory manager 6000 will be described with reference to FIG. The texture memory manager 6000 receives the addresses of the compression unit blocks for which transfer requests have been made from the texture caches 5000-1 to 5000-4, and selects which request is to be satisfied, and the five chips forming the texture memory 7000. And a TMM control unit 6100 for controlling them.

Texture cache 5000-1 to 50
00-4 is a block selector 6 through the signal line tc_mm_adr
At the same time as sending the address of the requested compression unit block to 200, a request signal is sent through the signal line tc_mm_req.

The block selection unit 6200 sends any one of these requests to the TMM control unit 6100. As one of the selection methods, for example, the most requested one may be selected, and if there is the same number, the selection may be made based on a predetermined priority order.

The TMM control unit 6100 reads the address sent from the block selection unit 6200 if any one of the texture caches 5000-1 to 5000-4 has issued a request.
~ 6300-5 is sent an address through the signal line tm_adr and a request signal through the signal line tm_req. Also, for the texture caches 5000-1 to 5000-4, the signal line
The address selected through tmm_c_adr is set to the signal line tmm_
Signal that the request has been accepted via c_ack.

Based on the address sent from the TMM control unit 6100, the TM control units 630-1 to 6300-5 successively read out 8-bit data of consecutive addresses from the chip of the texture memory 7000 which they are in charge of twice. At this time, the address (except the chip selection signal) is sent through tmm_m_adr and control is performed through tmm_m_cnt.

The TM control units 630-1 to 6300-5 receive the data received from the texture memory 7000 through the signal line tmm_c_data and the texture cache 5000-.
1 to 5000-4.

When there is a writing request from the geometry processor to the texture memory 7000, the TMM control unit 6100 receives it, and thereafter the same as above.
The 6100 issues a write request to the TM control units 630-1 to 6300-5, and the TM control units 630-1 to 6300-5 write to the texture memory 7000.

A plurality of texture caches 5000
-1 to 5000-4 do not always request the same image data. At this time, texture memory manager 60
The block selection unit 6200 of 00 controls the demands for a plurality of different compressed blocks according to the demand for the texture cache having the longest waiting period, thereby equalizing the variations in the processing speed of the rendering processors. be able to.

[0100]

As described above in detail, according to the present invention, it is possible to realize a graphics system capable of improving the use efficiency of the memory and processing at high speed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a graphics system.

FIG. 2 is a diagram for explaining a block configuration of a texture image.

FIG. 3 is a diagram for explaining a compression method of a texture image.

FIG. 4 is a diagram showing a configuration of a texture memory.

FIG. 5 is a diagram showing a configuration of a texture cache.

FIG. 6 is a diagram showing addressing of a texture memory and a texture cache memory.

FIG. 7 is a diagram showing a configuration of a texture cache.

FIG. 8 is a diagram for explaining an address conversion method.

FIG. 9 is a diagram showing a configuration of a memory control unit.

FIG. 10 is a diagram showing a configuration of a tag table.

FIG. 11 is a diagram showing a configuration of a texture memory manager.

FIG. 12 is a diagram showing an operation of a memory control unit.

FIG. 13 is a diagram showing locality between processors.

FIG. 14 is a diagram showing a configuration of stored data in a cache memory.

[Explanation of symbols]

0000 ... Display device, 1000 ... CPU, 2000 ... Main memory MM, 3000 ... Geometry processor, 400
0-1 to 4000-4 ... Drawing processor, 5000-1 to 5
000-4 ... Texture cache, 6000 ... Texture memory manager, 7000 ... Texture memory,
8000-1 to 8000-4 ... Frame memory FM.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuhisa Takami 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Kazunori Oniki 5-2, Omika-cho, Hitachi-shi, Ibaraki No. 1 Hitachi Ltd. Omika Plant (56) Reference JP 10-307925 (JP, A) JP 10-27132 (JP, A) JP 10-11594 (JP, A) JP 9-292927 (JP, A) JP 9-282231 (JP, A) JP 9-212654 (JP, A) JP 9-198306 (JP, A) JP 9-102047 (JP, A) JP-A-8-328954 (JP, A) JP-A-8-138080 (JP, A) JP-A-7-85308 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) ) G06T 15/00 300 G06F 12/08 JISST file (JOI )

Claims (4)

(57) [Claims] 1. A CPU, a memory for storing a plurality of types of texture images, a plurality of drawing processors for mapping a texture image on a figure generated based on a command sent from the CPU, and each of the drawing processors. A plurality of cache memories that are connected to the cache memory for storing texture images processed by the drawing processor, and are connected to the memory and the plurality of cache memories, and from the memory to the cache memory in response to a request from the cache memory. In a graphic processing system having a transfer device for transferring a texture image to, the transfer device selects one request from a plurality of requests from the cache memory, and all texture images corresponding to this request are transferred from the memory. Transfer to the above cache memory Graphics system which is characterized. 2. The graphics system according to claim 1, wherein the transfer device transfers the most requested texture image out of a plurality of requests from the cache memory from the memory to all the cache memories. 3. The texture image stored in the memory according to claim 1, wherein the texture image is a compressed texture image, and each of the cache memories expands the texture image transferred from the memory. A graphics system having a decompression unit and storing a decompressed texture image. 4. The graphics system according to claim 3, wherein the texture cache has a filter operation unit for performing texture filtering.