KR20070038955A - Cash memory managemnet system and methods - Google Patents

Abstract

A cache memory method for two-dimensional data processing and a corresponding system, which includes two-dimensional image processing by simultaneous coordinate transformation. This method uses a wide and fast primary cache memory (PCM) device and a deep secondary cache memory (SCM) device, which contains multiple banks so that each device can access data simultaneously. The provided prefetch logic was used to receive pixel data from an external memory capable of receiving control variables from the external processor system PU1 and to provide this data to the PCM based on the secondary control queue. This data is then prepared in a constant block size and format and stored in the PCM based on the primary control queue prefetch at the optimized size. The prepared data is then read by another external processor system (PU2) for processing. Cache control logic ensures consistency of data and control variables at the input of PU2.

Description

Cache Memory Management System and Method {CASH MEMORY MANAGEMNET SYSTEM AND METHODS}

The present invention relates to a cache memory structure and management related to digital data processing, and more particularly, to digital image data processing.

Because of the invention of new computer systems, there has always been competition for faster processing and faster systems. Faster processing has been achieved by an explosive increase in clock speed. Naturally, the amount of data and commands has likewise increased rapidly. In computer systems, storage devices such as ROM (read only memory) for storing data instructions and burst-based storage devices such as DRAM are dramatically increased in capacity. Architecturally, large memory space is deep and can slow the processor to access data and instructions in memory. These problems have led to the need for more efficient memory management, cache memory creation, and cache memory structure. Cache memory is generally shallow and wide memory that resides within or in proximity to the processor to allow access to the data and the device processor for changing the content of the data. The basics of cache memory management are to store frequently used copies of data and instructions to be stored in the processor in the near future. This makes the processor accessing data and instructions many times faster than accessing it from external memory. However, this task must be done carefully, and the contents of cache memory and external memory must be harmonized. These themes have led to the creation of techniques to manage and manage cache memory in accordance with hardware and software characteristics.

As mentioned, cache memory supplements by copying data and addresses that the processor is likely to access next. External memory usually requires re-entry cycles to hold the data in the resistor and recharge the resistor to prevent loss of data. However, a typical cache memory uses eight transistors represented by one bit, eliminating the need for re-entry cycles. Therefore, cache memory can store data whose unit size is much smaller than that of external memory. Therefore, carefully select data and instructions to optimize cache operations.

Different approaches and protocols have been used to optimize cache memory operations. The best known of these methods is direct mapping, associative mapping and set associative mapping. Such protocols are familiar to people. They use operations for general purposes, including data processing, web-based applications, and so on. In U.S. Patent No. 4,295,193 to Pomerene, a computing device for simultaneous execution of instructions via a double instruction has been filed. This is the earliest patent that includes cache memory, address generators, instruction registers and pipelining. Matsuo has applied for a microprocessor in US Pat. No. 4,796,175 that includes an instruction queue for prefetch instructions in the form of a main memory and an instruction cache. Stills filed Branch Predictive Cache (BPC) as a hybrid cache structure in US Pat. No. 6,067,616. It is. Frank filed for a cache management system in a computer system in US Pat. No. 6,654,856, which emphasizes the address-view cyclic structure of the cache memory structure.

Liao filed a microprocessor with a control unit and a cache in US Pat. No. 6,681,296, which was divided into optional or single or fixed and normal parts. Arimmilli patents US Pat. No. 6,721,856 for a cache for coherency state and system control for each row having a different subentry for different processors containing a processor access sequence. U. S. Patent No. 6,629, 188 includes a plurality of primary and secondary cache memories of storage space. U. S. Patent No. 6,339, 428 includes a cache device in a video graphic that receives compressed texture information and operates to decompress texture. US Pat. No. 6,353,438 includes a cache combination that maps multiple tiles of a texture and data directly to the cache.

Each of the above inventions provides specific advantages. Effective cache structures and policies depend closely on the immediate availability of a particular application. For digital video applications, high quality real-time digital image processing is one of the biggest challenges in this field. In particular, people want to perform detailed two-dimensional image processing by nonlinear coordinate transformation. Dedicated and professional systems therefore require special advantages of fast access while maintaining data consistency. Therefore, it is necessary to optimize the cache structure and cache management policy for these applications.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows the overall plan of a cache system made in accordance with the present invention;

2 shows a detailed structure of a cache system made in accordance with the present invention;

3 shows an example of a block structure of input data to be cached;

4 illustrates the general structure of a primary cache system made in accordance with the present invention;

5 shows the general structure of a secondary cache system made in accordance with the present invention; And,

Figure 6 illustrates the logic flow of a cache system made in accordance with the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In one aspect, the present invention provides a method for cache memory management and structure of digital data processing, in particular, digital image processing, and particularly includes the following apparatus.

a) an external memory in which data to be accessed and processed is stored;

b) a plurality of processor units PU1 for generating control commands and generating memory addresses and control variables of data to be processed in the external memory; And

c) multiple processor units (PU2) to process data;

This method is;

(i) a deep secondary cache memory (SCM) having a plurality of banks having a plurality of storage lines for reading data from the external memory and having a large storage capacity;

(ii) a fast and wide primary cache memory (PCM) having a plurality of banks having several storage lines for reading data by the PU2, and having low storage capacity; And

(iii) using a cache structure that provides control of prefetching and cache, and includes control logic including a control stage and a control queue,

When PU1 receives address sequence and control parameters, it accesses data from external memory, prepares data for fast access and processing by PU2, and then goes through the following steps to achieve cache consistency and hide memory read delays. Characterized in that the method.

(a) identifying a data block to be processed in an external memory based on the form and structure of the processing operation network of the PU2;

(b) create a sufficiently large SCM control queue based on the results of (a) and determine whether the data is in the PCM, so that the SCM can access data in external memory much faster than it is processed by PU2. Doing;

(c) Simultaneously reading input data blocks from a plurality of banks of the SCM at a predetermined number of clock cycles, extracting and reformatting the external memory data from the cache data organization, extracting this data, and hiding the external data organization from the PU2. Increasing the data processing rate in PU2;

(d) generating PCM control queues large enough to store the extracted data in the PCM before the data needed by the PU2 based on the results of (a) and (b); And

(e) synchronizing the arrival of data and control parameters in the PU2 to maintain cache coherency.

In another aspect, the present invention provides a cache system based on what has been described above.

Further details of other aspects and advantages as the invention is embodied will appear in the following description of the accompanying drawings.

DETAILED DESCRIPTION OF EMBODIMENTS The following detailed description of the invention according to the accompanying drawings and typical methods. The present invention relates to cache structure and management. The given example, given in this description, relates to image processing via co-ordinate transformations. However, one of ordinary skill in the art will recognize that the scope of this invention is not limited to this particular example. This involves all sorts of digital data processing, which refers to attempts by multiple processors to fetch control parameters from other processors of some form with data and external memory. In particular, the two-dimensional (2D) image transformation example, given herein, can be easily changed to any 2D data transformation without departing from the scope of the present invention. Therefore, in the future, the data will be referred to as image pixel data. Many processors that issue control parameters that take into account the structure of the input data and the shape of the network will be referred to as the geometry engine. In addition, a number of processors that access data for an operation will be referred to as a filter engine, and the corresponding operation will be referred to as filtering.

Figure 1 made in accordance with the present invention graphically illustrates an example of the configuration of the cache system 100, designed for digital data processing including simultaneous coordinate transformations within the computing device. The cache system 100 interfaces with two sets of processors. The first plurality of processors, in the method of this example, consists of a geometry engine 300, and the second plurality of processors consists of a filter engine. In addition to these two engines, cache system 100 interfaces with external memory 700, which may be any memory having an access time delay. The cache system 100 receives a control parameter including a coordinate transformation as well as a filter width parameter in the geometry engine 300. It simultaneously accepts pixel data from the external memory 700. The cache system 100 provides these data to the filter engine 500 in a manner that optimizes the filtering process with minimal stalling of the filter engine 500.

In secondary (2D) data processing, digital image data processing, comprehensive filtering or sampling functions are required in particular. In the future, we will cover a special example of 2D image processing; The word "image" will therefore be used as a special case of any 2D data. In 2D digital image processing, each output image is formed based on a lot of input image information. First, output image coordinates are displayed over input image coordinates. This is the coordinate transformation, usually done electronically via image wrapping techniques. Once the central input image is determined, the filtering or sampling function needs to generate the output image specification, i.e., the intensity of the color components and other information such as the sampling format and the mixing function. The area including all the images around the center input image and the place where sampling is performed are called the filter bottom width. It is well known in this field that the size and shape of the filter footprint affect the quality of the output image.

The function of the cache system 100 is to use a prefetch logic that allows for a sufficient random access of the dedicated structure and sufficient random access image data and control parameters to the filter engine 500, thereby minimizing stall Allows the ring to process data at a given clock rate. With the read request queue of the optimized size, the cache system 100 can hide most of the memory read time delay inherent in the external memory 700 from which the pixel data is fetched. This memory read time delay is excellent for filter performance. If this time delay is not adequately concealed, the filter engine 500 will not have maximum power. The allowable stalling amount is a design parameter. In order to obtain the required output, it is necessary to adjust different parameters in exchange for hardware costs.

In addition, the cache system 100 provides coordinate transformations, filter footing parameters, and control paths for reading from the geometry engine 300. The cache system 100 allows the pixel data from the external memory 700 to be synchronized on the one hand and the control data from the geometry engine 300 to the filter engine 500 on the other hand.

In this specification, the quantity (eg, 64 bytes) is conventionally indicated in Italian to distinguish it from the reference number (eg, the filter engine 500).

2 illustrates a detailed structure of the cache system 100 in the drawing. For each output pixel, the cache system 100 receives certain control parameters from the geometry engine 300. This parameter contains additional control parameters including the map coordinates of the input pixel, U and V, and the shape, rotation and size of the filter footprint. At the same time, the cache system 100 receives the pixel data for each pixel included in the filter width from the external memory 700. These data include the intensity of the color component in the color space, i.e. RGB or YCrCb, the sampling format, i.e. 4: 4: 4 or 4: 2: 2, and with or without the blending function, in other words.

The structure of the cache system 100 is related to dividing the input image by the block size of m x n pixels. 3 shows a special example of the input video pixel block structure, where n = 8 and m = 4. The input image 330 is grouped into blocks, for example, 1024x1024, including a certain number of pixels. Each input pixel block 332 contains an m x n input pixel 334. In different filtering schemes, the structure of the block is generally a function of the shape and size of the footprint.

The cache system 100 fetches data related to the mxn input pixel block 332 and generates a data block useful for the filter engine 500. In doing so, the system must determine which blocks fall within the footprint and which pixels within the blocks must be included for filtering. The structure of the cache system 100 can be scaled to fit the input data structure. In general, the structure of the cache system 100 is a function of the nature and operation of the filter engine 500. In the special case of image processing, the structure of the operation and the shape of the network is defined in part by the filter footprint.

Referring to the example diagram of FIG. 2, the cache system 100 is a shallow and wide but low capacity primary cache 110 and deep and high capacity secondary cache 120, block containing stage 150, block data generation stage 130, a primary cache control stage 170, and a secondary cache control stage 190. There is also a large number of queues in the cache system, which will be described later herein. The pixel data is first read from the external memory 700 into the secondary cache memory 120. These data will then be reformatted and decompressed by the block generation stage 130 for use in the filter engine 500. These reformatted data are placed in a queue and placed in the primary cache 110 at an appropriate time for immediate access by the filter engine 500. The data path and control logic structure will be described below respectively.

Referring now to the example diagram of FIG. 5, the secondary cache 120 is a high capacity storage device that reads unprocessed data from the external memory 700. The pixel data in the external memory 700 is stored in a certain format, which is generally not suitable for processing within the filter engine 500, for example, as a special case, the data is stored sequentially in the scan line order. The secondary cache 120 is designed to read these data efficiently with minimal interference.

Each line in the secondary cache is designed to accommodate a full b2 bytes of data from external memory 700. For this reason, each line in the secondary cache 120 is sized according to the structure and read requirements of the external memory 700. Each line in the secondary cache 120 where the data is stored is also a design parameter that allows for optimization to reduce miss counts in the secondary cache calculation. The secondary cache 120 is lined up to allow sufficient read output to update the primary cache 110 to minimize stalling of the filter engine 500. Because many nearby pixels are needed to sample the central input pixel, these design parameters play a crucial role in storing enough data for pixel processing by the filter engine 500.

Thus, the secondary cache 120 is designed to have a certain number of banks with independent access lines to simultaneously read data from the external memory 700. As shown in the example figure of FIG. 5, the secondary cache 120 consists of several banks 122, each of which has a certain number of lines 124. Each secondary cache line contains data read from external memory 700. These data will eventually be read by the filter engine 500. In so doing, several secondary cache banks will be designed as a function of the data output. With the mxn input block structure and the required clock cycle Nc, n / Nc banks are needed in the secondary cache 120 to read the data. As a special tool, a combination of computer least significant bits (LSB) U and V is used to distribute data between secondary cachebanks. This reduces the complexity of the decoding logic, saving area and making updates faster. To divide each bank into parts of 2i, i LSB is used. If the second line, if this 2j of each cache bank ^{(122), 2 j / 2} i set combination divalent primary cache structure is created. This design, which will be described later in accordance with cache logic, with the appropriate replacement policy for the secondary cache 120, leads to a simple and efficient partitioning for distributing data through the secondary cache 120.

Once data is read from the external memory 700 into the secondary cache 120, these data must be converted into a format that can be used by the filter engine 500. The block generation stage 130 reads the data in the secondary cache 120 and prepares these data in a block containing all the data in the m x n input pixel block. As described above, block generation stage 130 reads from the n / Nc lines of secondary cache 120 every clock cycle. By doing this, within each Nc clock cycle, all data associated with one input pixel block is read simultaneously. Depending on the packing format of the data and the output requirements, multiple reads from the secondary cache 120 are required to generate the input pixel block. In addition to reading these data, block generation stage 130 will be adapted to reformat and decompress these data into a format that can be used directly with filter engine 500. The block generation stage 130 thus hides the original pixel data format and can be compressed in various compression forms. This demonstrates that the filter engine 500 solves the pixel data in the external memory 700 and solves the packet of original formatted data in the block to be used for filtering. These block data are stored in the primary cache 110 which is eventually read by the filter engine 500.

Referring to the example diagram of FIG. 4, the primary cache 110 is designed to optimize the data access rate in the filter engine 500. By doing so, it has a shallow but wide structure that can be accessed by multiple lines. The primary cache 110 is divided into a certain number of banks, and each primary cache bank 112 is read independently and simultaneously by the filter engine 500. The number of primary cache banks is determined by experimental data and simulations to optimize filtering performance. Each primary cache bank 112 contains a certain number of primary cache lines. Each primary cache line 114 contains data from the entire m x n input data block. In so doing, for the primary cache bank of b1, filter engine 500 reads the data containing the b1 input block per cycle in a suitable format. This is significant, in the case of sampling, many input blocks are required around the input pixels and if they are not provided to the filter engine 500, a delay occurs. The amount and period of stalling determines the output efficiency.

In order to distribute the data to different primary cache banks, LSB, U and V, of the input pixel coordinates are used. Each primary bank 112 in primary cache 110 is also divided into a certain number of portions. As described above, a certain number of LSBs are used again for data distribution in different primary cache banks 112. Within the remaining bits of the input pixel U and V addresses, more LSBs are again used to distribute the data in each primary cachebank 112. Jinde been used to 2f of the first line and the g LSB separates the respective banks per cache bank, when this separation 2 ^f / 2 is made a set combination of structure ^g.

This design is used with a suitable replacement policy, described later, for the primary cache 110 to obtain optimal output. As the amount of input data increases, more bits are used in the U and V addresses, so this structure can be scaled in a simple and natural way. In order to ensure the presence of data in a format usable when the filter engine 500 requires, a prefetch logic structure is designed. 6 illustrates cache logic 400. This logical structure allows the secondary cache 120 to read data from the external memory 700 and read and reformat the data in the block generation stage 130 and to store the data blocks in the primary cache 110. To control.

In step 402, it is determined which block of data is needed for sampling, based on the control parameters received from the geometry engine 300. Once the data is verified, it is determined at step 410 whether these data exist in the primary cache. If present, an entry is written to the primary control queue at step 412 and the addresses of these data are sent to the filter engine at step 414. If the data is not in the primary cache, then at step 415, the primary cache line to be replaced is determined in accordance with the replacement policy described later. The address of this primary cache line is then written to the primary control queue in step 416 and sent to the filter engine in step 418. It will then be determined whether these data exist in the secondary cache at step 420. If the data is not there, it will be determined in step 422 which cache line to replace. A read request will then be sent to external memory to fetch the data to be read later into the secondary cache at step 426. If the data is in the secondary cache, the entry will be written to the secondary cache control queue at step 428.

In both cases, secondary cache data is read after the data is fetched from external memory, or secondary cache is missed, in step 440 to read the block for block generation. Here data is read from the plurality of secondary cache banks, reformatted and decompressed in step 442. At this stage, in step 450, an input data block of the appropriate format is sent to the queue to be stored in the primary cache.

The update of the primary cache 110 occurs when associated control data is read from the primary control queue 212 and the pixel control queue 218. This allows cache coherency to be maintained within primary cache 100. At this time, the data read into the primary cache while maintaining control parameter consistency is input to the filter engine in step 510.

2, a hardware device will be described in the cache control logic 400. The block inclusion stage 150 is the starting point of the control logic. The device accepts, for each output pixel, a control parameter from the geometry engine 300 containing the mapping coordinates of the input pixel and the shape of the filter footprint. Based on input coordinates, U and V, and footprint geometry, and other control parameters, block inclusion logic determines which input blocks are needed for each output pixel processing and which pixels in the block are required for sampling.

The block containing stage 150 compares the coordinate positions of the neighboring blocks, including the shape of the base, to include the block of pixels required for sampling in one example of the invention. Block inclusion logic generates k blocks per clock cycle with each block having one U or V value that is at least the least significant bit in each block address. This ensures that the k combination of LSBs will be present in each block set by block inclusion logic. This constraint is used to distribute blocks between primary cache banks. The number of blocks generated every clock cycle, k, is a function of the size of the floor, and the phase of the block is a function of the shape of the floor. These parameters should be considered in the design of the cache system related to the data processing in the filter engine 500 with careful simulation and experimentation. The pixel control queue 218, generated by the block inclusion stage 150, is sent to the filter engine 500 before allowing the filter engine 500 to generate the scaling parameters ahead of the actual pixel data.

The primary cache control stage 170 provides control logic for processing data in the primary cache 110. For each input block determined by the block inclusion stage 150, the primary cache control 170 checks whether the block exists in the primary cache 110. If data exists, it is called a cache hit. If not present, a cache miss is recorded and a miss flag is sent to secondary cache control 190. The primary cache control stage 170 writes an entry to the primary control queue 212 that not only indicates whether there was a primary cache hit or miss, but also points to the address of the data in the primary cache 110. The primary control queue 212 is read by the filter engine 500 based on the FIFO. If the cache miss flag is raised in one of the entries, the filter engine 500 sends a read request to the block queue 214 to update the primary cache 110.

In the case of primary cache mismatch, this happens when a data block does not exist in the primary cache 110, and this happens when the U or V address does not match in all the blocks examined, or the associated valid bits are not set. This primary cache miss is called. The control logic in the secondary cache control stage 190 determines the stage in which to generate an m x n block to be written to the primary cache, with the primary cache miss flag received. The secondary cache control stage 190 will first determine whether the data is in the secondary cache 120. This will yield a secondary cache hit or a secondary cache miss. If a secondary cache miss occurs, the secondary cache control 190 issues a read request to the external memory 700 to fetch the data read from the external memory 700 to the secondary cache 120. And write an entry to the secondary control queue 216. If a secondary cache hit occurs, the secondary cache control stage 190 only writes an entry to the secondary control queue 216 without sending a read request, which entry is based on the FIFO and the block generation stage 130. Will be read by

After receiving each cue entry, block generation stage 130 reads raw data associated with the entire input block from secondary cache 120. These data will then be reformatted in the block generation stage 130 and formatted for use by the filter engine 500 soon. Depending on the data packing mode, the plurality of secondary cache lines will probably need to create the primary cache line 114. After obtaining all the data related to one input block and reformatting these data, block generation stage 130 writes an entry to block queue 214. Thus, each block queue entry contains all the data from the entire input block in the proper format. Block queue entries then begin to be received in the primary cache 110 where they are stored for immediate access by the filter engine 500. Thus, block queue 214 allows secondary cache 120 to run prior to filter engine 500.

It should be noted that the functionality of the cache system 100 is based on the identity and control parameters of the pixel data in addition to the prefetch logic provided. No data is read by the secondary cache 120 unless there is a request from the secondary cache control stage 190. Once such data is in the secondary cache, only entries in the secondary control queue 216 can determine whether these data are required for block generation in block generation stage 130. Once the data blocks are created, they are queued and stored in the primary cache 110 only by a read request from the filter engine 500, which is triggered by an entry in the primary control queue 212 itself. It is done. Moreover, the filter engine waits for the arrival of both pixel data as well as control parameters from two independent queues before processing the data.

Depending on the relative size of the filter footprint and the cache storage space, it may be necessary to divide the footprint into subsections and process each subsection sequentially. This size is predicted according to the design of the cache system 100 for dynamic size footprints. Once the data associated with each lower footprint is cached, the filter engine processes these data sequentially.

To evaluate the effect of data prefetching using the cache system 100 to hide the memory read time delay, it was benchmarked in one example of the invention that the read time delays were in the order of 128 clock cycles. By supplying a sufficiently large cue, almost all time delays are hidden. In the present invention, the size of the queues can be adjusted to match the memory read time delay seen in the system, so that they can adjust the design parameters based on system specifications.

Once the cache logical structure determines that certain data blocks should be read by the secondary cache 120 or prepared to be stored in the primary cache 110, a replacement policy is needed. One existing primary cache line 114 or a plurality of secondary cache lines 124 need to be replaced. In the example of the present invention, the cache replacement policy is based on distance. According to the input block addresses U and V, the primary cache control stage 170 and the secondary cache control stage 190 compare the central input pixel U and V coordinates in the cache line with the coordinate values of the existing block. The entry farthest from the center input pixel is replaced. This policy stems from the fact that the closer the central pixel is, the higher the probability that sampling calculations will require.

In another example of the present invention, the cache replacement policy is based on least recently used (LRU). At the end of this example, the primary cache control stage 170 and the secondary cache control stage 190 choose to replace the least recently used cache line.

The design of the cache system 100 has only a few dimensions to ensure that the system is resizable. The size of the secondary cache line can be adjusted according to the memory read size, that is, burst size, from the external memory 700 and the block generation rate. The number of secondary cache lines can be scaled according to the cache efficiency required. The number of secondary cache banks can be scaled according to the required input block data structure and the number of clock cycles due to accesses leaving the secondary cache. Sizing of the secondary cache 120 is based on the required size and cache system efficiency, i.e., the amount of input digital data to be read back.

The number of blocks generated per clock cycle in the block inclusion stage 150 may be scaled according to the filtering algorithm, the size of the width, and the output required. The partitioning of the primary cache 110 and the secondary cache 120 can be adapted to the size of the cache based on U and V, which are input pixels LSB. This translates to the number of bits used for the particular division. The size of the primary cache line can be scaled based on the input block size. The number of primary cache banks can be scaled based on the filtering output. Different queue sizes can also be scaled based on parameters based on the output needed versus memory time delay. These sizes are determined based on simulations and experiments.

All these design parameters must carefully consider the price-to-performance ratio. Therefore, careful simulation and experimentation have been done to optimize the cache solution in the special case that is always available for the particular device of the present invention.

While certain features of the invention have been illustrated and described in this article, numerous modifications, substitutions, changes, etc. have occurred in light of the original art in the art. It is, therefore, to be understood that the appended claims are intended to embrace all such changes and changes in accordance with the true spirit of the invention.

Claims (34)

In the data processing, specifically the method for the cache structure and management in the two-dimensional image processing by the coordinate coordinate conversion: a) an external memory in which data to be accessed and processed is stored; b) a plurality of processor units PU1 for generating control commands and generating memory addresses and control variables of data to be processed in the external memory; And c) in the apparatus consisting of a plurality of processor units (PU2) to process data; (i) a deep secondary cache memory (SCM) having a plurality of banks having a plurality of storage lines for reading data from the external memory and having a large storage capacity; (ii) a fast and wide primary cache memory (PCM) having a plurality of banks having several storage lines for reading data by the PU2, and having low storage capacity; And (iii) using a cache system that provides control of prefetching and cache, and includes control logic including control stages and control queues, Upon receiving the address sequence and control parameters from the PU1, access the data from the external memory, prepare the data for fast access and processing by the PU2, and follow the steps below to achieve cache coherency and read memory. Hiding the delay. (a) identifying a data block to be processed in an external memory based on the form and structure of the processing operation network of the PU2; (b) create a sufficiently large SCM control queue based on the results of (a) and determine whether the data is in the PCM, so that the SCM can access data in external memory much faster than it is processed by PU2. Doing; (c) Simultaneously reading input data blocks from a plurality of banks of the SCM at a predetermined number of clock cycles, extracting and reformatting the external memory data from the cache data organization, extracting this data, and hiding the external data organization from the PU2. Increasing the data processing rate in PU2; (d) generating PCM control queues large enough to store the extracted data in the PCM before the data needed by the PU2 based on the results of (a) and (b); And (e) synchronizing the arrival of data and control parameters in the PU2 to maintain cache coherency. 2. The method of claim 1, further comprising optimizing the SCM structure and the required workload, including the number of SCM banks, the number of lines per SCM bank, and the SCM line size based on an input block data structure and a read format of the external memory. Method comprising a. 3. The method of claim 2, further comprising optimizing the PCM structure and the amount of work required, including the number of PCM banks, the number of lines per PCM bank, and the PCM line size based on an output data structure and format. Way. 4. The method of claim 3, wherein the mapping to the cache system is a direct mapping based on an address sequence. 4. The method of claim 3, wherein the mapping to the cache system consists of two steps below. (a) direct mapping based on address sequences; And (b) Distance-based replacement policy for replacing data associated with the input block furthest from the data block being processed. 4. The method of claim 3, wherein the mapping to the cache system consists of two steps below. (a) direct mapping based on address sequences; And (b) Recently used replacement policy that replaces data related to the most recently used input block. 4. The method of claim 3, further comprising adjusting the PCM size based on the amount of data to access. 4. The method of claim 3, further comprising adjusting the SCM size based on the amount of data to access. 4. The method of claim 3, further comprising adjusting the PCM line size based on the frequency of cache updates. 4. The method of claim 3, further comprising adjusting the SCM line size based on read back elements. 4. The method of claim 3, further comprising dividing the input data block into sub-blocks and sequentially caching data from each sub-block for processing at PU2. 4. The method of claim 3, further comprising adjusting depths of control queues and data queues to optimize workload. 4. The method of claim 3, further comprising adjusting the PCM output width and the number of banks based on the required workload of the PU2. 4. The method of claim 3, further comprising adjusting the PCM line size based on an input datablock size. 4. The method of claim 3, further comprising adjusting an SCM line size based on the external memory burst size. 4. The method of claim 3, further comprising adjusting the number of SCM banks based on the required PCM update rate. 4. The method of claim 3, further comprising distributing data in the PCM and SCM based on the least significant bit of a memory address of an input data block. In a cache system that processes two-dimensional images by data processing, specifically co-ordinate transformations: a) an external memory in which data to be accessed and processed is stored; b) a plurality of processor units PU1 for generating control commands and generating memory addresses and control variables of data to be processed in the external memory; And c) in the apparatus consisting of a plurality of processor units (PU2) to process data; (i) a deep secondary cache memory (SCM) having a plurality of banks having a plurality of storage lines for reading data from the external memory and having a large storage capacity; (ii) a fast and wide primary cache memory (PCM) having a plurality of banks having several storage lines for reading data by the PU2, and having low storage capacity; And (iii) using a cache system that provides control of prefetching and cache, and includes control logic including control stages and control queues, Upon receiving the address sequence and control parameters from the PU1, access the data from the external memory, prepare the data for fast access and processing by the PU2, and follow the steps below to achieve cache coherency and read memory. Cache system, characterized in that to hide the delay. (a) identifying a data block to be processed in an external memory based on the form and structure of the processing operation network of the PU2; (b) create a sufficiently large SCM control queue based on the results of (a) and determine whether the data is in the PCM, so that the SCM can access data in external memory much faster than it is processed by PU2. Doing; (c) Simultaneously reading input data blocks from a plurality of banks of the SCM at a predetermined number of clock cycles, extracting and reformatting the external memory data from the cache data organization, extracting this data, and hiding the external data organization from the PU2. Increasing the data processing rate in PU2; (d) generating PCM control queues large enough to store the extracted data in the PCM before the data needed by the PU2 based on the results of (a) and (b); And (e) synchronizing the arrival of data and control parameters in the PU2 to maintain cache coherency. 19. The method of claim 18, wherein the SCM structure comprises a number of SCM banks, lines per SCM bank, and SCM line size based on an input block data structure and a read format of the external memory, and is suitable for optimizing the required workload. System characterized. 20. The system of claim 19, wherein the system is suitable for optimizing the PCM structure and required workload, including the number of PCM banks, the number of lines per PCM bank, and the PCM line size based on output data structure and format. 21. The system of claim 20, wherein the mapping to the cache system is a direct mapping based on an address sequence. 21. The system of claim 20, wherein the mapping to the cache system consists of two steps below. (a) direct mapping based on address sequences; And (b) Distance-based replacement policy for replacing data associated with the input block furthest from the data block being processed. 21. The system of claim 20, wherein the mapping to the cache system consists of two steps below. (a) direct mapping based on address sequences; And (b) Recently used replacement policy that replaces data related to the most recently used input block. 21. The system of claim 20, adapted to adjust the PCM size based on the amount of data to access. 21. The system of claim 20, adapted to adjust the SCM size based on the amount of data to access. 21. The system of claim 20, adapted to adjust the PCM line size based on the frequency of cache updates. 21. The system of claim 20, adapted to adjust the SCM line size based on read back elements. 21. The system of claim 20, adapted to divide the input data block into sub-blocks and to sequentially cache data from each sub-block for processing at PU2. 21. The system of claim 20, adapted to adjust the depth of the control queue and the data queue to optimize workload. 21. The system of claim 20, adapted to adjust the PCM output width and the number of banks based on the required workload of the PU2. 21. The system of claim 20, adapted to adjust the PCM line size based on an input datablock size. 21. The system of claim 20, adapted to adjust SCM line size based on the external memory burst size. 21. The system of claim 20, adapted to adjust the number of SCM banks based on a required PCM update rate. 21. The system of claim 20, adapted to distribute data in the PCM and SCM based on the least significant bit of the memory address of an input data block.