JP2008507028A - System and method for managing cache memory - Google Patents

Abstract

A cache memory method and a corresponding system for two-dimensional data processing, particularly two-dimensional image processing for performing coordinate transformation simultaneously, are disclosed. The method uses a wide and fast primary cache memory (PCM) and a deep secondary cache memory (SCM), each having multiple banks that simultaneously access data. When control parameters are received from the external processor system (PU1) using a dedicated prefetch logic, the pixel data is acquired from the external memory and stored in the PCM based on the secondary control queue.
This data is then prepared in a specific block size and a specific format and then stored in the PCM based on an optimized size prefetch primary control queue. Next, this prepared data is read and processed by another external processor system (PU2). This cache control logic ensures coherency of data and control parameters at the input of PU2.

Description

  The present invention relates to the structure and management of a cache memory in digital data processing, particularly digital image data processing.

  Since the invention of new computer systems, there has always been a competition for faster processing and faster systems. Faster processors have been created that potentially increase the speed of the clock. It is natural that the amount of data and instructions has increased rapidly. In a computer system, there are storage devices such as a ROM (Read Only Memory) for storing data and instructions having a larger storage capacity and a burst-based memory, for example, a DRAM. Structurally, large memory spaces are deepening, which slows down the speed of processors accessing data and instructions in memory. This problem creates a need for more efficient memory management and the creation of cache memory and cache memory structures. A cache memory is generally a shallow and wide storage device within or close to the processor that makes it easier for the processor to access and modify the contents of the data. The cache memory management philosophy is to keep a copy of data and instructions that are used frequently, that is, most likely to be used by the processor in the near future, in the fastest accessible storage device. . This allows the processor to access data and instructions many times faster than in external memory. However, care must be taken to maintain harmony in operations such as changing the contents of cache memory or external memory. Due to such problems related to hardware functions and software functions, cache memory structures and techniques for managing them have been created.

  As already mentioned, the cache memory holds a copy of the data and the address pointer that are most likely to be accessed next by the processor. The external memory generally stores data in the capacitor, and requires a refresh cycle for replenishing the capacitor with charge in order to prevent the data from being lost. However, a general cache memory uses 8 transistors to represent 1 bit, thereby eliminating the need for a refresh cycle. Therefore, the cache memory has much less storage space per unit size than the external memory. For this reason, cache memory has much less data capacity than external memory. As a result, data and instructions must be carefully screened to optimize cache operation.

  Various policies and protocols are used to optimize cache memory behavior. The most well-known of these are the direct mapping method, the full associative method, and the set associative method. These protocols are well known to those skilled in the art. These protocols are suitable for the general purpose of operations involving data processing, web-based applications, and the like. U.S. Pat. No. 4,295,193, issued to Pomerene, presents a computing machine that executes instructions compiled into multi-instruction words concurrently. This is one of the earliest patents suggesting cache memory, address generators, instruction registers, and pipelining. U.S. Pat. No. 4,796,175 issued to Matsuo presents a microprocessor with an instruction queue function that has a form for prefetching instructions from a main memory and an instruction cache. US Pat. No. 6,067,616 issued to Stills includes a fully associative wide and shallow first level BCP (branch prediction cache) and a deep narrow direct with partial prediction information. A branch prediction cache (BCP) scheme with a hybrid cache structure of mapped second level BCPs is presented. U.S. Pat. No. 6,654,856 issued to Frank presents a cache management system in a computer system with an emphasis on addressable circular cache memory.

  US Pat. No. 6,681,296 issued to Liao presents a microprocessor with a control unit and a cache, which is divided into a lock part and a normal part. A cache configuration or a single cache configuration can be selected. U.S. Pat. No. 6,721,856 issued to Arimili describes the coherency state and system controller information for each line with different processor subsequence entries for different processors. A cache with is presented. U.S. Pat. No. 6,629,188 discloses a cache memory having first and second storage spaces. U.S. Pat. No. 6,295,582 discloses a cache system that has data coherency and avoids deadlock between substantially sequential read and write commands. U.S. Pat. No. 6,339,428 discloses a caching device in the field of video graphics where compressed texture information is received and decompressed for texture manipulation. Yes. US Pat. No. 6,353,438 discloses a cache organization that has multiple tiles of texture image data and maps the data directly to the cache.

Each of the above inventions provides certain advantages. An efficient cache structure and policy strongly depends on the specific application at hand. In digital video applications, processing digital images in real time and with high quality is one of the major challenges in this field. Specifically, detailed two-dimensional image processing is required while simultaneously performing nonlinear coordinate transformation. Therefore, there is a need for specialized specialized systems that have the unique advantage of quickly accessing data with coherency. Therefore, it is necessary to optimize the cache structure and cache management policy for this application.
U.S. Pat. No. 4,295,193 U.S. Pat. No. 4,796,175 US Pat. No. 6,067,616 US Pat. No. 6,654,856 US Pat. No. 6,681,296 US Pat. No. 6,721,856 US Pat. No. 6,629,188 US Pat. No. 6,295,582 US Pat. No. 6,339,428 US Pat. No. 6,353,438

In one aspect of the present invention,
(A) an external memory for storing data to be accessed and processed;
(B) a plurality of processor units (PU1) that issue control commands and generate control parameters and memory addresses of processing-scheduled data in the external memory;
(C) a plurality of processor units (PU2) for processing data;
In a setting comprising: a cache memory management method and a cache memory structure in digital data processing, particularly digital image processing.
This method
(I) a deeper secondary cache memory (SCM) having a larger storage capacity, each having a plurality of banks having a plurality of storage lines for reading data from the external memory;
(Ii) a faster and wider primary cache memory (PCM) with smaller storage capacity, each having a plurality of banks with a plurality of storage lines from which the PU 2 reads data;
(Iii) control logic including a control stage and a control queue, which provides prefetch functionality and cache coherency;
When the address sequence and control parameters are received from PU1, the data in the external memory is processed, and the data is prepared so that PU2 can quickly access and process it.
This method
(A) identifying which data block in the external memory is to be processed based on the topology and structure of the processing operation in the PU 2;
(B) A sufficiently large SCM control queue is generated based on the result of step (a) to determine whether data is present in the PCM, and the SCM is required for processing by the PU 2 on the data in the external memory. Steps to ensure access early enough to be
(C) simultaneously reading blocks of input data from a plurality of banks of the SCM in a predetermined number of clock cycles and decompressing and reformatting the external memory data organization from the cache data organization. And thereby concealing (hiding) the external memory data organization from the PU2 to increase the speed of data processing in the PU2, and
(D) generating a sufficiently large PCM control queue based on the results of steps (a) and (b) and storing the extracted data in the PCM before the data is needed by the PU 2 When,
(E) Synchronizing the timing at which data arrives in the PU 2 and the timing at which control parameters arrive to achieve cache coherency;
To achieve cache coherency and conceal memory read latency.

  In another aspect, the present invention provides a cache system based on the method described above.

  Further details of various aspects and advantages of embodiments of the present invention are set forth below with reference to the accompanying drawings.

  The present invention will now be described in detail with reference to the accompanying drawings and exemplary embodiments. The present invention relates to cache structure and management. The embodiment described in the following description is an example of image processing that involves simultaneous coordinate transformation. However, those skilled in the art will understand that the scope of the present invention is not limited to this particular example. The present invention relates to any type of digital data processing in which multiple processors attempt to fetch data and control parameters from external memory and other processors of any format. In particular, it is obvious that the two-dimensional (2D) image conversion example described in this document can be replaced with any 2D image conversion without departing from the scope of the present invention. Therefore, in the following description, data means image pixel data. A plurality of processors that issue control parameters related to the structure and topology of input data refers to a geometry engine. In addition, the plurality of processors that process the operation data are filter engines, and the corresponding operation is a filtering operation.

  FIG. 1 illustrates an example of the setting of a cache system 100 in a computing device designed according to the present invention and designed for digital image data processing with a simultaneous coordinate transformation function. Cache system 100 interfaces with two sets of processors. In this embodiment, the first plurality of processors constitutes the geometry engine 300, and the second plurality of processors constitutes the filter engine 500. In addition to these two engines, the cache system 100 interfaces with an external memory 700 that can be any memory with access latency. The cache system 100 receives control parameters from the geometry engine 300 including coordinate transformation parameters and filter footprint parameters. At the same time, the system receives pixel data from the external memory 700. The cache system 100 provides these data to the filter engine 500 so as to optimize the filtering process while minimizing the outage of the filter engine 500.

  In two-dimensional (2D) data processing, particularly digital image data processing, a comprehensive filtering function or sampling function is required. In the following, 2D image processing will be taken as a particular example, so the term “pixel” is used as a specific case of arbitrary 2D data. In 2D digital image processing, each output pixel is formed based on information from many input pixels. First, output pixel coordinates are mapped to input pixel coordinates. This is a coordinate transformation, usually performed electronically by image warping techniques. Once the central input pixel is determined, a filtering or sampling function is required to generate the output pixel specification, ie, the intensity of the constituent colors, and other information such as the sampling format and blend function. On the other hand, the area containing all the pixels around the central input pixel on which sampling is performed is called the filter footprint. It is well known in the art that the size and shape of the filter footprint affects the quality of the output image.

  The functionality of the cache system 100 uses a dedicated architecture and prefetch logic to provide sufficient random access pixel data and control parameters to the filter engine 500, which allows the engine to select which clock while minimizing outages. It is to have data to be processed even at speed. The read request queue with the optimized size allows the cache system 100 to conceal most of the memory read latency inherent in the external memory 700 from which the pixel data is fetched. This concealment operation of the memory read latency takes precedence over the filter operation. If this latency is not properly concealed, the throughput of the filter engine 500 will not be maximized. The allowed outage time is a design parameter. Various parameters need to be adjusted to achieve the required throughput as a trade-off with hardware cost.

  In addition, the cache system 100 provides a filter footprint parameter read from the geometry engine 300 and a control path for coordinate conversion. The cache system 100 ensures that pixel data from the external memory 700 on the one hand and control parameters from the geometry engine 300 on the other hand are synchronized when they reach the input of the filter engine 500.

  Herein, we adopt a convention of displaying quantities in italics (eg, 64 bytes) so that they are distinguished from reference numbers (eg, filter engine 500).

  FIG. 2 is a diagram illustrating an example of a detailed structure of the cache system 100. For each output pixel, the cache system 100 receives certain control parameters from the geometry engine 300. Such parameters include the coordinates of the mapped input pixels, U and V, and additional control parameters such as control parameters that define the shape, rotation amount and size of the filter footprint. At the same time, the cache system 100 receives pixel data for each of the filter footprints from the external memory 700. Such data includes constituent colors in the color space, such as RGB or YCrCb intensity levels, sampling formats such as 4: 4: 4 or 4: 2: 2, and blending functions, ie α. Whether or not α is included.

  The structure of the cache system 100 is related to dividing an input image into blocks having a size of m × n pixels. FIG. 3 shows an example of an input image pixel block structure in which n = 8 and m = 4. The input image 330 includes a certain number of pixels, for example, 1024 × 1024 pixels divided into blocks. Each input pixel block 332 includes m × n input pixels 334. The structure of the block is generally a function of footprint shape and size in various filtering schemes.

  The cache system 100 fetches data associated with the m × n input pixel blocks 332 to generate a data block that can be used by the filter engine 500. Thus, the system must determine which blocks fall within the footprint and which pixels within such blocks should be included for filtering. The structure of the cache system 100 can be expanded to fit the input block data structure. It should also be noted that in general, the structure of the cache system 100 is a function of the nature and structure of the operation of the filter engine 500. In the special case of image processing, the structure and topology of this operation is defined in part by the filter footprint.

  Referring now to the example shown in FIG. 2, the cache system 100 includes a shallow, wide and low capacity primary cache 110, a deep and large secondary cache 120, a block inclusion stage 150, a block data generation stage 130, A primary cache control stage 170 and a secondary cache control stage 190 are provided. There are also many queues, which will be described later. Pixel data is first read from the external memory 700 into the secondary cache 120. These data are then reformatted by the block generation stage 130 and decompressed for use by the filter engine 500. These reformatted data are queued and placed in the primary cache 110 at the appropriate time, where they are immediately accessible by the filter engine 500. The data path and control logic structure will be described below.

  Referring now to the example shown in FIG. 5, the secondary cache 120 is a mass storage device that reads raw data from the external memory 700. The pixel data in the external memory 700 is stored in any format, generally not well suited for processing in the filter engine 500, for example, in a special case, the data is sequentially, ie, They are stored in the order of scanning lines. The secondary cache 120 is designed to read these data efficiently with minimal interruptions.

Each line in the secondary cache is designed to accommodate a b ₂ byte burst of data from the external memory 700. For this reason, the size of each line in the secondary cache 120 is determined according to the structure of the external memory 700 and the read requirements. The number of lines in the secondary cache 120 where such data is stored is also a design parameter optimized to reduce secondary cache miss counts. Secondary cache 120 is further banked to update primary cache 110 to allow sufficient read throughput to minimize outage of filter engine 500. These design parameters are critical to storing sufficient data for pixel processing by the filter engine 500 because many neighboring pixels are required to sample the central input pixel.

Therefore, the secondary cache 120 is designed to have a certain number of banks having access lines independent from each other in order to simultaneously read data from the external memory 700. As shown in the example of FIG. 5, the secondary cache 120 has many banks 122, each of which has a certain number of lines 124. Each line of the secondary cache contains one data burst of data read from the external memory 700. These data need to be finally read by the filter engine 500. For this reason, the number of banks of the secondary cache is designed as a function of data throughput. If the number of clock cycles required to read data is Nc with a structure of m × n input blocks, n / Nc banks are required in the secondary cache 120. In order to distribute the data to the banks of the secondary cache, in one particular embodiment, the least significant bit (LSB) U and V combination is used. This reduces the complexity of the decoding logic, which saves space and makes the update operation much faster. To divide each bank into 2 ^j partitions, j LSBs are used. If there are 2 ^j lines per secondary cache bank, the secondary cache architecture is a 2 ^j / 2 ^j set associative scheme. The design, combined with an appropriate replacement policy for the secondary cache 120, makes partitioning simple and efficient, as will be described later along with the cache logic, so that data is distributed throughout the secondary cache 120. .

  Once the data is read from the external memory 700 into the secondary cache 120, these data need to be converted into a format usable by the filter engine 500. The block generation stage 130 reads data from the secondary cache 120 and prepares these data into blocks that contain all the data from the block of m × n input pixels. As described above, the block generation stage 130 reads n / Nc lines of the secondary cache 120 every clock cycle. This ensures that every Nc clock cycles, all data associated with one input pixel block is read out simultaneously. Depending on the data packing format and read throughput, multiple read operations from the secondary cache 120 are required to generate the input pixel block. In addition to reading these data, the block generation stage 130 reformats these data and decompresses them into a format that the filter engine 500 can easily use. Accordingly, the block generation stage 130 conceals the original pixel data format that can be compressed with various compression schemes. This frees the filter engine 500 from the responsibility to unravel the format of the pixel data in the external memory 700 and unpack the original formatted data into blocks that can be used for filtering operations. These block data are finally stored in the primary cache 110 and read out by the filter engine 500 therefrom.

Referring now to the example of FIG. 4, the primary cache 110 is designed to optimize the data access speed in the filter engine 500. Therefore, it has a shallow but wide structure for a plurality of access lines. The primary cache 110 is divided into a number of banks, and each primary cache bank 112 is read independently and simultaneously by the filter engine 500. The number of primary cache banks is determined according to experience-based data and simulations to optimize filtering performance. Each primary cash bank 112 includes a number of primary cache lines. Each primary cache line 114 contains data from a complete m × n block of input data. Therefore, if there are b ₁ primary cache banks, the filter engine 500 reads data including b ₁ input blocks in an appropriate format for each cycle. This is very important because it requires a large number of input blocks around the input pixel to sample, and if a large number of input blocks are not provided to the filter engine 500, the engine will fail. It is. Throughput performance is determined by the duration and frequency of outages.

In order to distribute the data to the various primary cache banks, the input pixel coordinate LSBs U and V are used. Each primary bank 112 within the primary cache 110 is further divided into a number of partitions. As described above, a certain number of LSBs are used to distribute data to the various primary cache banks. Additional LSBs in the remaining bits of the input pixel U and V addresses are also used to distribute the data in each primary cache bank. For each primary cache bank and every 2 ^f lines, g LSBs used to partition each bank are used. This partitioning results in 2 ^f / 2 ^g set associative architectures. Become.

  As described below, this design is also used with an appropriate replacement policy for the primary cache 110 to achieve optimal throughput. This architecture is easily and naturally scalable because the amount of input data increases, so the number of bits available in address U and address V increases.

  The prefetch logic structure is designed to ensure that there is data in a usable format as needed by the filter engine 500. FIG. 6 shows the cache control logic 400. This logic structure controls the operation of the secondary cache 120 reading data from the external memory 700, the operation of reading and reformatting the data in the block generation stage 130, and the operation of storing the data block in the primary cache 110.

  At step 402, it is determined based on the control parameters received from the geometry engine 300 whether a data block is needed for sampling. Once the data is identified, it is determined at step 410 whether these data are present in the primary cache. If so, an entry is written to the primary control queue at step 412 and the address of these data is sent to the filter engine 414 at step 414. If the data does not exist in the primary cache, it is determined in step 415 which primary cache line to replace according to the adopted replacement policy described below. Next, at step 416, the address of this primary cache line is written to the primary control queue and sent to the filter engine at step 418. Next, it is determined at step 420 whether these data are present in the secondary cache. If the data does not exist there, it is determined in step 422 which secondary cache line should be replaced. Next, a read request is sent to the external memory to fetch data that is later read into the secondary cache at step 426. If the data is in the secondary cache, at step 428, an entry is written to the secondary cache control queue.

  Whether the secondary cache hits or the secondary cache misses after data is fetched from external memory, at step 440, the secondary cache data is read for block generation. In this case, data is read from multiple secondary cache banks and reformatted and decompressed at step 442. At this stage, in step 450, a block of input data with the appropriate format is sent as a queue and stored in the primary cache. At step 452, these data are stored in the primary cache bank.

  The update operation of the primary cache 110 occurs when related control data is read from the primary control queue 212 and the pixel control queue 218. This ensures that cache coherency is maintained within the primary cache 100. At this point, data from the primary cache arrives at the filter engine input at step 510 along with control parameter coherency.

  The prefetch logic is designed to conceal the read latency in the filter engine 500. Without this control logic structure, data throughput is not optimized and the rate at which the filter engine 500 stops functioning increases. If the queue size is sufficient, the storage size is optimal, the data is prepared, and the replacement policy is intelligent, the cache system 100 will run most of the read latency by running before the filter engine 500. Conceal.

  Referring again to FIG. 2, a hardware embodiment of the cache control logic 400 is described below. Block inclusion stage 150 is the starting point for this control logic. For each output pixel, the logic receives control parameters from the geometry engine 300 along with the mapped input pixel coordinates and the filter footprint shape. Based on the input pixel coordinates, U and V, footprint shape, and other control parameters, the block inclusion logic determines which input block is required to process each output pixel, and Determine which pixels in each block are needed for sampling.

  The block inclusion stage 150, in one example of the present invention, includes blocks of pixels necessary for sampling by comparing the coordinate positions of adjacent blocks with the footprint geometry. The block inclusion logic generates k blocks each having at least the least significant bit (LSB) 1U or 1V different in the block address every clock cycle. This ensures that there are k combinations of LSBs in each set of blocks generated by the block containment logic. Using this constraint, blocks are distributed among the primary cache banks. The number of generated blocks k per clock cycle is a function of the footprint size, and the block topology is a function of the footprint shape. These parameters should be considered when designing the cache system 110 for data processing in the filter engine 500 through careful simulation and experimentation. The pixel control queue 218 generated at the block inclusion stage 150 is sent to the filter engine 500 before allowing the filter engine 500 to generate the scaling parameters prior to the actual pixel data.

  The primary cache control stage 170 provides control logic for handling data in the primary cache 110. For each input block determined by the block inclusion stage 150, the primary cache controller 170 checks whether this block exists in the primary cache 110. If there is data, this is called a cache hit. If not, a cache miss is registered and a miss flag is sent to the secondary cache controller 190. The primary cache control stage 170 writes an entry into the primary control queue 212 to indicate the address of the data in the primary cache 110 and whether there was a primary cache hit or a miss. The primary control queue 212 is read by the filter engine 500 in a FIFO manner. When the cache miss flag is raised in one of such entries, the filter engine 500 sends a read request to the block queue 214, which then updates the primary cache 110.

  In the case of a primary cache miss that occurs if the data block does not exist in the primary cache 110, the address U or V does not match any of the checked blocks, or the associated valid bit is not set, this event Called a cache miss. When the control logic in the secondary cache stage 190 receives the primary cache miss flag, it determines what action (steps) should be taken to generate m × n blocks to be written to the primary cache. The secondary cache control stage 190 first determines whether data is present in the secondary cache 120. As a result, a secondary cache hit or a secondary cache miss occurs. When a secondary cache miss occurs, the secondary cache controller 190 sends a read request to the external memory 700, fetches missing data from the external memory 700 into the secondary cache 120, and enters the secondary control queue 216. Write. When a secondary cache hit occurs, the secondary cache control stage 190 simply writes the entry to the secondary control queue 216 without sending a read request, where the entry is read by the block generation stage 130 in a FIFO manner.

  Upon receipt of each queue entry, the block generation stage 130 reads raw data associated with the entire input block from the secondary cache 120. These data are then reformatted in the block generation stage 130 into a format that the filter engine 500 can easily use. Depending on the data packing mode, a plurality of secondary cache lines are required to generate the primary cache line 114. Once all the data associated with one input block has been obtained and reformatted, the block generation stage 130 writes an entry to the block queue 214. Thus, each block queue entry contains all the data from this entire input block in an appropriate format. The block queue entry is then received by the primary cache 110 where it is stored for easy access by the filter engine 500. Therefore, the secondary cache 120 is allowed to travel before the filter engine 500 by the block queue 214.

  It should be noted that the function of the cache system 100 depends on pixel data and control parameter coherency in addition to dedicated prefetch logic. No data is read by the secondary cache 120 unless requested by the secondary cache control stage 190. Once that data enters the secondary cache, only entries for the secondary control queue 216 determine whether these data are needed for block generation at the block generation stage 130. Once a block of data is generated, it is queued and stored in the primary cache only when a read request is made from the filter engine 500, but the engine 500 itself is stored by an entry in the primary control queue 212. Be tempted. In addition, the filter engine waits for both data and control parameters to come from two independent queues and then processes the data.

  Depending on the relative size of the filter footprint and the cache storage space, it may be necessary to divide the footprint into sub-footprint parts and process the data in each sub-footprint part. This measure is foreseen in the design of a cache system 100 for a dynamically sized footprint. Once the data associated with each sub-footprint is cached, the filter engine processes these data sequentially.

  In understanding the effect of data prefetch operation that allows the cache system 100 to conceal the memory read latency, an example of the present invention has been evaluated based on whether the read latency is in the 128 clock cycle range. By providing a sufficiently large queue, almost all latency is concealed. The size of the queue in the present invention can be adjusted to match the memory read latency found in the present system and is therefore an extensible design parameter based on system specifications.

  Once the cache logic structure determines that a block of data should be read by the secondary cache 120 or prepared for storage in the primary cache 110, a replacement policy is required. One existing primary cache line 114 or multiple secondary cache lines 124 must be replaced. In one example of the invention, the cache replacement policy is a distance-based policy. According to the input block addresses U and V, the primary cache control stage 170 and the secondary cache control stage 190 compare the coordinates of the central input pixels U and V with the coordinates of the existing block data in the cache line. Next, the entry with the largest distance from the central input pixel is replaced. This policy is derived from the fact that the closer the distance to the center pixel, the higher the probability that it will be needed for the calculation of the sampling.

  In another example of the present invention, the cache replacement policy is a least recently used (LRU) based policy. In this latter example, primary cache control stage 170 and secondary cache control stage 190 attempt to replace the least frequently used cache line.

  The design of the cache system 100 has several measures to make the system extensible. The size of the secondary cache line can be expanded from the external memory 700 and the block generation rate to a memory read size, for example, a burst size. The number of secondary cache lines can be expanded based on the required cache efficiency. The number of secondary cache banks can be expanded based on the input block data structure and the number of clock cycles per access from the secondary cache. The secondary cache 120 expansion is based on size requirements and cache system efficiency, ie, the amount of input digital data to be reread.

  The number of blocks generated per clock cycle in the block inclusion stage 150 is scalable based on the filtering algorithm and footprint size and required throughput. The positioning of the primary cache 110 and the secondary cache 120 based on the input pixels LSB U and V can also be adapted to the size of the cache. This is implemented by the number of bits used for a particular partitioning purpose. The size of the primary cache line can be expanded based on the size of the input block. The number of primary cache banks can be expanded based on filtering throughput. Various queue sizes are also scalable parameters that depend on the relationship between memory latency and required throughput. Such a size is determined based on simulation and empirical data.

  All such design parameters must be carefully considered as a trade-off between cost and performance. Careful simulations and experiments are therefore carried out specifically for the purpose of implementing the present invention to optimize the special case cache solution for the time being.

  While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. Accordingly, it is to be understood that the appended claims are intended to cover all modifications and changes that fall within the true spirit of the invention.

1 is a diagram illustrating the overall scheme of a cache system constructed in accordance with the present invention. It is a figure which shows the detailed structure of the cache system constructed | assembled according to this invention. It is a figure which shows the example of the block structure of the input data cached. 1 is a diagram illustrating the general structure of a primary cache system constructed in accordance with the present invention. 1 is a diagram illustrating the general structure of a secondary cache system constructed in accordance with the present invention. FIG. 3 is a diagram illustrating the flow logic of a cache system constructed in accordance with the present invention.

Claims (34)

A cache structure and management method in data processing, in particular, two-dimensional image processing in which coordinate transformation is performed simultaneously;
(A) an external memory for storing data to be accessed and processed;
(B) a plurality of processor units (PU1) that issue control commands and generate control parameters and memory addresses of processing-scheduled data in the external memory;
(C) a plurality of processor units (PU2) for processing data;
The method uses a cache system, the cache system comprising:
(I) a deeper secondary cache memory (SCM) having a larger storage capacity, each having a plurality of banks having a plurality of storage lines for reading data from the external memory;
(Ii) a faster and wider primary cache memory (PCM) with smaller storage capacity, each having a plurality of banks with a plurality of storage lines from which the PU 2 reads data;
(Iii) control logic including a control stage and a control queue, which provides prefetch functionality and cache coherency;
And when the address sequence and control parameters are received from the PU1, access the data in the external memory, and prepare the data so that the PU2 can quickly access and process it,
The method
(A) identifying which data block in the external memory is to be processed based on the topology and structure of the processing operation in the PU 2;
(B) A sufficiently large SCM control queue is generated based on the result of step (a) to determine whether data is present in the PCM, so that the SCM adds the PU2 to the data in the external memory. To ensure access early enough to be required for processing by
(C) simultaneously reading blocks of input data from a plurality of banks of the SCM in a predetermined number of clock cycles and decompressing and reformatting the external memory data organization from the cache data organization. And thereby concealing external memory data organization from the PU2 to increase the speed of data processing in the PU2, and
(D) generating a sufficiently large PCM control queue based on the results of steps (a) and (b) and storing the extracted data in the PCM before the data is needed by the PU 2 When,
(E) Synchronizing the timing at which data arrives in the PU 2 and the timing at which control parameters arrive to achieve cache coherency;
To achieve cache coherency and conceal memory read latency.   The number of SCM banks, the number of lines per SCM bank, the SCM structure including the SCM line size, the input block data structure, the read format from the external memory, and the required throughput. The method of claim 1, further comprising the step of optimizing.   Further optimizing the PCM structure including the number of PCM banks, the number of lines per PCM bank, and the size of the PCM lines based on the output data structure, format, and required throughput. The method of claim 2 comprising.   The method of claim 3, wherein the mapping to the cache system is a direct mapping based on an address sequence. Mapping to the cache system
(A) direct mapping based on address sequence;
(B) a distance-based replacement policy in which data associated with an input block that is remote from the data block being processed is replaced;
4. The method of claim 3, wherein the method is performed in two stages. Mapping to the cache system
(A) direct mapping based on address sequence;
(B) a least recently used replacement policy in which data associated with the least recently used input block is replaced;
4. The method of claim 3, wherein the method is performed in two stages.   The method of claim 3, further comprising scaling the PCM size based on the amount of data accessed.   The method of claim 3, further comprising scaling the SCM size based on the amount of data accessed.   4. The method of claim 3, further comprising scaling the PCM size based on cache update frequency.   The method of claim 3, further comprising scaling the SCM size based on a reread coefficient.   4. The method of claim 3, further comprising the step of dividing the input data block into sub-blocks and sequentially caching data from each sub-block for processing in the PU2.   The method of claim 3, further comprising scaling the depth of the control queue and data queue to optimize throughput.   4. The method of claim 3, further comprising scaling the PCM output width and the number of banks based on the PU2 throughput requirement.   The method of claim 3, further comprising scaling the PCM line size based on an input data block size.   The method of claim 3, further comprising scaling the SCM line size based on the external memory burst size.   4. The method of claim 3, further comprising scaling the number of SCM banks based on the required rate of the PCM update.   4. The method of claim 3, further comprising allocating data among the PCM and the SCM based on a least significant bit of a memory address of an input data block. A cache system for data processing, particularly two-dimensional image processing that simultaneously performs coordinate transformation;
(A) an external memory for storing data to be accessed and processed;
(B) a plurality of processor units (PU1) that issue control commands and generate control parameters and memory addresses of processing-scheduled data in the external memory;
(C) a plurality of processor units (PU2) for processing data;
An apparatus comprising:
(I) a deeper secondary cache memory (SCM) having a larger storage capacity, each having a plurality of banks having a plurality of storage lines for reading data from the external memory;
(Ii) a faster and wider primary cache memory (PCM) with smaller storage capacity, each having a plurality of banks with a plurality of storage lines from which the PU 2 reads data;
(Iii) control logic including a control stage and a control queue, which provides prefetch functionality and cache coherency;
And when the address sequence and control parameters are received from the PU1, the data in the external memory is accessed, and the data is prepared so that the PU2 can quickly access and process the data,
The system
(A) identifying which data block in the external memory is to be processed based on the topology and structure of the processing operation in the PU 2;
(B) A sufficiently large SCM control queue is generated based on the result of step (a) to determine whether data is present in the PCM, so that the SCM adds the PU2 to the data in the external memory. To ensure access early enough to be required for processing by
(C) simultaneously reading blocks of input data from a plurality of banks of the SCM in a predetermined number of clock cycles to decompress and reformat the external memory data organization from the cache data organization. And thereby concealing external memory data organization from the PU2 to increase the speed of data processing in the PU2, and
(D) generating a sufficiently large PCM control queue based on the results of steps (a) and (b) and storing the extracted data in the PCM before the data is needed by the PU 2 When,
(E) Synchronizing the timing at which data arrives in the PU 2 and the timing at which control parameters arrive to achieve cache coherency;
To achieve cache coherency and conceal memory read latency.   The SCM structure, including the number of SCM banks, the number of lines per SCM bank, and the SCM line size, the input block data structure, the read format from the external memory, and the required throughput The system of claim 18 further comprising the step of optimizing.   Further optimizing the PCM structure including the number of PCM banks, the number of lines per PCM bank, and the size of the PCM lines based on the output data structure, format, and required throughput. 20. The system of claim 19, comprising.   21. The system of claim 20, wherein the mapping to the cache system is a direct mapping based on an address sequence. Mapping to the cache system
(A) direct mapping based on address sequence;
(B) a distance-based replacement policy in which data associated with an input block that is remote from the data block being processed is replaced;
21. The system of claim 20, wherein the system is performed in two stages. Mapping to the cache system
(A) direct mapping based on address sequence;
(B) a least recently used replacement policy in which data associated with the least recently used input block is replaced;
21. The system of claim 20, wherein the system is performed in two stages.   21. The system of claim 20, further configured to scale the PCM size based on an amount of data accessed.   21. The system of claim 20, further configured to scale the SCM size based on the amount of data accessed.   21. The system of claim 20, further configured to scale the PCM line size based on cache update frequency.   21. The system of claim 20, further configured to scale the SCM size based on a reread factor.   21. The system of claim 20, further comprising: dividing an input data block into sub-blocks and sequentially caching data from each sub-block for processing in the PU2.   21. The system of claim 20, further configured to scale the depth of the control queue and data queue to optimize throughput.   21. The system of claim 20, further configured to scale the PCM output width and the number of banks based on the PU2 throughput requirement.   21. The system of claim 20, wherein the system is adapted to scale the PCM line size based on an input data block size.   21. The system of claim 20, wherein the system is adapted to scale the SCM line size based on the external memory burst size.   21. The system of claim 20, wherein the system is adapted to scale the number of SCM banks based on a required rate of the PCM update.   21. The system of claim 20, wherein data is distributed among the PCM and the SCM based on a least significant bit of a memory address of an input data block.

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