CN100527111C - On-chip DMA structure and its implement method - Google Patents
On-chip DMA structure and its implement method Download PDFInfo
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- CN100527111C CN100527111C CNB2007101754932A CN200710175493A CN100527111C CN 100527111 C CN100527111 C CN 100527111C CN B2007101754932 A CNB2007101754932 A CN B2007101754932A CN 200710175493 A CN200710175493 A CN 200710175493A CN 100527111 C CN100527111 C CN 100527111C
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Abstract
The utility model discloses an on-chip DMA structure and an implementation method, which comprises a DMA register set, a priority arbitration unit, a DMA data buffer register, an interrupting device and a receiving element and a plus/minus 1 control logic; the width of data transmission in the channel between memorizers on the on-chip DMA is 32 bits; due to the support of independent internal address and data bus, CPU and DMA can be operated at the same time and the transmission rate of DMA is fitted with CPU; the independent address plus/minus 1 module controls the automatic increase and decrease of the original and objective address register and transmission number. Two propriety judgment modes are available inside DMA. The implementation method of DMA is widely applicable to design high-performance processors and the structure is simple and reliable.
Description
Technical field
The present invention relates to the high-performance processor field, specially refer to a kind of on-chip DMA structure and its implementation.
Background technology
Data throughput capabilities is the key issue in the high performance processor design.For the common way of the handling capacity that improves the high-performance processor data is the data path bit wide of increase place processor or the frequency of handling up that improves data.These two kinds of methods all exist deficiency: first method, improve handling capacity by increasing data bit width, and the number of pins of processor can be increased sharply, and influences reliability of processor; Second kind of way, the frequency of handling up of raising data can directly cause the processing power consumption of processor too high.
Therefore in the design high-performance processor, can adopt the method that increases on-chip DMA (Direct MemoryAccess), improve the data throughput capabilities of high-performance processor.
DMA (Driect Memory Access) technology itself is that a kind of microprocessor that replaces is finished the method that mass data transmits between storer and external unit or the storer, also claims the direct memory access (DMA) method.In microsystem, the data transmission between peripheral hardware and internal memory normally realizes by one section program of CPU execution, but utilizes the DMA technology then can get involved the direct transmission that just can realize data between peripheral hardware and the internal memory without CPU.The major advantage of DMA is in the time need delivering to specified memory to the mass data of a peripheral hardware, it can finish the transmission task automatically, that is to say that peripheral hardware sends a DMA request, then dma circuit suspends the operation of CPU, and once pass number between control peripheral hardware and the internal memory, and then allow CPU continue executive routine, so just make CPU save a large amount of query times, thereby improved the overall performance of system peripheral hardware.The product of DMA mainly contains 8237 chips and 82258 chips that Intel (Intel) is produced.Wherein 8237 and 82258 is respectively to be applied to 8086CPU and 80386CPU is the system of process nuclear.Owing to do not have Interrupt Process function and system bus interface function, 8237 and 82258 when using in system, need interruptable controller (8259) and design system interface auxiliary logic, this makes system applies very loaded down with trivial details, and the work structuring of this DMA and implementation have also reduced the reliability of application system.
Along with the development of microelectric technique, the integrated level of single-chip improves constantly, and under such realization condition, the product that DMA improves data throughput capabilities occurred embedding in high-performance microprocessor.Mainly be TIX's (Texas Instrument, TI) She Ji MSP430 micro controller series and TMS320X240 series of products.All be to introduce in the majorityly from application process for the description of DMA in these product application data, all do not see as for its structure and specific implementation etc. to have a detailed description.
Domestic research for high-performance processor also just launched in recent years, about use the introduction of on-chip DMA in the high-performance processor of autonomous Design, did not appear in the newspapers.Domestic data about DMA also is at 8237 and 82258 and product such as L82C37A gains in depth of comprehension and the introduction how to use mostly.These DMA product ranges of application are narrow, application is complicated, are difficult to be integrated in the on-chip processor system of autonomous Design.
The present invention is that 32 high-performance digital signal processor SMDSP with autonomous Design are background, has designed structure and its implementation of a kind of on-chip DMA on SMDSP.Because it is simple in structure, realization is convenient, therefore is easy to be applied in the design of other high-performance processor.
Summary of the invention
The object of the present invention is to provide structure and its implementation of a kind of on-chip DMA that extensively is suitable for.And simple in structure, it is convenient to realize.
The technical solution used in the present invention is: a kind of on-chip DMA structure is characterized in that comprising:
Registers group is carried out initial configuration by the peripheral data bus to registers group by CPU before DMA work, determine DMA duty, data address value and promptly will transmit the number of data;
The priority arbitration unit, in when, between CPU and the DMA read/write conflict taking place when, the DMA/CPU priority arbitration is judged according to the signal that the interruptable controller of current transmission state and CPU transmits, whether give DMA control, when DMA acquires a priority when carrying out data transmission, determine whether needs arbitration according to the quantity of DMA inner passage, when the DMA inner passage is two or more, the priority arbitration unit is arbitrated, and determines which passage to carry out data transmission work;
The DMA data buffer register, the data I/O equipment that is used for buffer-stored low speed makes the message transmission rate of DMA and the processing speed of CPU be complementary to the data that DMA sends;
Interrupt to be provided with and receiving element, the one, when transmitting, DMA utilizes this unit that the respective interrupt zone bit is set in the system break register when finishing to represent that a data transfer finishes, and CPU can carry out respective handling according to this interrupt flag bit; The 2nd, when data I/O device ready, can send the interrupt request singal of request data transfer to system, this interrupt request singal is by interrupt being provided with and receiving element receives and the respective interrupt zone bit of system break register is provided with, and CPU carries out data transmission work according to configuration and the startup DMA that this interrupt flag bit carries out the DMA working method;
Add/subtract 1 steering logic,, add/subtract 1 steering logic and realize modification, promptly realize adding 1 or subtract 1 or the operation that remains unchanged data register in the registers group by the configuration of CPU to the global state control register in the registers group;
Dma bus comprises DMA address bus and DMA data bus, and what transmit on the DMA address bus is to read or to write the start address of data in storer; What transmit on the DMA data bus is the data that will read or write, is sent to inside or external memory storage after the data process DMA data buffer register transfer of its transmission.
When the DMA inner passage is two passage DMA0 and DMA1, the circuit structure of described interruption setting and receiving element is: connect the input of reverser inv_1 behind test signal TEST1 and the external interrupt signal EINT alternative selector switch M21_1 through control signal C1 and control signal C2 control, the output of inv_1 connects the input of two inputs and door and2_1, the input end of two input rejection gate nor2_1 is received in the output of two inputs and door and2_1, the output of two input rejection gate nor2_1 is as the input end of three Sheffer stroke gate nand3_1, circuit reset signal RESET receives another input end of two input rejection gate nor2_1, minimum two signal START[1 of overall situation control register] and START[0] meeting reverser inv_2 after meeting two input rejection gate nor2_2, second input end of three Sheffer stroke gate nand3_1 received in the output of reverser inv_2; The input signal DMAE that is used to select to carry out the DMA passage of data transmission outputs to the 3rd input end of three Sheffer stroke gate nand3_1 through reverser inv_3; The output of three Sheffer stroke gate nand3_1 connects the input end of the alternative selector switch M21_2 of control signal C3 and control signal C4 control, test signal TEST2 connects another input end of selector switch M21_2, the output of selector switch M21_2 connects the latch of being made up of inv_4 and inv_5, an output terminal of latch is interrupt identification signal INT_SIG, is connected to the input end of two inputs and door and2_1 behind the transmission gate TG of another output terminal welding system clock CLK control of latch through reverser inv_6.
When the DMA inner passage is two passage DMA0 and DMA1, the circuit structure of described DMA/CPU priority arbitration is: the control bit signal DMA1_PRI[1 of the overall control register of DMA inner passage DMA1] and enable signal DMA1_EN connect two input ends of two inputs and door and2_2, the control bit signal DMA0_PRI[1 of the overall control register of DMA inner passage DMA0] and enable signal DMA0_EN connect two input ends of two inputs and and2_3; Two inputs and door and2_2 and two inputs and the output terminal of door and2_3 are received two input ends of two input rejection gate nor2_3 respectively, and the outputs of two input rejection gate nor2_3 connect behind reverser inv_8 or the input of door or2_2; Status indicator signal DMA1_ST and DMA0_ST connect or the door or2_1 two inputs, or the input end of three Sheffer stroke gate nand3_2 is linked in the output of door or2_1, enable signal DMA_EN meets three Sheffer stroke gate nand3_2) another input, annular arbitrating signals CIR connects the 3rd input end of three Sheffer stroke gate nand3_2 after through reverser inv_7 negate; The output of three Sheffer stroke gate nand3_2 connects the input of reverser inv_9, the output of reverser inv_9 connect or the door or2_2 second input end; The control bit signal DMA1_PRI[0 of the overall control register of DMA inner passage DMA1] and enable signal DMA1_EN connects and two inputs of door and2_4, the control bit signal DMA0_PRI[0 of the overall control register of DMA inner passage DMA0] and enable signal DMA0_EN connects and two inputs of door and2_5; With the door and2_4 and the input of receiving two input rejection gate nor2_4 with two outputs of door and2_5, the output of rejection gate nor2_4 meets reverser inv_10; The output of reverser inv_10 and or the output of door or2_2 connect the input of two input nand gate nand2_1, the output of two input nand gate nand2_1 meets reverser inv_11, reverser inv_11 is output as priority arbitration signal DMA/CPU_PRI.
When the DMA inner passage is two passage DMA0 and DMA1, described adding/subtract,, the circuit structure of 1 steering logic was: control bit INCSRC in the overall control register and DECSRC connect two inputs with or the input of door xnor2_1, two inputs output same or door xnor2_1 connects first input end of three input nand gate nand3_3 through reverser inv_12, the signal WRE that is used to switch the read-write operation of DMA transmission connects second input end of three input nand gate nand3_3 behind reverser inv_13, the input signal DMAE that is used to select to carry out the DMA passage of data transmission connects the 3rd input end of three input nand gate nand3_3; Control bit INCDST in the overall situation control register and DECDST connect two and import together or the input of an xnor2_2, two inputs output same or door xnor2_2 connects first input end of three input nand gate nand3_4 through reverser inv_14, the signal WRE that is used to switch the read-write operation of DMA transmission connects second input end of three input nand gate nand3_4, and the input signal DMAE that is used to select to carry out the DMA passage of data transmission connects the 3rd input end of three input nand gate nand3_4; The output of three input nand gate nand3_3 meets reverser inv_15, and reverser inv_15 is output as the signal SRCAE that allows or do not allow source address register is carried out plus and minus calculation; The output of three input nand gate nand3_4 meets reverser inv_16, and reverser inv_16 is output as the signal DSTAE that allows or do not allow destination address register is carried out plus and minus calculation; The output of INCSRC and three input nand gate nand3_3 connects the input of two inputs or door or2_3; Control bit INCSRC in the overall situation control register and the output of three input nand gate nand3_4 connect the input of two inputs or door or2_4; The output of the output of two inputs or door or2_3 and two inputs or door or2_4 connects two input ends of two input nand gate nand2_2, the output of two input nand gate nand2_2 and system clock CLK connect two input ends of two input nand gate nand2_3 respectively, the output of two input nand gate nand2_3 meets reverser inv_17, and reverser inv_17 is output as the control signal INC that adds 1 operation; The control signal INC that adds 1 operation connects the input of reverser inv_18, and reverser inv_18 is output as the control signal DEC that subtracts 1 operation.
A kind of on-chip DMA implementation method is characterized in that: the DMA inner passage is at least one, and when the DMA inner passage was two or more, the implementation method of each passage was identical, and the implementation method of described DMA inner passage is as follows:
(1) carry out before data transmission begins at DMA, CPU carries out initial configuration by the peripheral data bus to the registers group of DMA channel interior earlier.Layoutprocedure is that the value on the peripheral hardware address bus is write enable signal through the decoding generation of address decoder, be used for a register of DMA registers group is carried out write operation, configuration data on the peripheral data bus is written in the relevant register when effective writing enable signal, and the configuration of a register is finished.After CPU wants each register in the DMA registers group to be configured, promptly finish the initial configuration of whole DMA.
(2) according to the initial configuration of CPU to the global state control register in the registers group of channel interior, add/subtract 1 steering logic to adding in the passage/subtract 1 module to control, realize the data register in the registers group is added 1 or subtract 1 or the operation that remains unchanged;
(3) according to the priority arbitration unit, interrupt to receive and be provided with the unit judges result and control gate which circuit-switched data is transferred on the DMA address bus, carry out data read, after data address has gone up the DMA address bus, data can be transported to the data buffer register of respective channel inside from storer following closely, select the data of which bar channel transfer are put on the DMA data bus through gate according to the arbitration result of priority arbitration unit again;
(4) judge by the output of comparer whether the value of a transmission number register is 0, i.e. end of transmission whether, when end of transmission, comparer can trigger to interrupt receiving and module is set and produce look-at-me to CPU, inform DTD, return the bus right to use, so far, one time the DMA data transfer procedure is finished.
When institute DMA inner passage was two passage DMA0 and DMA1, the implementation method of wherein said passage DMA0 was as follows:
(1) carry out before data transmission begins at DMA, CPU carries out initial configuration by the peripheral data bus to the registers group of passage DMA0 inside; CPU produces the signal of controlling collocation channel DMA0 registers group by the peripheral hardware address bus through the decoding of address decoder, and CPU control is also selected to be input to the signal that DMA0 adds/subtract 1 module by the register of first gate;
(2) according to the initial configuration of CPU to the global state control register in the registers group of passage DMA0 inside, DMA0 adds/subtracts 1 steering logic and the DMA0 in the passage is added/subtract 1 module controls, and transmission counter register, destination address register and source address register are added 1 or subtract 1 or the operation that remains unchanged;
(3) judged result of interrupting being provided with module and DMA0 mode bit module for reading and writing according to priority arbitration unit, DMA0 is controlled the 3rd gate which circuit-switched data is transferred on the DMA address bus, carry out data read, after data address has gone up the DMA address bus, data can be transported to the data buffer register of DMA0 inside from storer following closely, select the data of DM0 passage or DMA1 passage are sent on the DMA data bus through the 4th gate according to the arbitration result of priority arbitration unit again;
(4) judge by the output of DMA0 comparer whether the value of a transmission number register is 0, i.e. end of transmission whether, when end of transmission, the DMA0 comparer can trigger DMA0 and interrupt being provided with module generation DMA0 look-at-me DINT0 to CPU, inform DTD, return the bus right to use, so far, one time the DMA data transfer procedure is finished.
Described DMA carries out data transmission by the decision of the priority arbitration between two passage DMA0 and the DMA1 by which passage, and the implementation method of priority arbitration has two kinds: fixed priority and wheel change priority.Fixed priority is that acquiescence DMA0 or DMA1 have higher priority, and wheel to change priority be to drop to minimum principle according to the passage priority of service recently to arbitrate, this is to set according to the corresponding positions in the global state control register.
The present invention's beneficial effect compared with prior art:
(1) on-chip DMA structure of the present invention and its implementation are simple, cooperate easily with the sequential of other functional part, have improved the reliability of DMA work.
(2) on-chip DMA of the present invention has the priority arbitration of oneself and interrupts being provided with and receiving element, has alleviated the burden of CPU as much as possible, and both are complementary at transmitted data rates.
(3) on-chip DMA of the present invention has oneself independently data and address bus, can transmit 32 bit data.
Description of drawings
Fig. 1 is an on-chip DMA structure synoptic diagram of the present invention;
Fig. 2 is an on-chip DMA implementation method process flow diagram of the present invention;
Fig. 3 is a kind of interruption setting of the present invention and receiving element structural representation;
Fig. 4 is a kind of DMA/CPU priority arbitration structural representation of the present invention;
Fig. 5 is a kind of adding of the present invention/subtract 1 steering logic structural representation.
Embodiment
A kind of implementation method of on-chip DMA, the structure of DMA as shown in Figure 1.Wherein, the DMA registers group is by DMA global state control register, source address register, destination address register and transmission number register are formed, before DMA starts working at first by CPU by peripheral bus to the global state control register in the registers group, a source address and destination address register and transmission number register carries out initial configuration, promptly determines the duty (as the priority arbitration pattern and the read-write method of synchronization) of DMA, the start address value of data (data promptly the to be read first address in storer), the number of destination address value of data (being the first address of data in destination memory to be written) and data to be transmitted.
The priority arbitration unit comprises the priority arbitration between priority arbitration between the CPU/DMA and inner two passage DMA0 of DMA and the DMA1, in when, between CPU and the DMA read/write conflict taking place when, arbitrate promptly definite cpu bus control with this module, when DMA acquires a priority when carrying out data transmission, DMA1 and DMA0 two passages need be arbitrated and promptly determine which passage to carry out data transmission work.
The DMA data buffer register, the data I/O equipment that is used for buffer-stored low speed by the effect of DMA data buffer register, makes the message transmission rate of DMA and the processing speed of CPU be complementary to the data that DMA sends.
Interrupt to be provided with and receiving element, the one, when transmitting, DMA utilizes this unit that the respective interrupt zone bit is set in the system break register when finishing to represent that a data transfer finishes, and CPU can carry out respective handling according to this interrupt flag bit; The 2nd, when data I/O device ready, can send the interrupt request singal of request data transfer to system, this interrupt request singal is received by the interruption setting of DMA and receiving element and the respective interrupt zone bit of system break register is provided with, and CPU carries out the configuration of DMA working method and start DMA carrying out data transmission work according to this interrupt flag bit.
Add/subtract 1 steering logic by to the configuration of global state control register, source address register, a destination address register and transmission number register is made amendment, promptly add accordingly 1 or/subtract 1 operation.
Dma bus comprises DMA address bus and DMA data bus.What DMA address bus (24) went up transmission is to read or to write the start address of data in storer, and the address contents of its transmission is provided by source address and destination address register; What DMA data bus (32) was gone up transmission is the data that will read or write, is sent to destination memory after the data process DMA data buffer register transfer of its transmission.
The bit wide of DMA overall situation control register is 16, and structure is as shown in table 1 below.
The bit wide of the overall control register of table 1
| 16?15 | 14 | 13?12 | 11 | 10 | 9?8 | 7 | 6 | 5 | 4 | 3 2 | 1 0 |
| 0?0 | PRIORITY MODE | DMA?PRI | TCINT | TC | SYNC | DECDST | INCDST | DECSRC | INCSRC | STAT | START |
The function digit of DMA global controller is defined as follows shown in the table 2.
The mode bit definition of table 2DMA global controller
| Abbreviation | Reset values | Title | Describe |
| START | 00 | The DMA start-up control | Control DMA begins and halted state, is that the combination of START position and the reading or writing of operation Bitl bit0 function 00 DMA of DMA are finished not having to stop DMA transmission following table under the situation of obliterated data; Ignore reading of any data, cancel any undetermined reading or writing.DMA is reset and prepares next time beginning (reset values) 01 of transmission and stop to finish in the past a word that has begun at DMA and read or write.Do not begin if read or write, no longer include read and write so and 10 transmission (comprising read and write) that stop to finish in the past the data block that has begun at DMA take place, no longer include read and write so and 11 DMA take place restart from reset mode or preceding state if there is not transmission of data blocks.Finish when DMA once transmits, the START position remains on 11 when following any condition, the START position is set is 11 and restart transmission.When the value of the setting that transmits counter is not 0 for 0X0 TC position |
| STAT | 00 | Dma state | STAT specifies state and each cycle of DMA to upgrade, following table is STAT position and dma state: bit3 bit2 function 00 DMA are held between write and read, this is that value 01 DMA when resetting are held 10 to keep 11 DMA busy in the centre of read and write, comprise that the DMA execution reads or writes, wait for the source sync break, wait for the purpose sync break |
| INCSRC | 0 | The DMA source address increases progressively | Work as INCSRC=1, source address increases progressively after reading at every turn |
| DECSRC | 0 | The DMA source address is successively decreased | Work as DECSRC=1, source address is successively decreased at every turn after reading and is worked as INCSRC=DECSRC, does not revise source address after reading at every turn |
| INCDST | 0 | The DMA destination address increases progressively | Work as INCDST=1, destination address increases progressively after being write at every turn |
| DECDST | 0 | The DMA destination address successively decreases | Work as DECDST=1, destination address successively decreases at every turn after being write and works as INCDST=DECDST, does not revise destination address after writing at every turn. |
| |
0 | The DMA synchronous mode | The method of synchronization following table general introduction SYNC position and the DMA of source address and destination address are synchronous: Bit9 Bit8 function 00 is asynchronous, and it is synchronous to ignore interruption (reset values) 01 source addresses.When central broken hair was given birth to, it is synchronous that 10 destination addresses are read in execution.In the middle of broken hair when giving birth to, carry out write 11 source addresses synchronously and destination address synchronous.When central broken hair is given birth to, |
| Execution is read; When next interruption took place, execution was write | |||
| |
0 | The DMA transmission mode | Influence transmits the operation of counter.Work as TC=0, transmit counting and become at 0 o'clock, do not stop transmission and work as TC=1, t transmits counting and becomes at 0 o'clock, stops |
| TCINT | |||
| 0 | DMA transmits counter and interrupts | Work as TCINT=1, transmitting counter is 0 o'clock, DMA is set interrupts.Work as TCINT=0, transmitting counter is 0 o'clock, DMA is not set interrupts. | |
| PRI | 00 | The CPU/DMA mode of priority | PRI position definition CPU/DMA priority Bit13 Bit12 function 00 CPU priority be higher than DMA (this also is a reset values) 01 keep 10 priority in turn 11 DMA priority be higher than |
| PRIORITY MODE | |||
| 0 | DMA passage priority mode | As PRIORITY MODE=0, two DMA passage priority are fixed, and promptly |
Fig. 2 is the implementation method process flow diagram of DMA, and DMA is symmetrical binary channels, is that example describes with the DMA0 passage below:
The first step, carry out before data transmission begins at DMA, CPU carries out initial configuration by peripheral data bus (32bit) to the registers group (comprising global state control register, source address and destination address register, transmission counter register etc.) of DMA0 inside, promptly determines the working method (as the priority arbitration pattern and the read-write method of synchronization) of DMA, the start address value (data promptly the to be read first address in storer) of data, the destination address value (being the first address of data in destination memory to be written) of data and the number of data to be transmitted.Producing the signal of control configuration DMA0 registers group and control by peripheral hardware address bus (24bit) through the decoding of DMA0 address decoder in addition selects where organize register and is input to the signal that DMA0 adds/subtract 1 module by first gate.
Second step, initial configuration according to DMA0 global state control register, DMA0 adds/subtracts 1 steering logic and can add/subtract 1 module to DMA0 and control, and operand (data source address register, data destination address register and a data transmission number register) is added 1, subtracts 1 or the operation that remains unchanged.
The 3rd step, control the 3rd gate according to the judged result of DMA0 priority arbitration module, the synchronization control module of handling external interrupt signal EINT0 and mode bit module for reading and writing which circuit-switched data is transferred on the DMA address bus, carry out data read.After data address has gone up the DMA address bus, data can be transported to the data buffer register of DMA inside following closely from storer, selecting the data which bar passage (DMA0/DMA1) transmits are put on the DMA data bus through the 4th gate according to the judgement of mode bit and the arbitration result of priority control module.
The 4th step, judge that by the output of DMA0 comparer whether the value of a DMA0 transmission number register is 0 (promptly whether end of transmission), when end of transmission, it can trigger DMA0 and interrupt being provided with module and produce DMA0 look-at-me DINT0 and inform DTD to CPU, returns the bus right to use.Like this, a DMA data transfer procedure is finished.
What need further specify is that DMA carries out data transmission by DMA0 and two passages of DMA1, and decide by which passage by the arbitration result of DMA internal priority and to carry out data transmission, the implementation that priority is concrete has two kinds: fixed priority and wheel change priority, the former is that acquiescence DMA0 or DMA1 have higher priority, and the latter drops to minimum principle according to the passage priority of serving recently to arbitrate, and this is to set according to the corresponding positions in the global state control register; In addition, when having produced the data transmission conflict between DMA and the CPU, the signal that its DMA/CPU priority arbitration unit can transmit according to the interruptable controller of current transmission state and CPU is judged whether give DMA control.
Interrupt the receiving circuit structure, as shown in Figure 3: signal TEST1 and EI NT are through connecing the input of reverser inv_1 behind the alternative selector switch M21_1 of C1 and C2 control, the output of inv_1 inserts the input of two inputs and door and2_1, two inputs and the output of door and2_1 receive output to behind the two input rejection gates three with the input end of non-nand3_1.RESET receives another input of two input rejection gate nor2_1.START[1], START[0] meet reverser inv_2 after meeting two input rejection gate nor2_2, its output receive three with second input end of non-nand3_1.DMAE connect reverser inv_3 output to three with the 3rd input end of non-nand3_1.Three connect one of them input of the alternative selector switch M21_2 of C3 and C4 control with the output of non-nand3_1, and another is input as TEST2.The input of alternative selector switch M21_2 inserts the latch of being made up of inv_4 and inv_5, and this latch is output as INT_SIG, and connects by the input that is connected to two inputs and door and2_1 behind the transmission gate TG of CLK control through reverser inv_6.
Wherein TEST1 and EINT are respectively test and external interrupt signal, and process outputs to feedback loop by the MUX of the alternative of C1, C2 control.When circuit reset, RESET=1 puts 1 with an input signal of AND, and data result is by feedback hold reset value.Input signal START[1:0] be minimum two of overall control register, the start and stop of control DMA transmission.As START[1:0]=00 the time, end all ongoing transmission, prepare to carry out again new DMA transmission once.Input signal DMAE is used to select to carry out the DMA passage of data transmission, and when DMA finished certain read-write operation, this DMA passage free time, DMAE=0 waited for the appearance of sync break next time.If dma controller is set to not have under the synchronous mode of operation, then as long as certain passage is selected, then corresponding D MAE remains high level.After the output signal INT_SIG of circuit represented the DMA transmission start, whether the synchronizing signal that dma controller is waited for occurred, and this signal is that high level represents to have the sync break signal to occur.
DMA/CPU priority arbitration structure, as shown in Figure 4: DMA1_PRI[1] and DMA1_EN connect two input ends of two inputs and door and2_2, DMA0_PRI[1] and DMA0_EN connect two input ends of two inputs and an and2_3; Two inputs that two input rejection gate nor2_3 are received in two inputs and door and2_2 and two inputs and two outputs of door and2_3, the outputs of two input rejection gate nor2_3 connect behind reverser inv_8 or the input of door or2_2; DMA1_ST and DMA0_ST connect or the door or2_1 two inputs, or the output of door or2_1 link three with the input end of non-nand3_2, DMA_EN connect three with another input of non-nand3_2, CIR connect after through reverser inv_7 negate three with the 3rd input of non-nand3_2.Three connect the input of reverser inv_9 with the output of non-nand3_2, and the output of reverser inv_9 connects or second input end of door or2_2.DMA1_PRI[0] and DMA1_EN connects and two inputs of door and2_4, DMA0_PRI[0] and DMA0_EN connects and two inputs of door and2_5; With the door and2_4 and the input of receiving two input rejection gate nor2_4 with two outputs of door and2_5, the output of rejection gate nor2_4 meets reverser inv_10.The output of reverser inv_10 and or the output of door or2_2 connect the input of two input nand gate nand2_1, the output of two input nand gate nand2_1 meets reverser inv_11, reverser inv_11 is output as DMA/CPU_PRI.
Wherein, dma controller utilizes its inner dma bus transmission data, and when the access with CPU clashed, arbitration was absolutely necessary.When not having access conflict between them, the access of CPU and dma controller is parallel to be finished.Rules of arbitration are defined by the DMA PRI position in the DMA passage (be global state control register the 12nd and the 13rd), see table 1 for details.During system reset, overall control register will be cleared, and system default CPU is preferential.DMA PRI[1:0] be the 13rd and the 12nd in the overall control register, this value is provided with by the user, does not change before reprogramming.Signal CIR is the result of annular arbitration, and so-called annular arbitration is meant that the priority that CPU and DMA passage are set makes them take turns stream access, and when they in the continuous instruction cycle access conflict took place, CPU had higher priority; If in the cycle, when both took place the access conflict of same resource once more, DMA had higher priority at next instruction.During CIR=1, represent that this module CPU has access request.If have at least one same resource also proposed access request this moment in two passages of DMA, then there is conflict in the two.The priority of CPU or DMA which higher be to determine by global state control bit DMA PRI.DMA/CPU_PRI=0 represents CPU priority higher, and DMA/CPU_PRI=1 represents the DMA priority higher).
Add/subtract 1 steering logic structure, as shown in Figure 5: INCSRC and DECSRC connect two and import together or the input of an xnor2_1, two inputs output same or door xnor2_1 connects first input of three input nand gate nand3_3 through reverser inv_12, WRE connects second input of three input nand gate nand3_3 behind reverser inv_13, DMAE connects the 3rd input of three input nand gate nand3_3.INCDST and DECDST connect two and import together or the input of an xnor2_2, two inputs output same or door xnor2_2 connects first input of three input nand gate nand3_4 through reverser inv_14, WRE connects second input of three input nand gate nand3_4, and DMAE connects the 3rd input of three input nand gate nand3_4.The output of three input nand gate nand3_3 meets reverser inv_15, and reverser inv_15 is output as SRCAE.The output of three input nand gate nand3_4 meets reverser inv_16, and reverser inv_16 is output as DSTAE.The output of INCSRC and three input nand gate nand3_3 connects the input of two inputs or door or2_3; The output of INCDST and three input nand gate nand3_4 connects the input of two inputs or door or2_4.The output of the output of two inputs or door or2_3 and two inputs or door or2_4 connects two input ends of two input nand gate nand2_2, the output of two input nand gate nand2_2 and CLK connect two input ends of two input nand gate nand2_3 respectively, the output of two input nand gate nand2_3 meets reverser inv_17, and reverser inv_17 is output as INC.INC connects the input of reverser inv_18, and reverser inv_18 is output as DEC.
Wherein, INCSRC, DECSRC, INCDST, DECDST are the control bits in the overall control register, and the DMAE signal is used to select to carry out the DMA passage of data transmission, and the WRE signal is used to switch the read-write operation of DMA transmission.When WRE=0, carry out read operation, source address is carried out added 1, subtract 1 or invariant operation; When WRE=1, carry out write operation, will carry out destination address this moment and add 1, subtract 1 or invariant operation.CNTE will transmit numerical value with gating to be sent to the opposite signal of signal that adds/subtract 1 module, promptly be sent to when adding/subtracting in 1 module when the value of a transmission number register, and this CNTE=0 causes DEC=0, subtracts 1 and operates.In output signal, SRCAE represents to allow (1) or do not allow (0) that source address is carried out plus and minus calculation; DSTAE then represents to allow (1) or do not allow (0) that destination address is carried out plus and minus calculation.Signal DEC and I NC subtract 1 or add 1 control signal, are used for control and add 1/ and subtract 1 computing module, when output DEC=0, carry out and subtract 1 operation; When output INC=0, execution adds 1 operation.
Above-mentioned is to be that example has been set forth detailed performance of the present invention with two passages; when the DMA passage is one; realize will be easier; when DMA passage when being a plurality of,, can do adaptive variation to corresponding concrete structure etc. according to user's actual demand according to the detailed performance of two passages; only otherwise break away from the description scope of claims of the present invention; all in protection scope of the present invention, therefore, the present invention is widely.
Claims (7)
1, a kind of on-chip DMA circuit is characterized in that comprising:
Registers group is carried out initial configuration by the peripheral data bus to registers group by CPU before DMA work, determine DMA duty, data address value and promptly will transmit the number of data;
The priority arbitration unit, in when, between CPU and the DMA read/write conflict taking place when, the DMA/CPU priority arbitration of priority arbitration unit is judged according to the signal that the interruptable controller of current transmission state and CPU transmits, whether give DMA control, when DMA acquires a priority when carrying out data transmission, determine whether needs arbitration according to the quantity of DMA inner passage, when the DMA inner passage is two when above, the priority arbitration unit is arbitrated, and determines which passage to carry out data transmission work;
The DMA data buffer register, the data I/O equipment that is used for buffer-stored low speed makes the message transmission rate of DMA and the processing speed of CPU be complementary to the data that DMA sends;
Interrupt to be provided with and receiving element, the one, when transmitting, DMA utilizes this unit that the respective interrupt zone bit is set in the system break register when finishing to represent that a data transfer finishes, and CPU carries out respective handling according to this interrupt flag bit; The 2nd, when data I/O device ready, can send the interrupt request singal of request data transfer to system, this interrupt request singal is by interrupt being provided with and receiving element receives and the respective interrupt zone bit of system break register is provided with, and CPU carries out data transmission work according to configuration and the startup DMA that this interrupt flag bit carries out the DMA working method;
Add/subtract 1 steering logic,, add/subtract 1 steering logic and realize modification, promptly realize adding 1 or subtract 1 or the operation that remains unchanged data register in the registers group by the configuration of CPU to the global state control register in the registers group;
Dma bus comprises DMA address bus and DMA data bus, and what transmit on the DMA address bus is to read or to write the start address of data in storer; What transmit on the DMA data bus is the data that will read or write, is sent to internal storage or external memory storage after the data process DMA data buffer register transfer of its transmission.
2, a kind of on-chip DMA circuit according to claim 1, it is characterized in that: when the DMA inner passage is two passage DMA0 and DMA1, the circuit of described interruption setting and receiving element is: connect the input of reverser inv_1 behind test signal TEST1 and the external interrupt signal EINT alternative selector switch M21_1 through control signal C1 and control signal C2 control, the output of inv_1 connects the input of two inputs and door and2_1, the input end of two input rejection gate nor2_1 is received in the output of two inputs and door and2_1, the output of two input rejection gate nor2_1 is as the input end of three Sheffer stroke gate nand3_1, circuit reset signal RESET receives another input end of two input rejection gate nor2_1, minimum two signal START[1 of overall situation control register] and START[0] meeting reverser inv_2 after meeting two input rejection gate nor2_2, second input end of three Sheffer stroke gate nand3_1 received in the output of reverser inv_2; The input signal DMAE that is used to select to carry out the DMA passage of data transmission outputs to the 3rd input end of three Sheffer stroke gate nand3_1 through reverser inv_3; The output of three Sheffer stroke gate nand3_1 connects the input end of the alternative selector switch M21_2 of control signal C3 and control signal C4 control, test signal TEST2 connects another input end of selector switch M21_2, the output of selector switch M21_2 connects the latch of being made up of phase inverter inv_4 and phase inverter inv_5, an output terminal of latch is interrupt identification signal INT_SIG, is connected to the input end of two inputs and door and2_1 behind the transmission gate TG of another output terminal welding system clock CLK control of latch through reverser inv_6.
3, a kind of on-chip DMA circuit according to claim 1, it is characterized in that: when the DMA inner passage is two passage DMA0 and DMA1, the circuit of the DMA/CPU priority arbitration of described priority arbitration unit is: the control bit signal DMA1_PRI[1 of the overall control register of DMA inner passage DMA1] and enable signal DMA1_EN connect two input ends of two inputs and door and2_2, the control bit signal DMA0_PRI[1 of the overall control register of DMA inner passage DMA0] and enable signal DMA0_EN connect two input ends of two inputs and and2_3; Two inputs and door and2_2 and two inputs and the output terminal of door and2_3 are received two input ends of two input rejection gate nor2_3 respectively, and the outputs of two input rejection gate nor2_3 connect behind reverser inv_8 or the input of door or2_2; Status indicator signal DMA1_ST and DMA0_ST connect or the door or2_1 two inputs, or the input end of three Sheffer stroke gate nand3_2 is linked in the output of door or2_1, enable signal DMA_EN connects another input of three Sheffer stroke gate nand3_2, connects the 3rd input end of three Sheffer stroke gate nand3_2 after the annular arbitrating signals CIR process reverser inv_7 negate; The output of three Sheffer stroke gate nand3_2 connects the input of reverser inv_9, the output of reverser inv_9 connect or the door or2_2 second input end; The control bit signal DMA1_PRI[0 of the overall control register of DMA inner passage DMA1] and enable signal DMA1_EN connects and two inputs of door and2_4, the control bit signal DMA0_PRI[0 of the overall control register of DMA inner passage DMA0] and enable signal DMA0_EN connects and two inputs of door and2_5; With the door and2_4 and the input of receiving two input rejection gate nor2_4 with two outputs of door and2_5, the output of rejection gate nor2_4 meets reverser inv_10; The output of reverser inv_10 and or the output of door or2_2 connect the input of two input nand gate nand2_1, the output of two input nand gate nand2_1 meets reverser inv_11, reverser inv_11 is output as priority arbitration signal DMA/CPU_PRI.
4, a kind of on-chip DMA circuit according to claim 1, it is characterized in that: when the DMA inner passage is two passage DMA0 and DMA1, described adding/subtract,, the circuit of 1 steering logic was: control bit INCSRC in the overall control register and DECSRC connect two inputs with or the input of door xnor2_1, two inputs output same or door xnor2_1 connects first input end of three input nand gate nand3_3 through reverser inv_12, the signal WRE that is used to switch the read-write operation of DMA transmission connects second input end of three input nand gate nand3_3 behind reverser inv_13, the input signal DMAE that is used to select to carry out the DMA passage of data transmission connects the 3rd input end of three input nand gate nand3_3; Control bit INCDST in the overall situation control register and DECDST connect two and import together or the input of an xnor2_2, two inputs output same or door xnor2_2 connects first input end of three input nand gate nand3_4 through reverser inv_14, the signal WRE that is used to switch the read-write operation of DMA transmission connects second input end of three input nand gate nand3_4, and the input signal DMAE that is used to select to carry out the DMA passage of data transmission connects the 3rd input end of three input nand gate nand3_4; The output of three input nand gate nand3_3 meets reverser inv_15, and reverser inv_15 is output as the signal SRCAE that allows or do not allow source address register is carried out plus and minus calculation; The output of three input nand gate nand3_4 meets reverser inv_16, and reverser inv_16 is output as the signal DSTAE that allows or do not allow destination address register is carried out plus and minus calculation; The output of INCSRC and three input nand gate nand3_3 connects the input of two inputs or door or2_3; Control bit INCSRC in the overall situation control register and the output of three input nand gate nand3_4 connect the input of two inputs or door or2_4; The output of the output of two inputs or door or2_3 and two inputs or door or2_4 connects two input ends of two input nand gate nand2_2, the output of two input nand gate nand2_2 and system clock CLK connect two input ends of two input nand gate nand2_3 respectively, the output of two input nand gate nand2_3 meets reverser inv_17, and reverser inv_17 is output as the control signal INC that adds 1 operation; The control signal INC that adds 1 operation connects the input of reverser inv_18, and reverser inv_18 is output as the control signal DEC that subtracts 1 operation.
5, the implementation method of the described a kind of on-chip DMA circuit of claim 1 is characterized in that: the DMA inner passage is at least one, and the implementation method of each passage is identical when above when the DMA inner passage is two, and the implementation method of described DMA inner passage is as follows:
(1) carries out before data transmission begins at DMA, CPU carries out initial configuration by the peripheral data bus to the registers group of DMA channel interior earlier, be that value on the peripheral hardware address bus produces through the decoding of address decoder and writes enable signal, be used for a register of DMA registers group is carried out write operation, configuration data on the peripheral data bus is written in the relevant register when effective writing enable signal, the configuration of a register is finished, after CPU wants each register in the DMA registers group to be configured, promptly finish the initial configuration of whole DMA;
(2) according to the initial configuration of CPU to the global state control register in the registers group of channel interior, add/subtract 1 steering logic to adding in the passage/subtract 1 module to control, realize the data register in the registers group is added 1 or subtract 1 or the operation that remains unchanged;
(3) which circuit-switched data the judged result control gate according to priority arbitration unit, interruption setting and receiving element is transferred on the DMA address bus, carry out data read, after data address has gone up the DMA address bus, data can be transported to the data buffer register of respective channel inside from storer following closely, select the data of which bar channel transfer are put on the DMA data bus through gate according to the arbitration result of priority arbitration unit again;
(4) judge by the output of comparer whether the value of a transmission number register is 0, i.e. end of transmission whether, when end of transmission, comparer can trigger the interruption setting and receiving element produces look-at-me to CPU, inform DTD, return the bus right to use, so far, one time the DMA data transfer procedure is finished.
6, the implementation method of the described a kind of on-chip DMA circuit of claim 1 is characterized in that: the DMA inner passage is two passage DMA0 and DMA1, and the implementation method of wherein said passage DMA0 is as follows:
(1) carry out before data transmission begins at DMA, CPU carries out initial configuration by the peripheral data bus to the registers group of passage DMA0 inside; CPU produces the signal of controlling collocation channel DMA0 registers group by the peripheral hardware address bus through the decoding of address decoder, and CPU control is also selected to be input to the signal that DMA0 adds/subtract 1 module by the register of first gate;
(2) according to the initial configuration of CPU to the global state control register in the registers group of passage DMA0 inside, DMA0 adds/subtracts 1 steering logic and the DMA0 in the passage is added/subtract 1 module controls, and transmission counter register, destination address register and source address register are added 1 or subtract 1 or the operation that remains unchanged;
(3) judged result of interrupting being provided with module and DMA0 mode bit module for reading and writing according to priority arbitration unit, DMA0 is controlled the 3rd gate which circuit-switched data is transferred on the DMA address bus, carry out data read, after data address has gone up the DMA address bus, data can be transported to the data buffer register of DMA0 inside from storer following closely, select the data of channel transfer are sent on the DMA data bus through the 4th gate according to the arbitration result of priority arbitration unit again;
(4) judge by the output of DMA0 comparer whether the value of a transmission number register is 0, i.e. end of transmission whether, when end of transmission, the DMA0 comparer can trigger DMA0 and interrupt being provided with module generation DMA0 look-at-me DINT0 to CPU, inform DTD, return the bus right to use, so far, one time the DMA data transfer procedure is finished.
7, the implementation method of a kind of on-chip DMA circuit according to claim 6, it is characterized in that comprising: described DMA carries out data transmission by the decision of the priority arbitration between two passage DMA0 and the DMA1 by which passage, the implementation method of priority arbitration has two kinds: fixed priority and wheel change priority, fixed priority is that acquiescence DMA0 or DMA1 have higher priority, and wheel commentaries on classics priority is to drop to minimum principle according to the passage priority of serving recently to arbitrate, and this is to set according to the corresponding positions in the global state control register.
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| CN101339541B (en) * | 2008-08-11 | 2012-06-06 | 无锡中星微电子有限公司 | DMA data-transmission method and DMA controller |
| CN101634975B (en) * | 2009-08-20 | 2011-09-14 | 广东威创视讯科技股份有限公司 | Method for realizing DMA data transmission and apparatus thereof |
| CN101699418B (en) * | 2009-10-30 | 2011-11-16 | 曙光信息产业(北京)有限公司 | Interruption processing method, system and equipment |
| CN101833490B (en) * | 2010-03-31 | 2012-05-30 | 卡斯柯信号有限公司 | Information processing method of two out of two safe platform based on soft hardware difference |
| CN102231142B (en) * | 2011-07-21 | 2013-12-11 | 浙江大学 | Multi-channel direct memory access (DMA) controller with arbitrator |
| CN102831091B (en) * | 2012-07-31 | 2015-01-21 | 宁波成电泰克电子信息技术发展有限公司 | Serial port-based ship radar echo data collecting method |
| CN102929816A (en) * | 2012-11-02 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Radio frequency communication transceiver device utilizing memory controller to load programs and relative method |
| US20160092118A1 (en) * | 2014-09-26 | 2016-03-31 | Intel Corporation | Memory write management in a computer system |
| DE102016206350A1 (en) * | 2016-04-15 | 2017-10-19 | Robert Bosch Gmbh | Direct memory access controller |
| CN107315703B (en) * | 2017-05-17 | 2020-08-25 | 天津大学 | Dual priority control type fair arbiter |
| CN109471816B (en) * | 2018-11-06 | 2021-07-06 | 西安微电子技术研究所 | Descriptor-based PCIE bus DMA controller and data transmission control method |
| CN109597654B (en) * | 2018-12-07 | 2022-01-11 | 湖南国科微电子股份有限公司 | Register initialization method, basic configuration table generation method and embedded system |
| CN110865953B (en) * | 2019-10-08 | 2021-01-26 | 华南师范大学 | Asynchronous copying method and device |
| CN111666237B (en) * | 2020-06-08 | 2022-06-28 | 王斌 | DMA controller with cache management function |
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