CN100432968C - Direct access device of storage and data transmission method thereof - Google Patents
Direct access device of storage and data transmission method thereof Download PDFInfo
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- CN100432968C CN100432968C CNB2004100526742A CN200410052674A CN100432968C CN 100432968 C CN100432968 C CN 100432968C CN B2004100526742 A CNB2004100526742 A CN B2004100526742A CN 200410052674 A CN200410052674 A CN 200410052674A CN 100432968 C CN100432968 C CN 100432968C
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Abstract
The present invention relates to a direct memory access (DMA) device and a method thereof. The DMA device comprises a control register, a data bus and an address bus, a parameter RAM and at least one working engine, wherein the parameter RAM can be provided with a plurality of inlet ports, and the inlet ports, the data bus, the address bus and the working engine together form a data channel; the working engine comprises a data transmitting unit, an address computing unit and a global address memory. The DMA method comprises the steps that a central processor sends out a DMA transmission request; an arbitrator checks a preparing bit register of the data channel; the arbitrator arbitrates according to the value of the preparing bit register and informs the parameter RAM; the parameter RAM sets the working mode of the data channel; data is transmitted through collaborative work in the data channel.
Description
Technical field
(Direct Memory Access DMA) and data transmission method, relates in particular to a kind of direct memory access device that carries out data transfer operation quickly and easily in space, discontinuous address to the present invention relates to a kind of direct memory access device.
Background technology
In the image transmission epoch in vogue day by day, the high-speed transfer of view data becomes an important research project.Direct memory access device (DMA) is widely used in various processor systems, it can be directly with peripheral unit, be connected with the appropriate address of storer as all kinds of input-output apparatus, the data of directly carrying out between the two by bus transmit, also can directly between storer, carry out data transmission, it need be through the allotment of central processing unit, the speed of speeding up data transmission greatly.Therefore, adopt the DMA device to carry out image data transmission and also become a kind of usual way.
In the application of carrying view data, need set up model to the transmission of various types of data, and usually with the basic model of data block (Block) as data transmission.Often there are the characteristics that transport mode is various, addressing mode is complicated in the carrying of this class view data.Data block model shown in Figure 1A and 1B, the view data that at every turn is handled upside down comprise a plurality of data blocks 100, and each data block is made of a plurality of row 101 (Array), and a row then includes a plurality of continuous elements 111 (Element).Element address in the same row can be continuous, also can be equidistant in order the arrangement.The model array of data block is similar to the model array of element among Figure 1B among Figure 1A, and the inside of each the data block model array among Figure 1A constitutes the model array that is element among Figure 1B.When data block is carried, not only the plain bit with next data block of the last bit of a data block usually often is on discontinuous address, even in same data block, the plain bit element with next line of the last bit of delegation often also is on discontinuous address, and the element in the same delegation in the data block also may be on discontinuous address, like this, just the ability that data transmission devices such as DMA are carried out high speed data transfer in discontinuous space has proposed higher requirement.
A kind of basic model DMA device of the prior art is to adopt direct transmission manner to carry out the data carrying.When needing to transmit data fast at every turn, send the internal register that the DMA data transfer command is given DMA by central processing unit (CPU), order may comprise the data start address and the parameters such as end address and control word of data transmission, DMA carries out data transmission between peripherals and the storer by bus under the order of internal register control, and sends after the data transmission of end address is finished and interrupt giving central processing unit.Then wait for the next data transfer command of central processing unit afterwards.For the data transmission in space, discontinuous address, this DMA often needs repeatedly to send interruption to CPU, and waiting for CPU is sent the command dma that includes another initial address parameter again.The for example data of Figure 1A and Figure 1B carrying, just need send interruption when finishing in each data block carrying, if the also discontinuous address of the row in the data block, also may when each row carrying finishes, send interruption, even send interruption to CPU when each element carrying finishes in may needing to be expert to CPU.So both increased the work load of CPU, also increased time overhead, the phenomenon of obliterated data had especially taken place in high speed data transfer easily.
Chain type DMA is that the data transmission in space, discontinuous address has been made some improvement.Be provided with a plurality of dma controllers among the chain type DMA, each dma controller takies certain space and is used for the storage links descriptor in storer.The parameter that comprises in the linkage descriptor except with direct conveying type DMA in similarly start address and the data length etc., be used for describing the indicator linking parameter of the next address that DMA will visit in addition.Dispose a plurality of dma controllers for the transmission of satisfying part high capacity DMA data among this chain type DMA, and usually also can't effectively utilize idle dma controller.And command dma that CPU sends and the linkage descriptor of DMA all leave in the storer, have increased the complexity of design, also cause the waste of DMA resource.On the other hand, because chain type DMA needs to find command at any time and linkage descriptor, under the situation that has a plurality of orders to switch, may untimelyly cause loss of data from storer owing to what switch.
Also has a kind of queue-type DMA in the prior art.This queue-type dma controller includes the command register storehouse (Register bank) that a plurality of internal registers are formed, and a plurality of data transfer commands are housed in the command register storehouse simultaneously, loads a command dma in each internal register.Command dma in the command register storehouse is worked in the mode of order reach.Executing the order of an internal register at every turn, then continue the order of the next internal register of execution sequence reach, is zero up to the value of judging all registers, promptly no longer includes pending command dma in the command register storehouse.Though this queue-type DMA can accelerate command dma switching processing speed to a certain extent, do not eliminate chain type DMA waste resource and the complicated defective of design.
Summary of the invention
The object of the present invention is to provide a kind of simple in structure, can fast and effeciently transmit the direct memory access device (DMA) of the data message in space, discontinuous address flexibly and simultaneously.It comprises the control register that is used for storing the whole control information of DMA device, the data bus and the address bus that can carry out data transmission work, the parameter random access memory that is used for storing control parameter, moderator and at least one work engine, described work engine links to each other with control register, parameter random access memory and moderator by described bus, wherein said parameter random access memory can be divided into a plurality of inlets, and wherein each inlet constitutes a data channel with data bus, address bus and work engine.The global address storer that described work engine comprises data carrying unit, at least one address calculation and is coupled with described address calculation.Described global address storer just refreshes when being arranged in that address calculation is finished address computation and it being write result of calculation, and when different data channel was switched, address date wherein remained unchanged.Every described data channel all can be configured to operate under data transport mode or the plot computation schema.Described work engine comprises the streamline controller that is used for the co-ordination process.Described streamline is divided into level Four: the second preloaded level, the first preloaded level, operation level and storage level.
Another object of the present invention is to provide a kind of data transmission method of direct memory access device, described method comprises: accept the DMA transmission requests that central processing unit sends; Check the preparation bit register of data channel by moderator; Moderator is made arbitration and notifying parameters RAM according to the value of described preparation bit register; Parameters R AM sets the mode of operation of described data channel; And the data carrying is carried out in collaborative work between many described data channel.
In the first embodiment of the present invention, described data channel comprises first data channel and second data channel at least.Collaborative work mode between the described data channel is an on-link mode (OLM).The step that described parameters R AM sets the mode of operation of described data channel also comprises: described parameters R AM is set to the plot computation schema according to value first data channel of described preparation bit register, and second data channel is set to the data transport mode.The step that data carryings is carried out in collaborative work between the described data channel also comprises: set link enable register and hyperlink target channel register in the inlet of the pairing parameters R AM of each bar data channel; Activate the link enable register of first data channel, and the value of this data channel hyperlink target channel register is made as the number of another data channel; When the first preloaded level judgement of described first data channel has the link action, notify the register of its second preloaded level to remove to load the transmission parameter of second data channel; Described first data channel is calculated at the plot that this carries out new data block, and the result is left in the global address storer; Described second data channel is then taken out the plot of new data block from the global address storer, calculate the address of each data in the new data block in conjunction with transmission parameter, and carry accordingly; Second data channel judges in its first load stage whether this passage has the link action after this is carried out again, and notifies first data channel to load corresponding transmission parameter; And second data channel finish the carrying work of a data block, turn back to the address that first data channel is calculated next data block again.
In the second embodiment of the present invention, described data channel comprises first data channel, second data channel, the 3rd data channel and the 4th data channel at least.Collaborative work mode between the described data channel comprises on-link mode (OLM) and switching mode.The step that described parameters R AM sets the mode of operation of described data channel also comprises: described parameters R AM is set to the plot computation schema according to value first data channel of described preparation bit register, second data channel is set to the data transport mode, the 3rd data channel is made as the plot computation schema, and the 4th data channel is made as the data transport mode.The step that data carryings is carried out in collaborative work between the described data channel also comprises: set link enable register and hyperlink target channel register in the inlet of the pairing parameters R AM of each bar data channel; In the inlet of the pairing parameters R AM of second data channel, set and switch enable register; Activate the link enable register of first data channel, and the value of this data channel hyperlink target channel register is made as the number of another data channel; When the first preloaded level judgement of described first data channel has the link action, notify the register of its second preloaded level to remove to load the transmission parameter of second data channel; Described first data channel is calculated at the plot that this carries out new data block, and the result is left in the global address storer; Described second data channel is then taken out the plot of new data block from the global address storer, calculate the address of each data in the new data block in conjunction with transmission parameter, and carry accordingly; When needs insert the data transmission of new images, the switching enable register in the described second data channel transmission parameter is changed to 1, but the value of its switching target channel register still is the number of first data channel; Start the data carrying of new images from the outside; Third and fourth data channel is carried out the data carrying of new images in the mode identical with the data mode of transport of first, second data channel; After the new images carrying was finished, signaling second data channel continued the carrying of original image.
The present invention is provided with data carrying unit and address calculation in the work engine of DMA device, and in the work engine,, address calculation keeps in the address that calculates for having disposed corresponding global address storer, simultaneously correspondingly be provided with data transport mode and two kinds of mode of operations of plot computation schema for data channel, like this, data transmission for space, discontinuous address, can directly finish the evaluation work of address in inside by the DMA device, corresponding data channel is reference address from the global address storer of work engine directly, and needn't be by the outer address computation work of the computing unit commitment of outer CPU, also needn't repeatedly send the interrupt request address computation, perhaps finish address computation and assignment to the corresponding internal register of DMA device by the computing unit of CPU in advance as interlinkage and queue-type DMA device as basic model DMA device to CPU.Therefore, DMA device of the present invention not only can be saved repeatedly the time overhead that interrupts, and can reduce the idle of register hardware resource, can also guarantee that data transmission carries out effectively simultaneously.
On the other hand, among the present invention in the global address storer storage addresses only finish new address computation and just refresh during to its assignment in address calculation, and factor does not refresh according to the switching of passage, even therefore refreshing the preceding switching that data channel is arranged repeatedly, when address calculation is carried out address computation next time, still can take in the global address storer storage addresses as parameters calculated, that is to say that storage addresses can be repeatedly used in the global address storer, can be arranged on collaborative work under data transport mode and two kinds of mode of operations of plot computation schema as required in conjunction with the different pieces of information passage again, not only can accelerate the arithmetic speed of address calculation, more can make full use of the evaluation work that these limited resources of address calculation are finished multiplexed address.
Simultaneously, the present invention can finish the transmission of a series of continuous datas, as the complete transmission of piece image fast for many data channel of multi-channel DMA device provide two kinds of different collaborative work modes when adopting on-link mode (OLM) fully; When adopting on-link mode (OLM) to combine with switching mode, the transmission that can preferentially insert other data in finishing a series of continuous data transmission courses is as the transmission of other images of combination insertion in the transmission course of piece image.Like this, utilize the DMA device of the present invention progress of control data transmission flexibly, keep with extraneous synchronously, and can carry out the insertion transmission operation etc. of other data at any time.
Below in conjunction with accompanying drawing the present invention is made a detailed description.
Description of drawings
The following drawings is the aid illustration to exemplary embodiment of the present, to the elaboration of the embodiment of the invention, be to disclose feature of the present invention place, but do not limit the present invention in conjunction with the following drawings for further, same numeral is represented respective element or step among the embodiment among the figure, wherein:
Figure 1A is data block 100 carrying model synoptic diagram.
Figure 1B is the carrying model synoptic diagram of row 101 and element 111 in the data block.
Fig. 2 is an exemplary block diagram of direct memory access (DMA) device 200 of the present invention.
Fig. 3 A is that the data channel of direct memory memory storage of the present invention is formed synoptic diagram.
Fig. 3 B is the inner structure synoptic diagram of the parameters R AM 204 of direct memory memory storage of the present invention.
Fig. 4 is the inner structure synoptic diagram of the work engine 201,202 of direct memory memory storage shown in Figure 2.
Fig. 5 A and 5B are two exemplary configurations synoptic diagram of global address storer 301 of the present invention.
Fig. 6 is the inner structure synoptic diagram of the control register 203 of direct memory memory storage of the present invention.
Fig. 7 is an example with the carrying of piece image data block, and the workflow diagram 700 of on-link mode (OLM) is described.
Fig. 8 is an example with the carrying of two width of cloth view data, and link and switching mode collaborative work process flow diagram 800 are described.
Embodiment
In conjunction with the application shown in Figure 1A and the 1B content of the present invention is described in detail in the present embodiment.Fig. 2 is an exemplary block diagram of direct memory access (DMA) of the present invention (DMA) device 200, and this DMA device 200 mainly comprises control register 203, parameter random access memory (RAM) 204 and two working cells 214,215 of reading and writing.
Fig. 3 A is that the data channel of direct memory memory storage of the present invention is formed synoptic diagram.Among Fig. 3 A, can comprise many data channel in the DMA device 200 of the present invention, be that example describes at this to comprise 64 data channel, but as because of the needs on the function, the also setting of changeable passage should be included in the essential scope of the present invention equally.Corresponding one by one with data channel, parameters R AM 204 is divided into 64 inlets, stores the transmission parameter of corresponding data passage respectively.Article 64, data channel sharedly read work engine 201, write work engine 202, control register 203 and data bus and address bus (Fig. 2 illustrates) etc.In other words, i.e. each inlet and data bus, address bus and read or write work engine 201,202 and constitute a data channel together.With two work engines 201,202 of reading and writing the reading and writing operation is separated in the present embodiment, therefore, when two data channel respectively when carrying out read operation and write operation, two work engines 201,202 of reading and writing can be worked simultaneously, thereby improve data rate.In other embodiments, for satisfying the demand of many data channel concurrent workings, also can dispose more work engine and more data bus and address bus etc.Each work is provided with work register 404 (shown in Fig. 4) in engine 201,202, required all kinds of transmission parameters when can be used to the work of store data passage.
Fig. 3 B is the inner structure synoptic diagram of the parameters R AM 204 of direct memory memory storage of the present invention.Among Fig. 3 B, comprise a plurality of transmission parameter registers 301 in each inlet among the parameters R AM 204, the respectively control information of store data channel transmission data waits transmission parameters such as the source data address of pending data transmission and destination data address.According to the difference of the application of concrete data transmission, transmission parameter can also have different types.Application shown in Figure 1A and 1B, then can also comprise the element number in each row in source block and the destination data piece, side-play amount in source block and the destination data piece between the element address, the number of row in source block and the destination data piece, and the side-play amount of going in source block and the destination data piece etc.When data channel is in running order, be loaded onto with the stored transmission parameter of the corresponding inlet of this data channel among the parameters R AM 204 and read or write in the work engine 201,202, control reads or writes the work of work engine 201,202.
Fig. 4 is the inner structure synoptic diagram of the work engine 201,202 of direct memory memory storage shown in Figure 2.Referring to Fig. 4, each work engine 201,202 comprises a data carrying unit 402 and an address calculation 403 from logic function.Data carrying unit 402 is used for carrying out the carrying work of data; 403 calculating that are used for carrying out data address specially of address calculation.Work is provided with global address storer 401 corresponding to address calculation 403 in the engine 201,202, the address that can storage address computing unit 403 calculates, and can storage addresses wherein compose to after need to carry out data carrying work data channel.401 of global address storeies just refresh when address calculation 403 is finished address computation and it is write result of calculation, and different data channel is when switching, and the address date in the global address storer 401 still remains unchanged.Like this, as long as the operation that address calculation 403 does not have new address computation and refreshes global address storer 401, data channel in each work can be taken identical address date from global address storer 401, that is to say the address date repeated citing repeatedly in the global address storer 401.Like this, when utilizing many data channel collaborative works, can carry out the carrying of the data in space, discontinuous address easily.The needs of the big I of global address storer 401 when using are configured in advance, and its inner structure then can be defined by software according to demands of applications.
Application according to Figure 1A and 1B, wherein the row 101 of each data block 100 inside and element 111 have certain rules, the side-play amount of can be according to the plot of each data block 100 and wherein going calculate the start address of each row, and the address of calculating each element 111 in the trip according to the side-play amount between the element in the start address of row and the row.The plot of each data block 100 then must calculate in addition.
Corresponding to the application shown in Figure 1A and the 1B, as shown in Figure 4, each work engine 201,202 comprises a data carrying unit 402 and an address calculation 403.In the middle of present embodiment, the data carrying of adopting two data channel to work in coordination with to finish this application, two data channel are separately positioned on data porter operation mode and plot evaluation work pattern.In this is used, global address storer 401 needs the storage addresses data to have three grades, be respectively data block address, row address and element address, therefore, the inner structure of global address storer 401 also shown in Fig. 5 A, can be divided into data block address 501, row address 502 and element address 503 3 parts.Every part address can be provided with corresponding figure place by software according to address realm.Estimate that as the data block address then data block address part 501 can be arranged to 3 in 0 ~ 8; Row address estimates that then row address part 502 can be arranged to 4 in 0 ~ 16; Element address estimates that then element address part 503 can be arranged to 6 in 0 ~ 64.
At first, the data channel under the plot computation schema is finished the calculating of the plot of data block in address calculation 403, and a data block plot that calculates is stored in the global address storer 401.Carry out the carrying of each element in the data block then by the data channel under the data transport mode.In the handling process of a data block, the data channel under the data transport mode can continuous working, utilizes the plot of data block to carry out the calculating of each row address and element address in this data block and carries out the carrying of element simultaneously.
When the element data carrying in data block was finished, the data channel under the plot computation schema calculated the plot of next data block, and refreshes global address storer 401 with result of calculation; Data channel under the data transport mode is taken out the corresponding data block plot more again and is begun the data carrying work of next data block from global address storer 401.
For other application, for example, suppose that the address of each data block is made of two-dimensional data among Figure 1A, as (x, y); The address of each element is made of four parts, be data block address, row address and the interior element address of row of bidimensional, in this case, can correspondingly change the inner structure of global address storer 401, it is divided into four parts, promptly the data block address part 501 among Fig. 5 A is divided into data block x address portion and data block y address portion (seeing Fig. 5 B).Therefore the calculating of this two-dimensional data piece plot also is to adopt a data channel that is arranged under the plot computation schema to finish, and the row address in the data block and the calculating of element address and the carrying work of data still can adopt another data channel that is arranged under the data transport mode to finish.Be understandable that the inner structure of global address storer 401 can also adopt alternate manner to divide, and must belong within the scope of the present invention.
The view data that at every turn is handled upside down with reference to the database model shown in Figure 1A and the 1B comprises that a plurality of data blocks 100 are arranged, and each data block is made of a plurality of row 101 (Array), and a row includes a plurality of continuous elements 111 (Element).Element address in the same row can be continuous, also can be equidistant in order the arrangement.The model array of data block 100 is similar to the model array of element 111 among Figure 1B among Figure 1A, and the inside of each the data block 100 model array among Figure 1A constitutes the model array that is element 111 among Figure 1B.Therefore, the data block 100 during this is used can adopt identical address computation model with the element 111 in each data block.Like this, for the plot calculating of data block and the address computation of row and element, can the multiplex data address calculation.That is to say, what the data channel under data porter's operation mode was carried out can calculate a multiplexing data address calculation with the plot to data block that the data channel under the plot evaluation work pattern is carried out to the row and the simple address computation of element, thereby has simplified the hardware configuration of DMA device.Certainly, also can adopt a plurality of data address computing units to reach different address computation, not influence enforcement of the present invention.
With reference to Fig. 4, utilize the data carrying unit 402 and the address calculation 403 of work engine 201,202, each data channel all possesses at least two kinds of different mode of operations, i.e. data transport mode and plot computation schema.By carrying out software setting, every data channel can be specified under wherein any mode of operation works.In the present embodiment, in the transmission parameter register of each inlet, be provided with mode of operation (WM) position, the control information of depositing designation data passage mode of operation.For example, a WM position can be set in the transmission parameter register, when WM was 0, data channel was worked with the data transport mode; When WM was 1, data channel was with the work of plot computation schema, and vice versa.And the value of WM position can be provided with decision by software.
With reference to Fig. 2, the control register 203 of DMA device 200 is one group of register, be used for storing the control information of DMA device configured in one piece, for the work engine 201 in the DMA device 200,202 and other controllers etc. be all the time as seen, can call the required loading action of information in need not similar call parameters RAM 204 when calling the control information in the control register 203 at any time.Control register 203 comprises prepares bit register 601 and SYN register 602 (see figure 6)s etc.Prepare bit register and be made of a plurality of positions, every data channel is corresponding with one of them, is provided with 64 data channel in the present embodiment, then prepares bit register and has 64 at least.When the pairing preparation of data channel position for example is 1, show that this data channel is ready, can respond synchronous event; When the pairing preparation of data channel position for example is 0, show that this data channel can not respond any synchronous event.Usually, at every turn will be after software is finished a data channel configuration with the ready position 1 of this data channel correspondence, like this, when synchronous event took place, this data channel just can commence work without delay.
Be provided with moderator 205 in the DMA device 200 of Fig. 2, can arbitrate the DMA transmission requests that source device sent that a plurality of different transmission that DMA device 200 is connected is operated, determine the DMA transmission requests of priority processing, thereby solve that a plurality of DMA request proposes simultaneously and the various conflicts that produce.The source device here can be the interior subsystem or the processor of computer system at DMA device 200 places, also can be peripherals etc.The input end of moderator 205 is accepted the DMA transmission requests from each transmission operate source equipment, and output terminal then links to each other with work engine 201,202, is sent to work engine 201,202 with the DMA transmission requests of the need priority processing that in time arbitration drawn and handles.Simultaneously, in the DMA device 200 data buffer 207 can also be set, as FIFO.When carrying out write operation, the data in advance that source device mails to the DMA device leaves in the data buffer 207, the data accumulation of depositing in the data buffer 207 is during to the data volume of predefined, and DMA device 200 is carried the data of data buffer 207 to target device with regard to beginning.Whether the setting of data buffer 207, and quantity is set can be determined by actual needs, but the present invention be there is no substantial influence.
In addition, for improving the work efficiency of DMA device 200, can adopt the multi-stage pipeline mode to the work of DMA device 200.With reference to figure 2, can be with the writing working cell 215, read working cell 214 and be divided into level Four respectively of DMA device 200, and utilize streamline controller 208 and 208 ' to coordinate the progress of work of each level production line.Level Four streamline line shown in Figure 2 is respectively the second preloaded level 209 and 209 ', the first preloaded level 210 and 210 ', operation level 211 and 211 ' and storage level 212 and 212 '.The transmission parameter of the data channel that the second preloaded level 209 and 209 ' will be worked the next one is loaded into work engine 201, the preloaded register of work register 404 (see figure 4)s in 202, like this, finish in the work of current data channel transfer, next bar data channel will enter operation level 211, can be directly in the time of 211 ' in work engine 201,202 start-up operation, and need not load transmission parameters from parameters R AM 204 again; The first preloaded level, 210,210 ' data channel receives the data from the preloaded register, and judges whether this data channel transmissions links can take place after this DMA transmission work is finished; Operation level 211,211 ' finishes DMA transmission operation, carries out the transmission of data by data bus, or finishes the calculating of address, and send interruption after work executes; Storage level 212,212 ' then is to write back parameter, and judges according to the transmission parameter of data channel whether this data channel transmission takes place switch, to operate accordingly.As indicated above, data channel can be operated under data transport mode or the plot computation schema by setting.Therefore, in the first preloaded level 210,210 ', parameters R AM 204 is sending into streamline controller 208 corresponding to the controlled variable of the data channel that will carry out the DMA transmission; At operation level 211, the mode of operation that is provided with in the controlled variable of 211 ' middle work engine 201,202 according to streamline controller 208 is carried out data carrying or address computation; At storage level 212,212 ' then checks the collaborative work mode.
Usually include many data channel in the DMA device, utilize the collaborative work of data channel to finish the continuous carrying task of mass data.The present invention provides two kinds of different collaborative work modes for the data channel of DMA device, and a kind of is on-link mode (OLM), and another kind is a switching mode.This dual mode of utilization between many passages, combined crosswise becomes the cooperative work mode of various complexity, still belongs within the scope of the present invention.Will be at this with first data channel and second data channel, the collaborative work of two data channel is an example, makes an explanation.
Fig. 3 B is the inner structure synoptic diagram of the parameters R AM 204 of direct memory memory storage of the present invention.In parameters R AM 204, all be provided with every corresponding inlet of data channel and link enable register 302 and hyperlink target channel register 303.When needs used the work of collaborative first data channel of on-link mode (OLM) and second data channel to transmit, the enable register 302 that links that earlier will be corresponding with first data channel of formerly working activated, and has promptly opened the linking functions of first data channel.Then, in parameters R AM 204 with in the corresponding inlet of first data channel, the passage number of the target data passage that will be connected is set, the i.e. passage number of second data channel in this example.When the second preloaded level of first data channel, the work engine load among the parameters R AM 204 with the corresponding inlet of first data channel in the transmission parameter deposited, wherein the transmission parameter of Zhuan Zaiing has comprised the value that links enable register 302 and hyperlink target channel register 303.When first data channel begins to enter the first preloaded level of streamline at the work engine, can judge automatically whether this passage linked operation can take place after this is complete.When find with the corresponding enable register 302 that links of this passage state of activation (promptly being set as 1), then check the destination channel number in the hyperlink target channel register 303, simultaneously, notice work engine is the transmission parameter of second data channel to the transmission parameter of parameters R AM 204 loading target data passages at this.Like this, still when operation level carried out address computation or data carrying, second data channel just can enter the second preloaded level transmission parameter is loaded into the work engine first data channel.Second data channel transmission parameter load finish after, the stream line operation after can continuing, and interruption that need not inside and outside portion excites.
Switching mode and on-link mode (OLM) are similar, all are provided with switching enable register 304 and switching target channel register 305 among the parameters R AM 204 with in every corresponding inlet of data channel.When needs used the work of collaborative first data channel of switching mode and second data channel to transmit, switching enable register 304 that earlier will be corresponding with first data channel of formerly working activated, and has promptly opened the handoff functionality of first data channel.Then, in parameters R AM 204 with in the corresponding inlet of first data channel, the passage number of the target data passage that will be connected is set, at this i.e. passage number of second data channel.Different with on-link mode (OLM) is, switching mode is when first data channel enters the storage level of streamline, just checks the operation that whether can switch after this is complete of this passage.When find with the corresponding switching enable register 304 of this passage in state of activation, just check the destination channel number in the switching target channel register, the destination channel number is second data channel in this example, and the notice control register puts 1 with the preparation position (READY) of second data channel.Under switching mode, first data channel is not under on-link mode (OLM), directly activate the work of second data channel, and just make second data channel enter the standby condition that can respond synchronous event, the interruption that needs inside or outside just can excite second data channel to start working.
For the application shown in Figure 1A and the 1B, adopt link and switching mode can coordinate the carrying that view data is finished in each data channel collaborative work effectively.And on-link mode (OLM) and switching mode also can be divided into dissimilar, are divided into element link, row link and block chaining as on-link mode (OLM), and switching mode is divided into the element switching, row switches and piece switches.Under element link/switching mode, when data channel has enabled this function, behind the intact element of the every transmission of data channel the once action of link/switching just takes place; Under the link/switching mode of being expert at, when data channel had enabled this function, the once action of link/switching just took place in the intact row back of the every transmission of data channel; Under block chaining/switching mode, when data channel has enabled this function, after the intact data block of the every transmission of data channel the once action of link/switching just takes place.When dissimilar link/switchings occurs simultaneously and clashes, the link/change action of a type that execution priority is the highest then.For example can stipulate that priority order is: block chaining/switching has precedence over row link/switching, and row link/switching has precedence over element link/switching, yet this is not to be restrictive.
Fig. 7 is an example with the carrying of piece image data block, and the workflow diagram 700 of on-link mode (OLM) is described.Among Fig. 7, be that collaborative work is the process flow diagram 700 that example illustrates carrying how to carry out piece image to adopt two data channel to link alternately, yet data channel can be not limited to two.At first, in step 701, send the DMA transmission requests by CPU; In step 703, moderator then can go to check the operating position of passage; In step 705, be all 1 o'clock as the preparation bit register of first data channel and second data channel, moderator will be made arbitration, and notifying parameters RAM; In step 707, parameters R AM is set to the plot computation schema to first data channel, and second data channel is set to the data transport mode; In step 709, the link enable register of first data channel is activated, and the value of hyperlink target channel register is made as the number of second data channel; In step 713, if judging in the first preloaded level of streamline, first data channel after this time carried out the link action is arranged, will notify the register of the second preloaded level to remove to load the transmission parameter of second data channel; In step 713, first data channel is used for the plot of each data block is calculated at operation level specially, and the plot that calculates is temporary in corresponding global address storer 301; In step 715, second data channel is according to the plot of the data block of taking out in the global address storer 301, according to this start address of each row and the address of element in the computational data piece; In step 717, data begin according to the address, are moved into by source device and read working cell 214, pass through data buffer FIFO 207 and write working cell 215, remove to target device successively.
Similarly, in step 719, whether second data channel can be judged this passage in first load stage of streamline the link action will take place after this is carried out, and promptly link enable register and whether be set to 1.If the link enable register is set to 1, then return step 711, repeating step 711 to 717.The carrying of entire image is finished in the collaborative work by two data channel that moves in circles like this.Be not set to 1 if in step 719, judge the link enable register, then send interruption, power cut-off.
Fig. 8 is an example with the carrying of two width of cloth view data, and link and switching mode collaborative work process flow diagram 800 are described.That is to say, in the carrying of first width of cloth image, may insert the dma operation of other image, now illustrate with four passages, if be responsible for the carrying of original image with first data channel and second data channel, and handle the carrying of new images with the 3rd data channel and the 4th data channel, by that analogy.Wherein the 3rd data channel mode of operation is set to the plot computation schema of new images, is responsible for the data block plot and calculates; The 4th data channel mode of operation is made as the data transport mode of new images, is responsible for each the data block internal data address computation and the data carrying work of new images.Yet the mode of operation that the number of described data channel and each bar data channel are selected is also nonrestrictive.
Step 701-705 among Fig. 8 is identical with step 701-705 shown in Figure 7.And in step 807, similar with the step 707 among Fig. 7, parameters R AM is made as the plot computation schema with first data channel, second data channel is made as the data transport mode, and first data channel and second data channel is carried out the carrying of original image with on-link mode (OLM).In the time need in the original image transmission course, inserting the data transmission of new images, in step 807 ' in, sending the DMA transmission requests of new images by CPU or other subsystem, moderator is checked the operating position of passage to control register.。In step 809, the switching enable register 304 of second data channel is changed to 1 (promptly activating), but the value of its switching target channel register 305 still is the number of first data channel.At this moment, second data channel is finished the carrying of certain data block in the original image, and do not finish the carrying of view picture original image, but be switching working mode because of detecting at storage level, therefore the carrying work of original image will be in halted state, and the synchronizing signal of sending after the transmission of needs wait new images is finished just can be restarted the carrying of original image.This moment can be in step 807 ' start the data carrying of new images with synchronizing signal from the outside.Similarly, also be with the on-link mode (OLM) collaborative work between the 3rd data channel of the DMA transmission of processing new images and the 4th data channel, until the transmission of finishing new images.In step 811, be 1 as the preparation bit register of the 3rd data channel, moderator will be made arbitration, and notifying parameters RAM204.In step 813, parameters R AM 204 is made as the plot computation schema with the 3rd data channel, and the 4th data channel is made as the data transport mode, carries out the carrying of new images.In step 815, after the new image data carrying is finished, can send synchronizing signal at any time, switch and get back to second data channel.In step 817, continue the data carrying work that original image suspends by first and second data channel again, until finishing.Send interruption then, power cut-off.
If between the data block of original image, insert the data transmission of new images, need the on-link mode (OLM) in the second data channel transmission parameter is made as the block chaining mode, in like manner, if between the row of original image or element, insert the data transmission of new images, just the on-link mode (OLM) in the second data channel transmission parameter is made as row link or element on-link mode (OLM), this is not to be restrictive.
Present embodiment is just in order further more clearly to describe the present invention, but not limitation of the present invention.Be to be understood that the present invention is not limited to the elaboration that embodiment does, anyly all should be encompassed within the spirit and scope of claim of the present invention based on modification of the present invention and equivalent of the present invention.
Claims (10)
1. direct memory access device, comprise and be used for control register, the data bus that carries out data transmission work and the address bus of the whole control information of memory direct access device, the parameter random access memory that is used for storing control parameter, moderator and at least one work engine, described work engine links to each other with control register, parameter random access memory and moderator with address bus by described data bus, it is characterized in that:
Described parameter random access memory is divided into a plurality of inlets, wherein each inlet and data bus, address bus and work engine constitute a data channel together, described work engine comprises data carrying unit, at least one address calculation, and with the global address storer of described address calculation coupling, wherein said global address storer be used for address that the storage address computing unit calculated and can stored address compose to after need to carry out data carrying work data channel, described global address storer just refreshes when address calculation is finished address computation and the global address storer write result of calculation, and when different data channel was switched, the address date in the global address storer remained unchanged.
2. direct memory access device as claimed in claim 1 is characterized in that, every described data channel all is configured to operate under data transport mode or the plot computation schema.
3. direct memory access device as claimed in claim 1, it is characterized in that, described work engine comprises the streamline controller that is used for the co-ordination process, streamline is divided into the level Four that links to each other successively in the following order: the second preloaded level, the first preloaded level, operation level and storage level, wherein
The transmission parameter of the data channel that the second preloaded level will be worked the next one is loaded into the preloaded register of work register in the work engine;
The first preloaded level receives the data from the preloaded register, and judges whether this data channel transmissions links can take place after this direct memory access transmission work is finished;
Operation level is finished direct memory access transmission operation, carries out the transmission of data by data bus, or finishes the calculating of address and send interruption after work executes;
Storage level writes back parameter, and judges according to the transmission parameter of data channel whether this data channel transmission takes place switch.
4. method that adopts the direct memory access device to carry out high speed data transfer, described method comprises:
Accept the direct memory access transmission requests that central processing unit sends;
Check the preparation bit register of data channel by moderator;
Moderator is made arbitration and notifying parameters random access memory according to the value of described preparation bit register;
Parameter random access memory is set the mode of operation of described data channel; And
The data carrying is carried out in collaborative work between many described data channel, and the collaborative work mode between the wherein said data channel is on-link mode (OLM) and/or switching mode,
Described parameter random access memory is divided into a plurality of inlets, wherein each inlet and data bus, address bus and work engine constitute a data channel together, described work engine comprises data carrying unit, at least one address calculation, and with the global address storer of described address calculation coupling, wherein said global address storer be used for address that the storage address computing unit calculated and can stored address compose to after need to carry out data carrying work data channel, described global address storer just refreshes when address calculation is finished address computation and the global address storer write result of calculation, and when different data channel was switched, the address date in the global address storer remained unchanged.
5. method as claimed in claim 4 is characterized in that, described data channel comprises first data channel and second data channel at least.
6. method as claimed in claim 5, it is characterized in that, the step that described parameter random access memory is set the mode of operation of described data channel also comprises: described parameter random access memory is set to the plot computation schema according to value first data channel of described preparation bit register, and second data channel is set to the data transport mode.
7. method as claimed in claim 6 is characterized in that, the step that data carryings is carried out in collaborative work between the described data channel also comprises:
In the inlet of the pairing parameter random access memory of each bar data channel, set link enable register and hyperlink target channel register;
Activate the link enable register of first data channel, and the value of this data channel hyperlink target channel register is made as the number of second data channel;
When the first preloaded level judgement of described first data channel has the link action, notify the register of its second preloaded level to remove to load the transmission parameter of second data channel;
Described first data channel is calculated at the plot that this carries out new data block, and the result is left in the global address storer;
Described second data channel is then taken out the plot of new data block from the global address storer, calculate the address of each data in the new data block in conjunction with transmission parameter, and carry accordingly;
When first load stage of second data channel judges that this passage has the link action after this is carried out, notify first data channel to load corresponding transmission parameter; And
Second data channel is finished the carrying work of a data block, turns back to the address that first data channel is calculated next data block again.
8. method as claimed in claim 4 is characterized in that, described data channel comprises first data channel, second data channel, the 3rd data channel and the 4th data channel at least.
9. method as claimed in claim 8, it is characterized in that, the step that described parameter random access memory is set the mode of operation of described data channel also comprises: described parameter random access memory is set to the plot computation schema according to value first data channel of described preparation bit register, second data channel is set to the data transport mode, the 3rd data channel is made as the plot computation schema, and the 4th data channel is made as the data transport mode.
10. method as claimed in claim 9 is characterized in that, the step that data carryings is carried out in collaborative work between the described data channel also comprises:
In the inlet of the pairing parameter random access memory of each bar data channel, set link enable register and hyperlink target channel register;
In the inlet of the pairing parameter random access memory of second data channel, set and switch enable register;
Activate the link enable register of first data channel, and the value of this data channel hyperlink target channel register is made as the number of second data channel;
When the first preloaded level judgement of described first data channel has the link action, notify the register of its second preloaded level to remove to load the transmission parameter of second data channel;
Described first data channel is calculated at the plot that this carries out new data block, and the result is left in the global address storer;
Described second data channel is then taken out the plot of new data block from the global address storer, calculate the address of each data in the new data block in conjunction with transmission parameter, and carry accordingly;
When needs insert the data transmission of new images, the switching enable register in the described second data channel transmission parameter is changed to 1, but the value of its switching target channel register still is the number of first data channel;
Start the data carrying of new images from the outside;
Third and fourth data channel is carried out the data carrying of new images in the mode identical with the data mode of transport of first, second data channel;
After the new images carrying was finished, signaling second data channel continued the carrying of original image.
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| CN101510183B (en) * | 2009-03-23 | 2011-05-11 | 华为技术有限公司 | Data transportation processing method and apparatus |
| TWI465905B (en) | 2010-09-22 | 2014-12-21 | Toshiba Kk | Memory system having high data transfer efficiency and host controller |
| JP5614420B2 (en) * | 2012-03-09 | 2014-10-29 | カシオ計算機株式会社 | Musical sound generating apparatus, electronic musical instrument, program, and musical sound generating method |
| JP6176058B2 (en) * | 2013-10-29 | 2017-08-09 | 株式会社ソシオネクスト | Direct memory access control device, control method thereof, and information processing system |
| KR20200090031A (en) * | 2019-01-18 | 2020-07-28 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
| CN111913898B (en) * | 2019-05-10 | 2024-07-09 | 恩智浦美国有限公司 | PCIE root complex message interrupt generation method using endpoint |
| US11003606B2 (en) * | 2019-06-21 | 2021-05-11 | Microchip Technology Incorporated | DMA-scatter and gather operations for non-contiguous memory |
| CN112732603A (en) * | 2019-10-14 | 2021-04-30 | 广州飒特红外股份有限公司 | Multi-channel VDMA control method and application thereof |
| CN111782154B (en) * | 2020-07-13 | 2023-07-04 | 芯象半导体科技(北京)有限公司 | Data moving method, device and system |
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