CN100511207C - Communication method between two processors - Google Patents
Communication method between two processors Download PDFInfo
- Publication number
- CN100511207C CN100511207C CNB2007100639424A CN200710063942A CN100511207C CN 100511207 C CN100511207 C CN 100511207C CN B2007100639424 A CNB2007100639424 A CN B2007100639424A CN 200710063942 A CN200710063942 A CN 200710063942A CN 100511207 C CN100511207 C CN 100511207C
- Authority
- CN
- China
- Prior art keywords
- processor
- interrupt
- communication
- memory block
- interruption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
This is a communication method for dual-processors. The DRAM is divided into four non-overlapping memory regions: the first storage area, the second storage area, the third storage areas and the fourth storage area. The second processor alternately triggered the first processor's interrupt periodically: first interrupt and the second interrupt. After the first interrupt is triggered, before triggering the second interrupt, the second processor reads the communication data stored in the first storage area, and writes the communication data to the third storage area. As a response to the first interrupt, the first processor writes the communication data in the second storage area, and reads the communication data stored in the fourth storage area. After the second interrupt is triggered, before triggering the first interrupt, the second processor reads the communication data stored in the second storage area, and writes the communications data to the fourth storage area. As a response to the second interrupt, the first processor writes the communication data in the first storage area, and read the communication data in the third storage area.
Description
Technical field
The present invention relates to a kind of means of communication of multiprocessor, relate in particular to the method for carrying out communication by DPRAM (Dual Port RAM, dual-port random access memory) between a kind of dual processor.
Background technology
In the field of widely-used computer systems such as communication, multimedia processing, along with improving constantly of data volume of handling and complexity, the system that comprises a processor has been difficult to satisfy the requirement of user to real-time and processing power.Therefore, large complicated system comprises two or more processors usually, and each processor is finished task separately.In addition, in some system, also need to use dissimilar processors to finish different tasks.For example, control function and data operation are transferred to different processors respectively handle, to reach best system performance.
As a system, need the real-time exchange data could guarantee to work in coordination with between a plurality of processors and work concurrently.A plurality of processors can be linked together in the mode of bus and realize exchanges data between the processor.But adopt this mode, usually need to use VME (Versa ModuleEurope, the Europe general module) waits the bus structure of support multiprocessor that system is designed, and need manage on the device the same operating system of operation throughout and could carry out synchronous and mutual exclusion effectively.Therefore this mode scope of application is less, and cost is higher.
Based on above reason, in the system that comprises two processors, adopt shared storage to carry out the mutual of message and data usually, to realize two communications between the processor device, shared storage adopts DPRAM usually.But adopt this mode also to need to design special bus control circuit to realize of the timesharing visit of two processors to DPRAM.This has increased the difficulty and the cost of hardware design, and dirigibility and versatility are relatively poor.
Summary of the invention
Technical matters to be solved by this invention is, overcome in the prior art deficiency of the means of communication between two processors, a kind of method that adopts DPRAM and specific communications protocol to realize the real-time communication between two processors is proposed, reduction improves dirigibility and universal to the degree of dependence of hardware circuit.
In order to address the above problem, the present invention proposes the means of communication between a kind of dual processor, is applied to comprise in the system of first processor, second processor and DPRAM, and wherein, described first processor, second processor link to each other with the different port of DPRAM respectively; Second processor triggers the interruption of first processor; It is characterized in that, in DPRAM, mark off 4 nonoverlapping storage areas: first memory block, second memory block, the 3rd memory block and the 4th memory block; Second processor periodically alternately triggers the interruption of first processor: first interrupts and second interruption;
Trigger first interrupt after, trigger second interrupt before, second processor reads the communication data of preserving in first memory block, and writes communication data in the 3rd memory block;
As the response to first interruption, first processor writes communication data in second memory block, and reads the communication data of preserving in the 4th memory block;
Trigger second interrupt after, trigger first interrupt before, second processor reads the communication data of preserving in second memory block, and writes communication data in the 4th memory block;
As the response to second interruption, first processor writes communication data in first memory block, and reads the communication data of preserving in the 3rd memory block.
In addition, the interrupt control position is set in described DPRAM, described second processor triggers the interruption of described first processor in the mode that writes the numerical value that identifies interrupt type in this interrupt control position; Have no progeny in receiving, described first processor is judged the type of the interruption that receives according to the numerical value in this interrupt control position, and interrupts clearly; Described interrupt control bit length is greater than 1 bit.
In addition, the subsystem of described first processor operation comprises first clock counter, and the subsystem of second processor operation comprises the second clock counter, second processor trigger first interrupt after, trigger second and first clock counter added 1 before interrupting; First processor is as first response of interrupting is added 1 with the second clock counter.
In addition, described communication data comprises: data length is used for identifying the length of the data that respective storage areas preserves; Data type is used for the type of identification data; And data content.
In addition, described second processor writes the communication data of expression system time in the 4th memory block, and described first processor is according to this communication data Adjustment System time.
In addition, triggering first interrupts the time interval between triggering second interruption and triggers second interrupting triggering carrying out Interrupt Process and DPRAM is carried out the required time of read-write operation interval greater than second processor and first processor of first interruption.
In addition, the time interval between the triggering constantly interrupted of twice first of being adjacent constantly of described second triggering of interrupting equates.
The present invention is by being initiated the read-write operation to the specific region of DPRAM by the mode of 2 interruptions of one in two processors triggering, not only realized the real-time communication of two processors, and isolated the otherness that operates in two operating systems on the processor fully, greatly shortened the cycle of the integration and the transplanting of different system.
Description of drawings
Fig. 1 is the structural representation by the two-processor system of DPRAM communication;
Fig. 2 is the synoptic diagram of the means of communication between dual processor of the present invention;
Fig. 3 adopts the ARM of the means of communication of the present invention and the timing diagram of DSP communication.
Embodiment
Basic ideas of the present invention are, in the system that comprises processor A and processor B, processor B triggers the interruption of 2 second processor A at interval with regular time, after down trigger, processor A and processor B are carried out read or write to the specific region of DPRAM simultaneously, to be implemented in the bi-directional data between the processor A and processor B and the communication of message in this time interval.
Below in conjunction with drawings and Examples the present invention is described in detail.
Fig. 1 is the structural representation by the two-processor system of DPRAM communication, and as shown in Figure 1, this system comprises processor A, processor B and DPRAM.Wherein, all link to each other with data bus between processor A and processor B and the DPRAM with the address.In addition, also comprise the interrupt control line between processor A and the DPRAM.
Wherein, processor A normally has the flush bonding processor of better control function, as ARM or PPC, is responsible for the task scheduling and the management of total system; The A of operation system on the processor A.
Processor B normally has the DSP (Digital Signal Processing, digital signal processor) of strong calculation function, is responsible for complicated data operation and processing; The B of operation system on the processor B.
DPRAM has 2 independently RAM of access port (random access memory), allows processor A by different ports it to be carried out the data write operation respectively with processor B, is used to store interactive messages or data between two processors.
The interrupt control line is used to trigger the interruption of processor A.The realization principle of interrupting is relevant with the design of hardware, can adopt the particular register write data among the DPRAM is produced interruption the clear mode of interrupting of read data.The interrupt control position that present embodiment adopts processor B to write among the DPRAM produces interruption, and processor A is read the clear working method of interrupting in interrupt control position among the DPRAM.
As a system that comprises the multiprocessor collaborative work, particularly comprise ASIC (Application SpecialIntegrated Circuit, the special IC) chip of multiprocessor, need to guarantee in a system unique clock is arranged.In the present embodiment, with processor B as the unique clock source in the system, by with regular time interval T constantly trigger the interruption of processor A, can be so that two processors keep synchronously.
In order to realize processor A and the processor B exclusive reference to DPRAM, processor B need trigger the interruption of 2 second processor A to initiate communication at time interval T.That is to say that system time is divided into the unit that length is T, and we are referred to as frame; One frame can comprise the clock period of a plurality of processors, the moment that each frame begins, be called full frame constantly, and constantly, be called field constantly in the middle of each frame.The interruption that processor B is initiated constantly at full frame is called full frame and interrupts; The interruption that processor B is initiated constantly at field is called field and interrupts.
Fig. 2 is the synoptic diagram of the means of communication between dual processor of the present invention.As shown in Figure 2, DPRAM is divided into upstream message, upstream data, downstream message, 5 zones of downlink data and interrupt control position.Wherein, message and the data that processor A sends to processor B are preserved in upstream message and upstream data zone; Message and the data that processor B sends to processor A are preserved in downstream message and downlink data zone; The interrupt control position is used for processor B and writes interrupting information to distinguish the type of interrupting, and triggers simultaneously and interrupts.
Communication between processor A and the processor B comprises full frame communication and field communication two parts:
Full frame communication: when the interim constantly processor B of full frame and processor A carry out following operation:
201: processor B writes the full frame interrupting information to the interrupt control position, triggers hardware interrupts;
Wherein the full frame interrupting information can be the integer greater than 0, is that full frame interrupts in order to the type that identifies this interruption.
202: processor B reads upstream data from DPRAM;
203: processor B writes downstream message to DPRAM;
204: simultaneously, processor A response hardware interrupts reads the interrupt control position, and identifying is that full frame interrupts; And writing 0 to the interrupt control position, the clear interruption is so that can respond interrupt request next time;
In addition, according to the requirement of system design, clear mode of interrupting also can be to remove automatically after processor A reads the interrupt control position.
205: processor A writes upstream message to DPRAM;
206: processor A reads downlink data from DPRAM.
Field communication: when the interim constantly processor B of field and processor A carry out following operation:
207: processor B writes the field interrupting information to the interrupt control position, triggers hardware interrupts;
Wherein the field interrupting information is to be not equal to 0 and the integer of full frame interrupting information, is that field interrupts in order to the type that identifies this interruption.
208: processor B reads upstream message from DPRAM;
209: processor B writes downlink data to DPRAM;
210: simultaneously, processor A response hardware interrupts reads the interrupt control position, and identifying is that field interrupts; And writing 0 to the interrupt control position, the clear interruption is so that can respond interrupt request next time;
211: processor A writes upstream data to DPRAM;
212: processor A reads downstream message from DPRAM.
Processor B can know that the full frame moment and field arriving constantly are to trigger corresponding interruption by periodic interruptions (clock interruption).In the full frame moment and the field moment, processor A and processor B repeat above-mentioned steps respectively, can realize two real-time communications between the processor.
To be that the invention will be further described for example with the WCDMA physical layer software test platform that comprises ARM and two processors of DSP below.
This test platform is made up of background module subsystem and foreground module subsystem, runs on respectively on two processors of ARM and DSP, and the operating system of the last operation of ARM is VxWorks, the last operation of DSP be Nucleus.Because two mechanism differences that operating system realizes, system function is also different, can not directly be undertaken alternately by message, therefore adopts DPRAM to realize the mutual of message and data as intermediary in this system.
In this test platform, adopted the DPRAM of a 4K byte-sized, comprise ULMSG, DLMSG, ULDATA, DLDATA, five zones of INTReg, the corresponding upstream message of difference, downstream message, upstream data, downlink data and interrupt control position, wherein ULMSG, DLMSG, ULDATA, DLDATA are divided into length and data/information two parts, data/message part also can comprise data/information type and data/information content, length is 1 byte partly, is used to identify this regional data/message length, and information such as concrete space and data flow see the following form:
In this system, a frame comprises 16 time slots, and in order to realize two real-time communications between processor, DSP needs to interrupt starting communication in 0 time slot triggering full frame interruption and 7 time slots triggering field respectively.Concrete communications protocol as above step 201 as described in 212.
Wherein, the length of interrupt control position is 1 byte, and it is set to 1 and triggered that full frame interrupts and the field interruption at 2 o'clock respectively DSP; ARM reads behind the interrupt control position its zero clearing.
In this system, for two system times on the processor are consistent, on two subsystems, be respectively arranged with clock counter usually, when full frame interim constantly, clock counter on the DSP adds 1, simultaneously ARM receive full frame when interrupting the clock counter on also with it add 1.
In addition, DSP also can submit to ARM with the form of message with clock information at field constantly, and ARM carries out the adjustment of clock counter according to this information.
The sequential relationship that DSP and ARM carry out communication in this system as shown in Figure 3.
As seen from the above description, eight read-write operations of processor A and processor B need be finished between two full frames interrupt, and this needs the dominant frequency (processing speed) of processor A and processor B to satisfy this requirement.In the example of above-mentioned WCDMA physical layer software test platform, according to the 3GPP agreement, 1 frame is 10ms, and this frame is divided into 16 time slots, so DSP and ARM need to finish at most in 8 time slots and once read and a write operation.
On the basis of the foregoing description, the present invention also has other mapping mode, and for example, the interruption that triggers processor A can realize by alternate manner.
General processor all provides GPIO (general input and output), is used for the User Defined purposes.The GPIO# 0 that we can utilize processor B is as the purposes of the interruption that triggers processor A, and connects an interrupt line from the GPIO# 0 of processor B to processor A.We just can send pulse (level) by the corresponding value of the control register of writing GPIO# 0 like this, and then trigger the processor A interruption.Processor A just can interrupt clearly by the mode of reading (or writing 0) after detecting interrupt request.Can realize the interrupt control between processor in this way equally.
Claims (7)
1, the means of communication between a kind of dual processor are applied to comprise in the system of first processor, second processor and DPRAM, and wherein, described first processor, second processor link to each other with the different port of DPRAM respectively; Second processor triggers the interruption of first processor; It is characterized in that, in DPRAM, mark off 4 nonoverlapping storage areas: first memory block, second memory block, the 3rd memory block and the 4th memory block; Second processor periodically alternately triggers the interruption of first processor: first interrupts and second interruption;
Trigger first interrupt after, trigger second interrupt before, second processor reads the communication data of preserving in first memory block, and writes communication data in the 3rd memory block;
As the response to first interruption, first processor writes communication data in second memory block, and reads the communication data of preserving in the 4th memory block;
Trigger second interrupt after, trigger first interrupt before, second processor reads the communication data of preserving in second memory block, and writes communication data in the 4th memory block;
As the response to second interruption, first processor writes communication data in first memory block, and reads the communication data of preserving in the 3rd memory block.
2, the means of communication between dual processor as claimed in claim 1, it is characterized in that, the interrupt control position is set in described DPRAM, and described second processor triggers the interruption of described first processor in the mode that writes the numerical value that identifies interrupt type in this interrupt control position; Have no progeny in receiving, described first processor is judged the type of the interruption that receives according to the numerical value in this interrupt control position, and interrupts clearly; Described interrupt control bit length is greater than 1 bit.
3, the means of communication between dual processor as claimed in claim 1, it is characterized in that, the subsystem of described first processor operation comprises first clock counter, the subsystem of second processor operation comprises the second clock counter, second processor trigger first interrupt after, trigger second and first clock counter added 1 before interrupting; First processor is as first response of interrupting is added 1 with the second clock counter.
4, the means of communication between dual processor as claimed in claim 1 is characterized in that, described communication data comprises: data length is used for identifying the length of the data that respective storage areas preserves; Data type is used for the type of identification data; And data content.
5, the means of communication between dual processor as claimed in claim 1 is characterized in that, described second processor writes the communication data of expression system time in the 4th memory block, and described first processor is according to this communication data Adjustment System time.
6, the means of communication between dual processor as claimed in claim 1, it is characterized in that, trigger first and interrupt the time interval between triggering second interruption and trigger second interrupting triggering the carrying out Interrupt Process and DPRAM is carried out the required time of read-write operation of first interruption interval greater than second processor and first processor.
7, the means of communication between dual processor as claimed in claim 1 is characterized in that, the time interval between the triggering constantly of twice first interruptions that described second triggering of interrupting is adjacent constantly equates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100639424A CN100511207C (en) | 2007-02-14 | 2007-02-14 | Communication method between two processors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100639424A CN100511207C (en) | 2007-02-14 | 2007-02-14 | Communication method between two processors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101013414A CN101013414A (en) | 2007-08-08 |
| CN100511207C true CN100511207C (en) | 2009-07-08 |
Family
ID=38700937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100639424A Active CN100511207C (en) | 2007-02-14 | 2007-02-14 | Communication method between two processors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100511207C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860894A (en) * | 2010-03-04 | 2010-10-13 | 宇龙计算机通信科技(深圳)有限公司 | System, method and mobile terminal for communication between mobile terminal processors |
| CN101894082B (en) * | 2010-07-21 | 2014-09-10 | 中兴通讯股份有限公司 | Storage device and smartphone system |
| JP5935235B2 (en) * | 2011-02-18 | 2016-06-15 | ソニー株式会社 | COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD |
| CN103853692B (en) * | 2014-03-12 | 2017-03-15 | 四川九洲空管科技有限责任公司 | A kind of multiprocessor data means of communication based on interruption judgment mechanism |
| CN106227681B (en) * | 2016-06-15 | 2019-08-23 | 北京和信瑞通电力技术股份有限公司 | A kind of dual port RAM access method of novel anti-collision |
| CN107577562B (en) * | 2017-09-19 | 2021-02-09 | 南京南瑞继保电气有限公司 | Data interaction method and device and computer readable storage medium |
| CN111742306A (en) * | 2018-12-14 | 2020-10-02 | 华为技术有限公司 | Multiprocessor system and communication method between processors |
| CN110532217A (en) * | 2019-08-02 | 2019-12-03 | 广州粒子微电子有限公司 | A kind of double processor communication method and its communication device |
-
2007
- 2007-02-14 CN CNB2007100639424A patent/CN100511207C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101013414A (en) | 2007-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100511207C (en) | Communication method between two processors | |
| US11294844B2 (en) | EtherCAT master-slave station integrated bridge controller and control method thereof | |
| CN109857685B (en) | MPU and FPGA extended multi-serial port implementation method | |
| JP4742116B2 (en) | Out-of-order DRAM sequencer | |
| CN108228492B (en) | Multi-channel DDR interleaving control method and device | |
| EP2767908A1 (en) | Method and system for improving serial port memory communication latency and reliability | |
| CN103077132B (en) | A kind of cache handles method and protocol processor high-speed cache control module | |
| WO2012143953A4 (en) | Optimized multi-root input output virtualization aware switch | |
| CN103593306A (en) | Design method for Cache control unit of protocol processor | |
| US8880745B2 (en) | Efficient scheduling of transactions from multiple masters | |
| CN103714026B (en) | A kind of memory access method supporting former address data exchange and device | |
| JP4903801B2 (en) | Subscriber interface connecting FlexRay communication module and FlexRay subscriber device, and method of transmitting message via subscriber interface connecting FlexRay communication module and FlexRay subscriber device | |
| CN101866328A (en) | Automatically accessed serial bus read/write control method | |
| US4691280A (en) | High performance multi-processor system | |
| CN1619524A (en) | Communication device and method having a shared local memory | |
| CN102855214B (en) | Realize the method for data consistency and a kind of multiple nucleus system | |
| CN102236623A (en) | Signal control device and signal control method | |
| CN101692346A (en) | Memory data sampling device and sampling controller | |
| CN100592272C (en) | Method for achieving multiprocessor share peripheral circuit and its circuit | |
| CN103810139A (en) | Data exchange method and device for multiple processors | |
| CN100470524C (en) | Small-capacity FIFO storage device data-moving trigger and method | |
| CN105530153A (en) | Slave device communication method in network, communication network, master device and slave device | |
| US8886844B2 (en) | Efficient scheduling of read and write transactions in dynamic memory controllers | |
| CN102591817B (en) | Multi-bus bridge controller and implementing method thereof | |
| CN100432968C (en) | Direct access device of storage and data transmission method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20151104 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Patentee after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |
|
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20070808 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Communication method between two processors Granted publication date: 20090708 License type: Common License Record date: 20190619 |
|
| EE01 | Entry into force of recordation of patent licensing contract |