CN110532217A - A kind of double processor communication method and its communication device - Google Patents
A kind of double processor communication method and its communication device Download PDFInfo
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- CN110532217A CN110532217A CN201910711700.4A CN201910711700A CN110532217A CN 110532217 A CN110532217 A CN 110532217A CN 201910711700 A CN201910711700 A CN 201910711700A CN 110532217 A CN110532217 A CN 110532217A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
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Abstract
The invention discloses a kind of double processor communication method and its communication devices, the dual processor is respectively first processor and second processor, using customized target data structure, in the memory headroom that target data deposit double-port RAM DPRAM is dynamically distributed；Mailbox Mailbox is written in customized target data structure by first processor, and first processor is in communication with each other with second processor by mailbox Mailbox, and second processor is made to read out target data from the memory headroom of corresponding double-port RAM DPRAM.The present invention using existing free memory space in double processor communication device, used can dynamic release, will not additional committed memory space, do not need individually to open up one piece of memory headroom, to save memory headroom yet；Using simple and quick mailbox Mailbox communication mechanism is designed, the high-speed traffic of mass data can be realized between dual processor, solves the problems such as memory usage is low, data transmission bauds is slow in existing multiprocessor communication system.
Description
Technical field
The present invention relates to semiconductor communication field, specifically a kind of double processor communication method and its communication device.
Background technique
With being constantly progressive for semiconductor fabrication process, in order to meet communication, multimedia and the contour end application of digital processing,
System on chip not only integrates a processor, but multiple processors are integrated into a system, or even is also needed
Processor outside bonding pad works together.In double processor communication, typical application is by CPU and DSP (Digital
Singnal Processor) it is integrated into a system, wherein CPU is responsible for the complex control of system, and DSP is responsible for answering for system
Two class processors are organically combined by system on chip, are given full play to respective advantage, complete system by miscellaneous calculating
Various functions.But there is inter-processor communication in on-chip multi-processor system, need between the process run on each processor
Shared resource, transmission data, and guarantee Process Synchronization.For the system being made of CPU and DSP, needed between CPU and DSP
It wants real-time exchange data just and can guarantee collaboration concurrent working.Between CPU and DSP information exchange can be carried out by mailbox Mailbox.
Mailbox Mailbox be in the mailbox processing and control element (PCE) added between CPU and DSP in system, for special disposal CPU with
Information between DSP is sent, and is received and is handled.Fig. 1 show typical dual processor by what mailbox Mailbox was communicated
System.
A kind of many places are proposed in patent CN108073545A (entitled " a kind of multiprocessor communication device and method ")
Manage device communication device and method.It is characterized in that, sender's processor, for when the demand for thering are data to be written, by number of targets
Interrupt signal is sent according to write-in shared drive, and to interrupt control unit；Recipient's processor, for being default when pending task
When task, the state of interrupt control unit is configured, and when receiving the interrupt signal of interrupt control unit transmission, from shared drive
Middle reading target data；Interrupt control unit generates mask bit in shielding shape for the configuration according to recipient's processor
State, or mask bit is removed to be in non-shielding state, and in non-shielding state, interrupt signal is sent to recipient's processing
Device.Its advantage is that improving the real-time that preset task executes, while the efficiency of system processing task is also improved, reduces system
Load；The disadvantage is that being first written in shared drive due to will send data, this just needs the computer system in multiprocessor
In open up one piece can by different processor access large capacity memory, when send data volume it is smaller when, will result in
The wasting of resources increases hardware spending.
Patent CN104462008A (entitled " multiprocessor communication system and its communication means of shared physical memory ")
In propose and a kind of the communication system communicated between multiprocessor and its communication means realized by shared physical memory.Wherein,
Multiple processors send and receive mutually data；Physical memory is divided into multiple physical memory blocks, so that each processing utensil
There is dedicated physical memory block；Transmitting data to the transmission processor for sending data in the multiple processor is the multiple
The dedicated physical memory of the reception processor that will receive data in processor, also, the reception processor is from the dedicated of it
Physical memory block reads the data.Its advantage is that in the multiprocessor communication system of shared physical memory, between multiprocessor
When carrying out data communication, peripheral circuit is not needed, access speed is fast, strong real-time.The disadvantage is that each processor have it is dedicated
Physical memory block, when between processor carry out mass data communication when, need at this time large capacity physical memory block store data,
Committed memory space；When not having data interaction between processor, memory is reserved necessarily to result in waste of resources, and increases hardware
Expense.
In conclusion in the prior art, in multiprocessor communication system, needing to open up one piece of great Rong in systems in advance
Multiprocessor shared memory space is measured, processor is sent by target data and the shared memory space is written, then receive processor
Target data is read from shared drive.It is transmitted in the existing system communicated between multiprocessor by shared drive
When data, physical memory utilization rate is low, and data transmission bauds is slow.
Summary of the invention
The purpose of the present invention is to provide a kind of double processor communication method using dynamic memory space and its communication dresses
It sets, to solve the problems such as memory usage is low, data transmission bauds is slow in existing multiprocessor communication system.
To achieve the above object, the invention provides the following technical scheme:
A kind of double processor communication method, the dual processor is respectively first processor and second processor, using certainly
Target data structure is defined, in the memory headroom that target data deposit double-port RAM DPRAM is dynamically distributed；First
Mailbox Mailbox is written in customized target data structure by processor, and first processor and second processor pass through mailbox
Mailbox is in communication with each other, and second processor is made to read out target from the memory headroom of corresponding double-port RAM DPRAM
Data.
As a further solution of the present invention: the customized target data structure includes target data address information sum number
According to length information.
As a further solution of the present invention: the customized target data structure also includes command recognition id information.
As a further solution of the present invention: the customized target data structure default bit wide is 32bits.
As a further solution of the present invention: the method specifically comprises the following steps: that (1) described dual processor is respectively
First processor and second processor, first processor are to send processor, and second processor is to receive processor；(2) it sends
In the memory headroom that processor dynamically distributes target data deposit double-port RAM DPRAM；(3) sending processor will
Comprising in the data packet of target data address and length information write-in mailbox Mailbox；(4) mailbox Mailbox, which is sent, interrupts letter
Number；(5) after receiving processor reception interrupt signal, the read data packet from mailbox Mailbox parses the storage of target data
Address and data length information；(6) it receives processor and reads target from corresponding double-port RAM DPRAM memory headroom
Data realize the communication between dual processor.
As a further solution of the present invention: the dual processor is respectively central processor CPU and Digital Signal Processing
Device DSP.
As a further solution of the present invention: arbitrarily define the central processor CPU, digital signal processor DSP it
One is sends processor, another processor is then to receive processor, sends processor and dynamically distributes target data deposit
Double-port RAM DPRAM (double-port RAM) memory headroom in；Then will comprising target data address and
In the data packet write-in mailbox Mailbox of length information, mailbox Mailbox sends interrupt signal later；Processor is received to receive
After interrupt signal, the read data packet from mailbox Mailbox parses the storage address and data length information of target data,
Then target data is read from corresponding double-port RAM DPRAM memory headroom, realizes the communication between dual processor.
As a further solution of the present invention: defining the central processor CPU to send processor, Digital Signal Processing
Device DSP is the communication flow between central processor CPU and digital signal processor DSP are as follows: (1) centre when receiving processor
Reason device CPU data to be sent are stored in the double-port RAM DPRAM memory headroom of dynamic allocation, then will be counted
It is written in customized data structure according to address information and length information, and number order identification id information is added, form data
Packet；(2) data packet is written in the FIFO1 in mailbox Mailbox central processor CPU, and the FIFO1 is only to centre
It is writeable to manage device CPU, it is only readable to digital signal processor DSP；(3) after writing end of data in FIFO1, pass through interrupt register
INT_STA_1 sends an interrupt signal, and until data are run through in FIFO1, which can just stop；(4) number letter
Number processor DSP receives the interrupt signal that interrupt register INT_STA_1 is sended over；(5) digital signal processor DSP is read
Then data in FIFO1 parse data address information and length information from the data packet of reading；(6) Digital Signal Processing
The data information that device DSP is obtained according to parsing data packet, corresponding position is read from double-port RAM DPRAM memory headroom
The data that central processor CPU sends over are taken, and discharge double-port RAM DPRAM memory headroom, so far, centre
Reason device CPU terminates to digital signal processor DSP transmission data procedures.
As a further solution of the present invention: defining the digital signal processor DSP to send processor, central processing
Device CPU is the communication flow between central processor CPU and digital signal processor DSP are as follows: (1) number letter when receiving processor
Number processor DSP data information to be sent is stored in the double-port RAM DPRAM memory headroom of dynamic allocation,
Then data address information and data length information are written in customized data structure, and number order identification id letter is added
Breath forms data packet；(2) mailbox will be written comprising the data packet of address information and length information in digital signal processor DSP
In FIFO2 in Mailbox, the FIFO2 is only writeable to DSP, only readable to CPU；(3) after writing end of data in FIFO2,
An interrupt signal, until data are run through in FIFO2, the interrupt signal will be sent by interrupt register INT_STA_2
Can just it stop；(4) central processor CPU receives the interrupt signal that interrupt register INT_STA_2 is sended over；(5) centre
It manages device CPU and reads data in FIFO2, then parse address information and length information from the data packet of reading；(6) centre
The data information that reason device CPU is obtained according to parsing data packet, the corresponding position from double-port RAM DPRAM memory headroom
The data that DSP is sended over are read, and discharge double-port RAM DPRAM memory headroom, so far, digital signal processor
DSP terminates to central processor CPU transmission data procedures.
As further scheme of the invention: a kind of dual processor communication device, including central processor CPU, number
Signal processor DSP, mailbox Mailbox and double-port RAM DPRAM, arbitrarily define the central processor CPU, number
One of word signal processor DSP is to send processor, another processor is then to receive processor, sends processor for target
Data are stored in the memory headroom that double-port RAM DPRAM is dynamically distributed；It then will include target data address and length
It spends in the data packet write-in mailbox Mailbox of information, mailbox Mailbox sends interrupt signal later；It receives in processor reception
After break signal, the read data packet from mailbox Mailbox parses the storage address and data length information of target data, so
Target data is read from corresponding double-port RAM DPRAM memory headroom afterwards, realizes the communication between dual processor.
Compared with prior art, the beneficial effects of the present invention are: the present invention use it is existing in double processor communication device
Free memory space, used can dynamic release, will not additional committed memory space, do not need individually to open up one piece of memory yet
Space, to save memory headroom；In addition, using simple and quick mailbox Mailbox communication mechanism is designed, it can be in dual processor
Between realize the high-speed traffic of mass data, solve that memory usage in existing multiprocessor communication system is low, data transmission
The problems such as speed is slow.
Detailed description of the invention
Fig. 1 is the system that typical dual processor is communicated by mailbox Mailbox in the prior art；
Fig. 2 is the work flow diagram of the method for the present invention；
Fig. 3 is the schematic block circuit diagram of double processor communication device of the present invention；
Fig. 4 is customized target data structure explanatory diagram in the method for the present invention；
Fig. 5 be in the method for the present invention central processor CPU to digital signal processor DSP transmission data flow diagram；
Fig. 6 be in the method for the present invention digital signal processor DSP to central processor CPU transmission data flow diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
A kind of double processor communication method of the present invention, the dual processor are respectively first processor and second processor,
Using customized target data structure, the memory headroom that target data deposit double-port RAM DPRAM is dynamically distributed
In；Mailbox Mailbox is written in customized target data structure by first processor, and first processor and second processor pass through postal
Case Mailbox is in communication with each other, and second processor is made to read out mesh from the memory headroom of corresponding double-port RAM DPRAM
Mark data.
Referring to Fig. 2, the method specifically comprises the following steps: (1) institute as the method for the present invention further embodiment
Stating dual processor is respectively first processor and second processor, and first processor is to send processor, and second processor is to connect
Receive processor；(2) memory headroom that processor dynamically distributes target data deposit double-port RAM DPRAM is sent
In；(3) sending processor will be comprising in the data packet of target data address and length information write-in mailbox Mailbox；(4) mailbox
Mailbox sends interrupt signal；(5) after receiving processor reception interrupt signal, the read data packet from mailbox Mailbox, solution
The storage address and data length information of target data is precipitated；(6) processor is received from corresponding double-port RAM DPRAM
Target data is read in memory headroom, realizes the communication between dual processor.
It include the data packet of target data address and length information in the present invention, use case is as shown in Figure 4 makes by oneself
Adopted target data structure.The customized data structure default bit wide is 32bits, and specific bit wide is described as follows:
Command recognition (ID): default bit wide 7bits, including send and receive known to order and communicating pair agreement
Some instructions.
Data address (Addr): default bit wide 9bits, the address double-port RAM DPRAM used in this example
Space is 512Kbyte, and defaulting maximum committed memory space due to the data of both sides' interaction is 1Kbyte, can be changed according to demand
Store data volume size, therefore the initial address for storing data uses the integral multiple of 1K, to facilitate record data initial address message (IAM).
Therefore the address space using the 1Kbyte dynamically distributed in double-port RAM DPRAM is for storing data, the data
Address is the first address for recording stored target data.
Data length (Size): definition stored target data maximum length is 1Kbyte, and each size is represented
32bits bit wide data, therefore data length bit wide is defined as 8bits.It, can be with if sending target data length is greater than 1Kbyte
It is divided into multiple 1Kbyte data lengths to send.
As shown in Fig. 2, mailbox Mailbox includes dual processor respectively for storage data in double processor communication device
The FIFO:FIFO1 and FIFO2 of structure, and corresponding interrupt status register INT_STA_1 and INT_STA_2.Double processing are equal
It the use of depth is 2, bit wide is the FIFO of 32bits, can be continuously written into two data packets, carries out ping-pong operation.FIFO is mainly used for
Storage includes the customized data packet of target data information, is filled with data packet when being written in data packet or FIFO in FIFO,
Or in FIFO when datagram overflow, all interrupt signal can be sent by interrupt register.It receives processor and receives interruption letter
After number, the read data packet from transmission processor FIFO, and packet information is parsed, obtain target data address and data length
Etc. information, data are then read from memory headroom, and discharge the memory headroom.
Double processor communication device is as shown in figure 3, arbitrarily define the central processing unit in further the method for the present invention
One of CPU, digital signal processor DSP are to send processor, another processor is then to receive processor, send processor
In the memory headroom that target data deposit double-port RAM DPRAM is dynamically distributed；It then will comprising target data
The data packet of location and length information is written in mailbox Mailbox, and mailbox Mailbox sends interrupt signal later；Receive processor
After receiving interrupt signal, the read data packet from mailbox Mailbox parses the storage address and data length letter of target data
Then breath reads target data from corresponding double-port RAM DPRAM memory headroom, realize logical between dual processor
Letter.
In double processor communication device, between central processor CPU and digital signal processor DSP by dual-port with
Machine accesses memory double-port RAM DPRAM and realizes data transmission, central processor CPU and digital signal processor
Mutual data communication can be carried out between DSP.
Preferably, referring to Fig. 5, if defining the central processor CPU to send processor, digital signal processor
DSP is to receive processor, then the communication flow between central processor CPU and digital signal processor DSP are as follows: (1) central processing
Device CPU data to be sent are stored in the double-port RAM DPRAM memory headroom of dynamic allocation, then by data
Address information and length information are written in customized data structure, and number order identification id information is added, and form data packet；
(2) data packet is written in the FIFO1 in mailbox Mailbox central processor CPU, and the FIFO1 is only to central processing
Device CPU is writeable, only readable to digital signal processor DSP；(3) after writing end of data in FIFO1, pass through interrupt register INT_
STA_1 sends an interrupt signal, and until data are run through in FIFO1, which can just stop；(4) at digital signal
Reason device DSP receives the interrupt signal that interrupt register INT_STA_1 is sended over；(5) digital signal processor DSP is read
Then data in FIFO1 parse data address information and length information from the data packet of reading；(6) Digital Signal Processing
The data information that device DSP is obtained according to parsing data packet, corresponding position is read from double-port RAM DPRAM memory headroom
The data that central processor CPU sends over are taken, and discharge double-port RAM DPRAM memory headroom, so far, centre
Reason device CPU terminates to digital signal processor DSP transmission data procedures.
Further, referring to Fig. 6, if defining the digital signal processor DSP to send processor, central processing unit
CPU is to receive processor, then the communication flow between central processor CPU and digital signal processor DSP are as follows: (1) digital signal
Processor DSP data information to be sent is stored in the double-port RAM DPRAM memory headroom of dynamic allocation, so
Data address information and data length information are written in customized data structure afterwards, and number order identification id letter is added
Breath forms data packet；(2) mailbox will be written comprising the data packet of address information and length information in digital signal processor DSP
In FIFO2 in Mailbox, the FIFO2 is only writeable to DSP, only readable to CPU；(3) after writing end of data in FIFO2,
An interrupt signal, until data are run through in FIFO2, the interrupt signal will be sent by interrupt register INT_STA_2
Can just it stop；(4) central processor CPU receives the interrupt signal that interrupt register INT_STA_2 is sended over；(5) centre
It manages device CPU and reads data in FIFO2, then parse address information and length information from the data packet of reading；(6) centre
The data information that reason device CPU is obtained according to parsing data packet, the corresponding position from double-port RAM DPRAM memory headroom
The data that DSP is sended over are read, and discharge double-port RAM DPRAM memory headroom, so far, digital signal processor
DSP terminates to central processor CPU transmission data procedures.
In conclusion the present invention using existing free memory space in double processor communication device, has used i.e. movably
State release, will not additional committed memory space, do not need individually to open up one piece of memory headroom, to save memory headroom yet；Separately
Outside, using simple and quick mailbox Mailbox communication mechanism is designed, the quick logical of mass data can be realized between dual processor
Letter, solves the problems such as memory usage is low, data transmission bauds is slow in existing multiprocessor communication system.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped
Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should
It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
The other embodiments being understood that.
Claims (10)
1. a kind of double processor communication method, which is characterized in that the described method includes:
Dual processor is provided, the dual processor is respectively first processor and second processor；
Using customized target data structure, the memory that target data deposit double-port RAM DPRAM is dynamically distributed
In space；
Mailbox Mailbox is written into customized target data structure using first processor, wherein at first processor and second
Reason device is in communication with each other by mailbox Mailbox, so that memory of the second processor from corresponding double-port RAM DPRAM
Target data is read out in space.
2. double processor communication method according to claim 1, which is characterized in that the customized target data structure packet
Information containing target data address and data length information.
3. double processor communication method according to claim 2, which is characterized in that the customized target data structure is also
Include command recognition id information.
4. double processor communication method according to claim 3, which is characterized in that the customized target data structure is silent
Recognizing bit wide is 32bits.
5. double processor communication method according to claim 1, which is characterized in that the method specifically includes following step
It is rapid:
(1) dual processor is respectively first processor and second processor, and first processor is to send processor, at second
Managing device is to receive processor；
(2) it sends in the memory headroom that processor dynamically distributes target data deposit double-port RAM DPRAM；
(3) sending processor will be comprising in the data packet of target data address and length information write-in mailbox Mailbox；
(4) mailbox Mailbox sends interrupt signal；
(5) after receiving processor reception interrupt signal, the read data packet from mailbox Mailbox parses depositing for target data
Put address and data length information；And
(6) it receives processor and reads target data from corresponding double-port RAM DPRAM memory headroom, realize double processing
Communication between device.
6. double processor communication method according to claim 5, which is characterized in that the dual processor is respectively centre
Manage device CPU and digital signal processor DSP.
7. double processor communication method according to claim 6, which is characterized in that arbitrarily define the central processing unit
One of CPU, digital signal processor DSP are to send processor, another processor is then to receive processor, send processor
In the memory headroom that target data deposit double-port RAM DPRAM is dynamically distributed；It then will comprising target data
The data packet of location and length information is written in mailbox Mailbox, and mailbox Mailbox sends interrupt signal later；Receive processor
After receiving interrupt signal, the read data packet from mailbox Mailbox parses the storage address and data length letter of target data
Then breath reads target data from corresponding double-port RAM DPRAM memory headroom, realize logical between dual processor
Letter.
8. double processor communication method according to claim 7, which is characterized in that defining the central processor CPU is
Processor is sent, digital signal processor DSP is when receiving processor, between central processor CPU and digital signal processor DSP
Communication flow are as follows:
(1) central processor CPU data to be sent store the double-port RAM DPRAM memory sky into dynamic allocation
Between in, then data address information and length information are written in customized data structure, and number order identification id is added
Information forms data packet；
(2) data packet is written in the FIFO1 in mailbox Mailbox central processor CPU, and the FIFO1 is only to center
Processor CPU is writeable, only readable to digital signal processor DSP；
(3) after writing end of data in FIFO1, an interrupt signal is sent by interrupt register INT_STA_1, until FIFO1
Middle data are run through, which can just stop；
(4) digital signal processor DSP receives the interrupt signal that interrupt register INT_STA_1 is sended over；
(5) digital signal processor DSP reads data in FIFO1, and data address letter is then parsed from the data packet of reading
Breath and length information；And
(6) data information that digital signal processor DSP is obtained according to parsing data packet, from double-port RAM DPRAM
The data that central processor CPU sends over are read in corresponding position in memory headroom, and discharge double-port RAM DPRAM
Memory headroom, so far, central processor CPU terminate to digital signal processor DSP transmission data procedures.
9. double processor communication method according to claim 7, which is characterized in that define the digital signal processor
DSP is to send processor, and central processor CPU is central processor CPU and digital signal processor DSP when receiving processor
Between communication flow are as follows:
(1) digital signal processor DSP data information to be sent is stored in the double-port RAM of dynamic allocation
In DPRAM memory headroom, then data address information and data length information are written in customized data structure, and is added
Number order identifies id information, forms data packet；
(2) digital signal processor DSP will be comprising in the data packet of address information and length information write-in mailbox Mailbox
In FIFO2, the FIFO2 is only writeable to DSP, only readable to CPU；
(3) after writing end of data in FIFO2, an interrupt signal will be sent by interrupt register INT_STA_2, until
Data are run through in FIFO2, which can just stop；
(4) central processor CPU receives the interrupt signal that interrupt register INT_STA_2 is sended over；
(5) central processor CPU reads data in FIFO2, then parses address information and length from the data packet of reading
Information；And
(6) data information that central processor CPU is obtained according to parsing data packet, from double-port RAM DPRAM memory
The data that DSP is sended over are read in corresponding position in space, and discharge double-port RAM DPRAM memory headroom, so far,
Digital signal processor DSP terminates to central processor CPU transmission data procedures.
10. a kind of dual processor communication device using such as any the method for claim 1-9, which is characterized in that including in
Central processor CPU, digital signal processor DSP, mailbox Mailbox and double-port RAM DPRAM, arbitrarily described in definition
One of central processor CPU, digital signal processor DSP are to send processor, another processor is then to receive processor,
It sends in the memory headroom that processor dynamically distributes target data deposit double-port RAM DPRAM；Then will include
The data packet of target data address and length information is written in mailbox Mailbox, and mailbox Mailbox sends interrupt signal later；
Receive processor receive interrupt signal after, the read data packet from mailbox Mailbox, parse target data storage address and
Then data length information reads target data from corresponding double-port RAM DPRAM memory headroom, realize double processing
Communication between device.
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| CN112506847A (en) * | 2021-02-04 | 2021-03-16 | 上海励驰半导体有限公司 | Multiprocessor communication method and system |
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