WO2016179968A1

WO2016179968A1 - Queue management method and device, and storage medium

Info

Publication number: WO2016179968A1
Application number: PCT/CN2015/092929
Authority: WO
Inventors: 周谦
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2015-05-13
Filing date: 2015-10-27
Publication date: 2016-11-17
Also published as: CN106302238A

Abstract

Disclosed is a queue management method. The method comprises: determining a current operation request to be an enqueueing operation request of message descriptors, storing, according to the enqueueing operation request and a cache situation of an on-chip random access memory (RAM), the message descriptors to an off-chip double-data rate synchronous dynamic random access memory (DDR) or the on-chip RAM, and updating information about a pointer linked list; and determining a current operation request to be a dequeueing operation request of message descriptors, acquiring location information about a queue header pointer corresponding to the dequeueing operation request in the pointer linked list, reading, according to the location information, the corresponding message descriptors, and updating the information about the pointer linked list, wherein the location information comprises location information about the on-chip RAM and location information about the off-chip DDR. Also disclosed are a queue management device and a storage medium.

Description

Queue management method, device and storage medium

Technical field

The present invention relates to a related art of queue management in the field of communication technologies, and in particular, to a queue management method, apparatus, and storage medium.

Background technique

As data traffic in the network grows larger, traffic bursts occur frequently. At present, an implementation method of queue management adopts a fixed allocation space, that is, each queue allocates a fixed space, and address spaces of different queues cannot be shared. This method is simple to implement, but since the address space of different queues cannot be shared, space waste is easily caused. And when there are a large number of queues, the space allocated by each queue is quite limited, and the anti-burst capability is weak; another implementation method is to use a shared space, to make a linked list for each queue, and to set a packet address space belonging to the same queue. Linked up, this method can improve the cache utilization, but the control is complicated, especially in the case of multi-linked list mode, and at the same time facing the instantaneous large-scale traffic of the network burst, the anti-burst capability is still insufficient.

Therefore, a technical solution for queue management is provided, which can effectively avoid the packet loss under the traffic burst while improving the access efficiency, and has become an urgent problem to be solved.

Summary of the invention

In view of this, the embodiment of the present invention is to provide a queue management method, device, and storage medium, which can effectively avoid packet loss under traffic bursts while improving access efficiency and reducing power consumption.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

An embodiment of the present invention provides a queue management method, where the method includes:

Determining that the current operation request is an enqueue operation request of the message descriptor, according to the enqueue operation Requesting and buffering of on-chip random access memory (RAM), storing the message descriptor to an off-chip double-rate synchronous dynamic random access memory (DDR) or on-chip RAM And update the pointer list information;

Determining that the current operation request is a dequeue operation request of the message descriptor, acquiring location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, and reading the corresponding message description according to the location information And updating the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.

In the above solution, the storing the message descriptor to the off-chip DDR or the on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM includes:

And determining, according to the enqueue operation request, that the current on-chip RAM has reached the upper limit, calculating an off-chip DDR address, and storing the message descriptor to an off-chip DDR according to the obtained off-chip DDR address;

When it is determined that the current on-chip RAM has not reached the upper limit, the queue number in the enqueue operation request is extracted, and the message descriptor is stored in the on-chip RAM according to the queue number.

In the above solution, when it is determined that the current operation request is an enqueue operation request of the message descriptor, the update pointer list information includes:

Extracting a queue number in the enqueue operation request, reading a corresponding queue tail pointer and a idle head pointer according to the queue number, updating the queue tail pointer to an address indicated by the idle head pointer, and then The idle header pointer points to the next address in the pointer list.

In the above solution, when it is determined that the current operation request is a dequeuing operation request of the message descriptor, the updated pointer list information includes:

Extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer and an idle tail pointer according to the queue number, updating the idle tail pointer to an address indicated by the queue head pointer, and then The queue head pointer points to the next address in the pointer list.

In the above solution, the obtaining a queue head pointer corresponding to the dequeuing operation request is in the finger The location information in the pin list, and the corresponding message descriptors are read according to the location information, including:

Extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer according to the queue number, and determining an off-chip DDR address when the position of the queue head pointer in the pointer list is in an off-chip DDR Reading the corresponding message descriptor in the off-chip DDR according to the obtained off-chip DDR address;

When it is determined that the position of the queue head pointer in the pointer list is in the on-chip RAM, the corresponding message descriptor in the on-chip RAM is read according to the queue number.

The embodiment of the invention further provides a queue management device, the device comprising: a first processing module and a second processing module; wherein

The first processing module is configured to determine that the current operation request is an enqueue operation request of the message descriptor, and describe the message according to the enqueue operation request and the buffering condition of the on-chip random access memory RAM. Stores to the off-chip double rate synchronous dynamic random access memory DDR or on-chip RAM and updates the pointer list information;

The second processing module is configured to determine that the current operation request is a dequeue operation request of the message descriptor, and obtain location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, according to the The location information reads the corresponding message descriptor and updates the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.

In the above solution, the first processing module is configured to calculate an off-chip DDR address when the current on-chip RAM cache has reached an upper limit according to the enqueue operation request, and the report is obtained according to the obtained off-chip DDR address. The text descriptor is stored to the off-chip DDR;

In the above solution, the first processing module is configured to extract a queue number in the enqueue operation request, read a corresponding queue tail pointer and a idle head pointer according to the queue number, and update the queue tail pointer to point Describe the address currently indicated by the idle head pointer, and then refer to the idle header The pin points to the next address in the list of pointers.

In the above solution, the second processing module is configured to extract a queue number in the enqueue operation request, read a corresponding queue head pointer and an idle tail pointer according to the queue number, and update the idle tail pointer to point The address currently indicated by the queue head pointer is then directed to the next address in the pointer list.

In the above solution, the second processing module is configured to extract a queue number in the enqueue operation request, read a corresponding queue head pointer according to the queue number, and determine that the queue head pointer is in the pointer list. When the location is in the off-chip DDR, the off-chip DDR address is calculated, and the corresponding message descriptor in the off-chip DDR is read according to the obtained off-chip DDR address;

The embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program configured to execute the foregoing queue management method of the embodiment of the present invention.

The queue management method, device and storage medium provided by the embodiment of the present invention; determining that the current operation request is an enqueue operation request of the message descriptor, according to the enqueue operation request and the on-chip RAM cache situation, The message descriptor is stored in the off-chip DDR or the on-chip RAM, and the pointer list information is updated; the current operation request is determined to be a dequeue operation request of the message descriptor, and the queue head pointer corresponding to the dequeue operation request is obtained. The location information in the pointer list reads the corresponding message descriptor according to the location information, and updates the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information. In this way, the queue is managed by the pointer list and the on-chip plus off-chip method, and the storage location of the message descriptor is determined according to the buffer condition of the on-chip RAM, thereby effectively improving the access efficiency and reducing the power consumption while avoiding the traffic burst. The packet loss situation.

DRAWINGS

1 is a schematic flowchart of a queue management method according to an embodiment of the present invention;

2 is a schematic diagram of initializing a pointer list RAM according to an embodiment of the present invention;

3 is a schematic diagram of data relationships between respective RAMs according to an embodiment of the present invention;

4 is a schematic flowchart of a queue management method according to Embodiment 2 of the present invention;

FIG. 5 is a schematic structural diagram of a queue management apparatus according to an embodiment of the present invention.

detailed description

In the embodiment of the present invention, determining that the current operation request is an enqueue operation request of the message descriptor, and storing the message descriptor to the off-chip according to the enqueue operation request and the buffering condition of the on-chip RAM. DDR or on-chip RAM, and updating pointer list information; determining that the current operation request is a dequeue operation request of the message descriptor, and acquiring location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, Reading the corresponding message descriptor according to the location information, and updating the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.

Embodiment 1

FIG. 1 is a schematic flowchart of a queue management method according to an embodiment of the present invention; as shown in FIG. 1 , a queue management method according to an embodiment of the present invention includes:

Step 101: Determine that the current operation request is an enqueue operation request of the message descriptor, and store the message descriptor to an off-chip DDR or an on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM. And update the pointer list information;

Here, the storing the message descriptor to the off-chip DDR or the on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM includes:

In an embodiment, the determining that the current on-chip RAM has reached a maximum limit includes:

According to the preset buffer size of the on-chip RAM and the number of non-free pointers in the current pointer list recorded by the cache counter in real time, it is determined whether the current on-chip RAM cache has reached the upper limit, if the number of non-free pointers in the current pointer list is less than the preset The buffer size of the on-chip RAM determines that the current on-chip RAM cache has not reached the upper limit; otherwise, it determines that the current on-chip RAM cache has reached the upper limit;

Here, the on-chip RAM is used to buffer message descriptor information, and its size can be set according to actual needs. In an embodiment, the size of the on-chip RAM is 4k, that is, the address of the on-chip RAM is 0. ～4k-1, that is, the depth of the on-chip RAM is 4×1024 addresses.

In an embodiment, the calculating the off-chip DDR address comprises:

Calculating an off-chip DDR address according to the size of the on-chip RAM and the number of non-free pointers in the current pointer list recorded by the cache counter; the off-chip DDR address may be a base address + a link intra-slice position offset; wherein The base address is a base address of the system configuration, and the message descriptor is stored in the off-chip DDR; the positional offset of the linked list is a relative address, and if the base address is 4k, the position of the linked list is offset. Move to 0. If the base address is 4k+1, the positional offset of the linked list is 1.

In an embodiment, the updating the pointer list information includes:

Extracting a queue number in the enqueue operation request, reading a corresponding queue tail pointer in the tail pointer RAM and a free head pointer in the pointer list table RAM according to the queue number, and updating the queue tail pointer to the idle head pointer The currently indicated address, and then directing the free head pointer to the next address in the pointer list;

Here, the tail pointer RAM is used to store a queue tail pointer of all queues, and indicates a queue status of each queue; wherein the queue status includes: empty and non-empty; the tail pointer RAM The size/depth of the tail can be set according to the actual situation. In an embodiment, the depth of the tail pointer RAM is equal to the number of queues. In this embodiment, the depth of the tail pointer RAM is 256 addresses, and the initialization is performed. The highest bit after the tail pointer RAM is 1 or all 1s, and the initialized queue state is empty;

Correspondingly, there is also a head pointer RAM for storing a queue head pointer of all queues, and indicating a queue status of each queue; wherein the queue status includes: null and non-empty; the size/depth of the head pointer RAM may be According to the actual situation, in one embodiment, the depth of the head pointer RAM is equal to the number of queues. In this embodiment, the depth of the head pointer RAM is 256 addresses, after the head pointer RAM is initialized. The highest bit is 1 or all 1s. It can be seen that the initialized queue status is empty.

The pointer linked list RAM is configured to store the pointer linked list, so that the queue pointer linked list and the free pointer linked list share a RAM, thereby eliminating the need for a separate first in first out queue (FIFO, First Input First Output) to store the idle pointer, thereby saving The hardware resource; the pointer list table RAM size can be set according to actual needs. In an embodiment, the on-chip RAM has a size of 4k, and the pointer list includes a pointer to the next address, which is initialized to a The null pointer list, as shown in Figure 2, the ptr RAM is the pointer list RAM, which is initialized. The address of the ptr RAM is from 0 to 8191, and the content stored in the ptr RAM is the next address value, thereby forming a pointer list. a form; the pointer list includes a non-free pointer and a free pointer; wherein the number of the non-free pointers characterizes the total number of addresses occupied by the on-chip RAM and the message descriptor in the off-chip DDR, once for each queue entry The text descriptor, the number of non-free pointers plus one, correspondingly, each time a message descriptor is dequeued, the number of non-free pointers is decremented by one; the on-chip RAM and the pointer chain There is a one-to-one correspondence between a part of the RAM, the message descriptor information in the on-chip RAM, and the corresponding address information in the pointer list table RAM; FIG. 3 is a schematic diagram of data relationships between the RAMs according to the embodiment of the present invention. ;

In Figure 3, head_ptr ram is the head pointer RAM, and tail_ptr ram is the tail pointer RAM. Ptr ram is pointer list RAM, desc ram is on-chip RAM; among them, black in the pointer list RAM is a queue member in a queue, there are 6 queue members, for convenience of explanation, they are marked as 1 to 6 in order. For the virtual tag), the address information of the latter data block is stored in the previous data block, because the label 6 is the last data of the queue, so the data in the pointer list RAM is invalid data; according to the head pointer and the tail pointer It can be seen that the queue number of the queue is 11, the address of the data block corresponding to the label 1 is determined by the value stored by the head pointer RAM address 11, and the data block address corresponding to the label 6 is determined by the value stored in the tail pointer RAM address 11.

Step 102: Determine that the current operation request is a dequeue operation request of the message descriptor, obtain location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, and read corresponding information according to the location information. Message descriptor and update pointer list information;

Here, the location information includes on-chip RAM location information and off-chip DDR location information;

And acquiring the location information of the queue head pointer corresponding to the dequeuing operation request in the pointer list, and reading the corresponding message descriptor according to the location information includes:

Extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer in the head pointer RAM according to the queue number, and determining that the position of the queue head pointer in the pointer list is in an off-chip DDR, The off-chip DDR address reads the corresponding message descriptor in the off-chip DDR according to the obtained off-chip DDR address;

In an embodiment, the updating the pointer list information includes:

Embodiment 2

4 is a schematic flowchart of a queue management method according to Embodiment 2 of the present invention; as shown in FIG. 4, The queue management method of the embodiment of the present invention includes:

Step 401: Receive an operation request and determine whether it is an enqueue operation request or a dequeue operation request of the message descriptor. If it is a enqueue operation request, step 402 is performed; if it is a dequeue operation request, step 404 is performed.

Step 402: Store the message descriptor into an off-chip DDR or an on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM;

The step includes: determining, according to the enqueue operation request, that the current on-chip RAM has reached the upper limit, calculating an off-chip DDR address, and storing the message descriptor to an off-chip DDR according to the obtained off-chip DDR address;

Here, the on-chip RAM is used to buffer the message descriptor information, and the size thereof can be set according to actual needs. In this embodiment, the size of the on-chip RAM is 4k, that is, the address of the on-chip RAM is 0. ～4k-1, that is, the depth of the on-chip RAM is 4×1024 addresses.

Step 403: Update the pointer list information, and perform step 406;

The step includes: extracting a queue number in the enqueue operation request, reading a corresponding queue tail pointer in the tail pointer RAM and a free head pointer in the pointer list table RAM according to the queue number, and updating the queue tail pointer to the location Describe the address currently indicated by the idle head pointer, and then point the free head pointer to the next address in the pointer list;

Here, the tail pointer RAM is used to store a queue tail pointer of all queues, and indicates a queue status of each queue; wherein the queue status includes: empty and non-empty; the size/depth of the tail pointer RAM may be based on The actual situation is set. In an embodiment, the depth of the tail pointer RAM is equal to the number of queues. In this embodiment, the depth of the tail pointer RAM is 256 addresses, and the highest value after the tail pointer RAM is initialized. If the bit is 1 or all 1, it can be known that the initialized queue status is empty.

The pointer linked list RAM is configured to store the pointer linked list, so that the queue pointer linked list and the free pointer linked list share a RAM, thereby eliminating the need for a separate FIFO to store the free pointer, thereby saving hardware resources; the pointer linked list RAM size can be based on Actually, the setting needs to be performed. In this embodiment, the size of the on-chip RAM is 4k, and the pointer list includes a pointer pointing to the next address, and is initialized into a list of empty pointers, as shown in FIG. 2, ptr The RAM is a pointer list RAM, which is initialized, the address of the ptr RAM is from 0 to 8191, and the content stored in the ptr RAM is the next address value, thereby forming a pointer list form; the pointer list includes non-idle pointers and a free pointer; wherein the number of non-free pointers characterizes the total number of addresses occupied by the message descriptors in the on-chip RAM and the off-chip DDR, and the number of non-idle pointers is incremented by one message descriptor per queue. Correspondingly, each time a message descriptor is dequeued, the number of non-free pointers is decremented by one; the on-chip RAM has a one-to-one correspondence with a part of the pointer list RAM, The RAM for packet descriptor information, the address information list pointer corresponding to the RAM; a schematic diagram of data relationships between each of Examples RAM embodiment of the present invention shown in Figure 3;

In Figure 3, head_ptr ram is the head pointer RAM, tail_ptr ram is the tail pointer RAM, ptr ram is the pointer list RAM, and desc ram is the on-chip RAM; wherein the black of the pointer list RAM is a queue member in the queue. 6 queue members, for convenience of explanation, are marked as 1 to 6 (all are virtual tags) in order, and the previous data block stores the address information of the latter data block, because the label 6 is the last data of the queue. Therefore, the data in the pointer list RAM is invalid data; according to the head pointer and the tail pointer, the queue number of the queue is 11, and the address of the data block corresponding to the label 1 is determined by the value stored by the head pointer RAM address 11, and the label 6 corresponds to The data block address is determined by the value stored in the tail pointer RAM address 11.

Step 404: Acquire location information of a queue head pointer corresponding to the dequeuing operation request in the pointer list, and read a corresponding message descriptor according to the location information.

The step includes: extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer in the head pointer RAM according to the queue number, and determining that the position of the queue head pointer in the pointer list is off-chip. In the case of DDR, the off-chip DDR address is calculated, and the corresponding message descriptor in the off-chip DDR is read according to the obtained off-chip DDR address;

Step 405: Update the pointer list information.

The step includes: extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer and an idle tail pointer according to the queue number, and updating the idle tail pointer to point to an address currently indicated by the queue head pointer. And then directing the queue head pointer to the next address in the pointer list.

Step 406: End the current processing flow.

Embodiment 3

FIG. 5 is a schematic structural diagram of a queue management apparatus according to an embodiment of the present invention; The configuration of the queue management device includes: a first processing module 51 and a second processing module 52;

The first processing module 51 is configured to determine that the current operation request is an enqueue operation request of the message descriptor, and store the message descriptor according to the enqueue operation request and the buffer condition of the on-chip RAM. Off-chip DDR or on-chip RAM, and update pointer list information;

The second processing module 52 is configured to determine that the current operation request is a dequeue operation request of the message descriptor, and obtain location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, according to The location information reads the corresponding message descriptor and updates the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.

In an embodiment, the first processing module 51 stores the message descriptor to an off-chip DDR or an on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM, including:

The first processing module 51 determines, according to the enqueue operation request, that the current on-chip RAM has reached the upper limit, calculates an off-chip DDR address, and stores the message descriptor into a slice according to the obtained off-chip DDR address. External DDR;

Determining, when the current on-chip RAM cache does not reach the upper limit, extracting the queue number in the enqueue operation request, and storing the message descriptor to the on-chip RAM according to the queue number;

The first processing module 51 determines that the current upper limit of the on-chip RAM has reached the upper limit, including:

The first processing module 51 determines whether the current on-chip RAM cache has reached the upper limit according to the preset buffer size of the on-chip RAM and the number of non-free pointers in the current pointer list recorded by the cache counter in real time, if the current pointer list is not The number of free pointers is smaller than the preset buffer size of the on-chip RAM, and it is determined that the current on-chip RAM cache has not reached the upper limit; otherwise, it is determined that the current on-chip RAM has reached the upper limit;

In an embodiment, when the current operation request is determined to be an enqueue operation request of the message descriptor, the first processing module 51 updates the pointer list information, including:

The first processing module 51 extracts the queue number in the enqueue operation request, reads the corresponding queue tail pointer and the idle head pointer according to the queue number, and updates the queue tail pointer to point to the current idle pointer. The indicated address, and then directing the free head pointer to a next address in the pointer list;

Here, the tail pointer RAM is used to store the queue tail pointers of all queues, and indicates the queue status of each queue; wherein the queue status includes: empty and non-empty; the size/depth of the tail pointer RAM may be based on actual conditions. In the embodiment, the depth of the tail pointer RAM is equal to the number of queues. In this embodiment, the depth of the tail pointer RAM is 256 addresses, and the highest bit after initializing the tail pointer RAM is 1 or all 1, it can be seen that the initialized queue status is empty;

The pointer linked list RAM is used for storing the pointer linked list, so that the queue pointer linked list and the free pointer linked list share a piece of RAM, thereby eliminating the need for a separate first in first out queue (FIFO, First Input First Output) to store the idle pointer, thereby saving hardware resources. The pointer list RAM size can be set according to actual needs. In an embodiment, the on-chip RAM has a size of 4k, and the pointer list includes a pointer pointing to the next address, and is initialized to a null pointer. The linked list, as shown in Figure 2, the ptr RAM is the pointer linked list RAM, which is initialized, the address of the ptr RAM is from 0 to 8191, and the content stored in the ptr RAM is the next address value, thereby forming a pointer list. a form; the pointer list includes a non-free pointer and a free pointer; wherein the number of the non-free pointers characterizes the total number of addresses occupied by the on-chip RAM and the message descriptor in the off-chip DDR, once for each queue entry The text descriptor, the number of non-free pointers is incremented by one, and correspondingly, each time a message descriptor is dequeued, the number of non-free pointers is decremented by one; the on-chip RAM has a one-to-one correspondence with a part of the pointer list RAM. The in-chip RAM is message descriptor information, and the pointer list table RAM is corresponding address information; FIG. 3 is a schematic diagram of data relationships between respective RAMs according to an embodiment of the present invention;

In an embodiment, the second processing module 52 acquires location information of the queue head pointer corresponding to the dequeuing operation request in the pointer list, and reads corresponding message descriptors according to the location information, including :

The second processing module 52 extracts the queue number in the enqueue operation request, reads the corresponding queue head pointer according to the queue number, and determines that the position of the queue head pointer in the pointer list is off-chip DDR. Calculating an off-chip DDR address, and reading a corresponding message descriptor in the off-chip DDR according to the obtained off-chip DDR address;

In an embodiment, when it is determined that the current operation request is a dequeuing operation request of the message descriptor, The updating, by the second processing module 52, the pointer list information includes:

The second processing module 52 extracts the queue number in the enqueue operation request, reads the corresponding queue head pointer and the idle tail pointer according to the queue number, and updates the idle tail pointer to point to the current queue head pointer. The indicated address, and then the queue head pointer is directed to the next address in the list of pointers.

The first processing module 51 and the second processing module 52 proposed in the embodiments of the present invention may be implemented by a processor, and may also be implemented by a specific logic circuit; wherein the processor may be a processing on a mobile terminal or a server. In practical applications, the processor may be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

In the embodiment of the present invention, if the queue management method is implemented in the form of a software function module and is sold or used as a separate product, it may also be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

Correspondingly, the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the foregoing queue management method of the embodiment of the present invention.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

A queue management method, the method comprising:

Determining that the current operation request is an enqueue operation request of the message descriptor, and storing the message descriptor to the off-chip double rate synchronization according to the enqueue operation request and the buffering condition of the on-chip random access memory RAM Dynamic random access memory DDR or on-chip RAM, and update pointer list information;

Determining that the current operation request is a dequeue operation request of the message descriptor, acquiring location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, and reading the corresponding message description according to the location information And updating the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.
The method of claim 1, wherein the storing the message descriptor to an off-chip DDR or an on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM comprises:

And determining, according to the enqueue operation request, that the current on-chip RAM has reached the upper limit, calculating an off-chip DDR address, and storing the message descriptor to an off-chip DDR according to the obtained off-chip DDR address;

When it is determined that the current on-chip RAM has not reached the upper limit, the queue number in the enqueue operation request is extracted, and the message descriptor is stored in the on-chip RAM according to the queue number.
The method according to claim 1 or 2, wherein when the current operation request is determined to be a queue operation request of the message descriptor, the update pointer list information includes:

Extracting a queue number in the enqueue operation request, reading a corresponding queue tail pointer and a idle head pointer according to the queue number, updating the queue tail pointer to an address indicated by the idle head pointer, and then The idle header pointer points to the next address in the pointer list.
The method according to claim 1 or 2, wherein when the current operation request is determined to be a dequeuing operation request of the message descriptor, the updated pointer list information includes:

Extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer and an idle tail pointer according to the queue number, updating the idle tail pointer to an address indicated by the queue head pointer, and then The queue head pointer points to the next address in the pointer list.
The method according to claim 1 or 2, wherein the acquiring the location information of the queue head pointer corresponding to the dequeuing operation request in the pointer list, and reading the corresponding message descriptor according to the location information includes :

Extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer according to the queue number, and determining an off-chip DDR address when the position of the queue head pointer in the pointer list is in an off-chip DDR Reading the corresponding message descriptor in the off-chip DDR according to the obtained off-chip DDR address;

When it is determined that the position of the queue head pointer in the pointer list is in the on-chip RAM, the corresponding message descriptor in the on-chip RAM is read according to the queue number.
A queue management device, the device comprising: a first processing module and a second processing module; wherein

The first processing module is configured to determine that the current operation request is an enqueue operation request of the message descriptor, and describe the message according to the enqueue operation request and the buffering condition of the on-chip random access memory RAM. Stores to the off-chip double rate synchronous dynamic random access memory DDR or on-chip RAM and updates the pointer list information;

The second processing module is configured to determine that the current operation request is a dequeue operation request of the message descriptor, and obtain location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, according to the The location information reads the corresponding message descriptor and updates the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.
The device according to claim 6, wherein the first processing module is configured to calculate an off-chip DDR address when the current on-chip RAM cache has reached an upper limit according to the enqueue operation request, and according to the obtained off-chip The DDR address stores the message descriptor to an off-chip DDR;

When it is determined that the current on-chip RAM has not reached the upper limit, the queue number in the enqueue operation request is extracted, and the message descriptor is stored in the on-chip RAM according to the queue number.
The device according to claim 6 or 7, wherein the first processing module is configured to extract a queue number in the enqueue operation request, and read a corresponding queue tail pointer and an idle head pointer according to the queue number, Updating the queue tail pointer to the address currently indicated by the free head pointer, and then directing the free head pointer to the next address in the pointer list.
The device according to claim 6 or 7, wherein the second processing module is configured to extract a queue number in the enqueue operation request, and read a corresponding queue head pointer and an idle tail pointer according to the queue number, Updating the idle tail pointer to the address currently indicated by the queue head pointer, and then directing the queue head pointer to the next address in the pointer list.
The device according to claim 6 or 7, wherein the second processing module is configured to extract a queue number in the enqueue operation request, read a corresponding queue head pointer according to the queue number, and determine the queue When the position of the head pointer in the pointer list is in the off-chip DDR, the off-chip DDR address is calculated, and the corresponding message descriptor in the off-chip DDR is read according to the obtained off-chip DDR address;

When it is determined that the position of the queue head pointer in the pointer list is in the on-chip RAM, the corresponding message descriptor in the on-chip RAM is read according to the queue number.
A computer storage medium having stored therein computer executable instructions for performing the queue management method of any one of claims 1 to 5.