CN114817091B - FWFT FIFO system based on linked list, implementation method and equipment - Google Patents

Abstract

The invention provides a FWFT FIFO system based on a linked list, and an implementation method and equipment thereof. The scheme is realized by adopting a linked list mode; a plurality of sub FIFO can be realized inside; RR/SP scheduling can be adopted between the sub-FIFOs for alternative output. The FIFO structure is suitable for the place where queues are needed in the related design of the communication transmission field. Compared with the use of a common FWFT FIFO, the scheme reduces the storage capacity of N-1/N, integrates and schedules internally, and enhances the integration level of the system.

Description

FWFT FIFO system based on linked list, implementation method and equipment

Technical Field

The invention relates to the field of integrated circuit control, in particular to a method and equipment for realizing FWFT FIFO based on a linked list, which can be applied to the specific aspect that FIFO needs to be used in FPGA or ASIC design and can also be applied to equipment needing queues in related design in the field of communication transmission.

Background

The FIFO commonly used in FPGA or ASIC design has two reading modes of a Standard FIFO and a First-word-Fall-Through, and the FWFT (First-word-Fall-Through) can automatically place the latest data on an output port without reading commands.

For the implementation of FWFT FIFO, it is usually modified by standard FIFO, and the implementation block diagram is shown in fig. 1. In the figure, the FWFT FIFO is composed of three modules of a Standard FIFO and a FIFO read enable generation module and a FIFO empty indication generation module, wherein rd _ en and empty are read enable and empty indications of the constructed FWFT FIFO, and FIFO _ rd _ en and FIFO _ empty are read enable and empty indications of the Standard FIFO.

The FIFO _ rd _ en is generated logically as | FIFO _ empty & (| | | | | | rd _ en), meaning that when the Standard FIFO is not empty, if FWFT FIFO is empty (condition 1) or a read operation occurs (condition 2), one data is read out from the Standard FIFO, condition 1 corresponds to a transition of the Standard FIFO from empty to non-empty, the data is to be read out automatically, and condition 2 corresponds to a read operation performed when the Standard FIFO is not empty.

The general domain FWFT FIFO may be adequate, but the applicability of the scenario FIFO involving queues is not sufficient: for example, based on 8 priority queues, 8 FWFT FIFOs are usually instantiated to realize different priority queues, and then the FIFO output with the highest SP scheduling selection level is externally performed. Firstly, for a queue with N elements, since the N elements may be put into any FIFO, the depth of any queue FIFO should be guaranteed to accommodate the N elements, and for a FIFO queue with 8 priorities, 8 × N elements should be accommodated, however, for any time, the number of elements existing in the 8 priority queues at the same time is at most N, that is, a buffer space with 7 × N elements is free, which causes a great waste.

Disclosure of Invention

In order to solve the problems of buffer waste and low integration level in the queue scene, the invention provides a FWFT FIFO system based on a linked list, an implementation method and equipment.

Specifically, the invention discloses the following technical scheme:

on one hand, the invention provides a linked list-based FWFT FIFO system, which can be used for effectively scheduling a plurality of independent sub FIFOs and comprises a TAG management module, a linked list maintenance module, an RAM read-write control module and an output scheduling module;

the TAG management module is used for distributing node numbers for input write data, completing linked list connection operation and generating empty and full indications of all sub FIFOs according to the using condition of the TAG label;

the linked list maintenance module is used for maintaining the head pointer, the tail pointer and the linked list node information; the linked list node information is stored in an external RAM;

the RAM read-write control module comprises an externally arranged RAM and is used for controlling the read and write operations of the RAM; the RAM stores pointer information and storage data of each sub FIFO;

and the output scheduling module selects one from the head pointer data of the multi-link list for output.

Further, each sub FIFO is constituted by a linked list. I.e. one complete linked list corresponds to one sub FIFO.

Preferably, the TAG management module is realized through bitmap, and when data is written into the sub FIFO, an idle TAG is applied from the TAG TAG; and when the sub FIFO has data read, returning the TAG label corresponding to the read data to the TAG management module.

Preferably, in the TAG management module, TAG _ Valid indications with the same number as the depth of the sub FIFOs are maintained in the TAG, and the TAG _ Valid indications are used for indicating the corresponding sub FIFOs are empty and full.

Preferably, when a write operation occurs to the sub-FIFOs, Tag values indicated as empty by the Tag _ Valid are searched in order, and the indication of the corresponding Tag _ Valid is changed to non-empty after the write operation is completed.

Preferably, when the sub FIFO is in a read operation, the TAG corresponding to the read data is returned to the resource pool, and the indication of the corresponding TAG _ Valid is changed to be empty.

Preferably, the linked list maintenance module comprises a head pointer maintenance unit, a tail pointer maintenance unit and a linked list node number maintenance unit;

the linked list maintenance module independently maintains a set of head pointer and tail pointer for each sub FIFO, and the middle nodes of the sub FIFOs are mutually shared;

the number of the sub FIFO is configured by a parameter; the paramter is a parameter whose value represents the number of sub FIFOs.

Preferably, the head pointer maintenance unit is used for maintaining a head pointer;

the head pointer points to Tag _0 corresponding to the first node of the corresponding sub FIFO, and the node corresponding to the Tag _0 stores the label corresponding to the next node; and effective data are respectively stored on the head pointer and the nodes corresponding to the labels.

Further, the head pointer stores the first valid data of the sub-FIFO, the first node stores the second valid data, and so on. No valid data is stored in the tail pointer.

Preferably, the tail pointer maintenance unit maintains the tail pointer according to the following update rule:

and when new data is written, the tail pointer is updated to be a label corresponding to the newly written data.

Preferably, the linked list node number maintenance unit is configured to record writing and reading of the linked list to determine whether the linked list participates in output scheduling.

Preferably, the update rule of the head pointer in the linked list is as follows:

when the number of the chain table nodes is 1 and the writing and reading operations occur simultaneously, the head pointer is updated to the label and the data corresponding to the new written value; when the number of the chain table points is 0 and the write operation occurs, the head pointer is updated to the label and the data corresponding to the new write value; when the number of the linked list nodes is more than 1, and when the reading operation occurs, the head pointer is updated to the label and the data corresponding to the next node.

Preferably, the mode of controlling the read and write operations of the RAM by the RAM read-write control module is as follows:

for write operation, when the linked list to be written is not empty, writing the label and data corresponding to the new written value into the address pointed by the tail pointer of the linked list;

for a read operation, when the number of linked list nodes to be read is greater than 1, data is read from the address pointed by the head pointer, and the read data is updated to the head pointer.

On the other hand, the invention also provides a FWFT FIFO implementation method based on the linked list, which is applied to the FWFT FIFO system based on the linked list and comprises data writing and data reading;

for data writing, the steps include:

step 11, the newly written data applies for TAG labels from the TAG management module, and the empty and full indications of each sub FIFO are updated (namely, the empty and full states of the sub FIFOs are updated);

step 12, the newly written data updates the selected sub FIFO queue, and the head pointer, the tail pointer and the middle node information of the sub FIFO queue are updated;

step 13, the newly written data updates the node number information of the selected sub FIFO queue;

step 14, updating the data output of the FIFO according to the scheduling condition of the output scheduling module by the newly written data;

for data readout, the steps include:

step 21, updating a head pointer, a tail pointer and intermediate node information of the sub FIFO queue where the data are read out;

step 22, updating the node quantity information of the sub FIFO queue after reading the data;

and step 23, reading the data and returning the TAG label, and updating the empty and full indications of each sub FIFO (namely updating the empty and full states of the sub FIFOs).

In addition, the invention also provides FWFT FIFO equipment based on the linked list, which comprises a processor and a memory;

the processor calls instructions in the memory to perform the linked list based FWFT FIFO implementation method described above.

Compared with the prior art, the scheme of the invention can instantiate N independent sub FIFOs in one FWFT FIFO and effectively manage the read-write data of the sub FIFOs, and the sub FIFOs can select one of the sub FIFOs for output by a specific scheduling method, such as RR or SP and the like. The invention is applied to FPGA or ASIC realization in the communication field, reduces N-1/N memory space, realizes internal integrated scheduling and enhances the integration level of the system compared with the common FWFT FIFO.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram of a conventional FWFT FIFO structure in the prior art;

FIG. 2 is a schematic diagram of a chain-table-based FWFT FIFO implementation structure according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating an initial state of BitMap according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating BitMap states after writing two data according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a BitMap state after data corresponding to tag 1 is read according to an embodiment of the present invention;

fig. 6 is a three-node chain representation of an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be appreciated by those of skill in the art that the following specific examples or embodiments are set forth in a series of optimized configurations for further explanation of the specific disclosure, and that all such configurations may be combined or used in conjunction with one another, unless specifically set forth herein as being incompatible with or used in conjunction with other embodiments or embodiments. Meanwhile, the following specific examples or embodiments are only provided as an optimized arrangement mode and are not to be understood as limiting the protection scope of the present invention.

In a specific embodiment, as shown in fig. 2, the implementation structure of the technical solution provided by the present invention preferably includes the following components: the system comprises a TAG management module, a linked list maintenance module, an RAM read-write control module and an output scheduling module. The linked list maintenance module further comprises a head pointer maintenance unit, a tail pointer maintenance unit and a linked list node number maintenance unit. Preferred implementations of the individual modules are explained below.

According to the scheme of the invention, a plurality of independent sub-FIFOs are instantiated through a plurality of modules and parameters controlled by the modules, and one of the sub-FIFOs can be selected for output through a corresponding scheduling method. Here, as for the scheduling method of the sub FIFO, a strict priority scheduling SP method may be adopted, and in a specific implementation, the priority of the sub FIFO 0 in the sub chain table may be set to be the lowest, the priority of the sub FIFO n-1 may be the highest, and the sub FIFO with the highest priority may be preferentially selected for reading; the scheduling of the sub-FIFOs can also be performed by adopting a Round-Robin polling scheduling mode, for example, the scheduling is performed according to the sequence from 0- (n-1) to n- (n-1); the sub FIFO can be scheduled by WRR, DRR and the like.

Firstly, a TAG management module:

the module is mainly used for distributing node numbers for input FIFO write data, performing link operation of a user linked list, and generating empty and full indications of each sub FIFO according to the use condition of a TAG label; in a preferred embodiment, the module is implemented by bitmap, and the work flow is as follows: when FIFO has data to write, applying for an idle TAG from TAG TAGs, and when FIFO has data to read, returning the TAG TAG corresponding to the read data to the TAG management module.

With reference to fig. 3, in a preferred embodiment, the bitmap implementation method for TAG may be set as follows: for a FIFO with a depth of n, maintaining a Tag _ Valid indication of n bits, all Tag _ Valid values are all 1 when the initial FIFO is empty. Tag _ Valid is used to indicate whether the corresponding node of the linked list is already allocated or occupied, i.e. indicates the empty and full status of the corresponding sub-FIFO.

In a preferred embodiment, further elaboration is made with practical examples: at the beginning, the FIFO is empty, all linked list nodes can be set to be empty, at this time, all Tag _ Valid can be set to be 1, indicating that the FIFO is empty, that is, the corresponding node of the linked list is not allocated or occupied; in the subsequent working process, when a node is strung into the linked list of a certain sub-FIFO, the Tag _ Valid corresponding to the node is set to 0, which represents that the node is occupied and cannot be utilized by other sub-FIFOs, until the node is released, the Tag _ Valid corresponding to the node is set to 1, and then the node cannot be utilized again to be connected in series into the linked list of a certain sub-FIFO.

When FIFO occurs write operation, the TAG with value 1 is searched for BitMap according to the sequence from 0 to (n-1) or from (n-1) to 0, when the TAG is found, the corresponding TAG value is output, and the corresponding TAG _ Valid is set to 0. Referring to fig. 4, after writing two data, the BitMap state is as shown in fig. 4, where Tag _ Valid [0] and Tag _ Valid [1] are set to 0, in this example, Tag with value 1 is searched in the order from 0 to (n-1), and at the beginning, the first Tag _ Valid [0] is searched to 1, and at this time, the corresponding Tag value is output, and Tag _ Valid [0] is set to 0; and then, starting to search from 0 again, at this time, when the value of the second bit of Tag _ Valid [1] is found to be 1, outputting the corresponding TAG value, and setting the Tag _ Valid [1] to 0.

When the FIFO is subjected to a read operation, as shown in fig. 5, the TAG corresponding to the read data needs to be returned to the resource pool, and the TAG _ Valid value corresponding to the TAG is directly set to 1, that is, the indication of the corresponding TAG _ Valid is modified to be empty for subsequent recall.

Second, linked list maintenance

In a more preferred embodiment, in combination with fig. 6, for the linked list, three types of information are mainly maintained, that is, the head pointer, the tail pointer, and the node information in the middle of the linked list, and for this implementation, the node information of the linked list is stored in the external RAM to support more storage capacity. The conventional FIFO has no concept of linked list nodes, and the management of the FIFO is performed through the sequential ordering of RAM addresses, which is one of the important differences between the present invention and the prior art.

As shown in fig. 6, a set of head pointer and tail pointer is maintained in each queue (i.e., each sub FIFO), and the middle node is shared by each sub FIFO, which is also the reason why the linked list structure FIFO provided by the present invention can save resources compared with a common FIFO. The number of queue entries present in the FIFO (i.e., the number of sub-FIFOs) can be configured by means of a modular instantiated parameter, which maintains only one sub-FIFO when the value of the parameter is 1.

Here, the parameter is a parameter, and in a more specific embodiment, the parameter may use a concept in the Verilog syntax of the IC design language, and when instantiating, a specific value of the parameter needs to be specified, which is also a standardized requirement based on the Verilog reason.

The value of paramter represents the number of sub-FIFOs, and the sub-FIFOs are selected by scheduling, in a preferred embodiment, each sub-FIFO is assigned a certain weight, and we can distinguish according to the number of each sub-FIFO, for example, 0 is the lowest priority, n-1 is the highest priority, and the sub-FIFO (or queue) corresponding to n-1 is preferentially selected for reading operation by the scheduling algorithm for setting the priority.

1. Maintaining a head pointer:

FIG. 6 is a schematic diagram of a linked list including three nodes. The Head pointer Head _ Ptr points to Tag _0, the node corresponding to Tag _0 stores the next node Tag _1, the node corresponding to Tag _1 stores the next node Tag _2, and since Tag _2 is the last node of the linked list, the tail pointer of the linked list also points to Tag _ 2. While the linked list structure is realized, effective Data, such as Data (0), Data (1) and Data (2) shown in fig. 6, are respectively stored on the head pointer, the Tag _0 and the Tag _1 nodes, that is, the first Data (0) in the sub FIFO is stored in the head pointer node, the second Data (1) in the sub FIFO is stored in the Tag _0 node, and so on, thereby realizing the function of storing Data in the FIFO. In this embodiment, Tag _0, Tag _1, Tag _2, and the like represent Tag labels, and when the TAGs are connected in series to a linked list, the TAGs are referred to as nodes of the linked list. In this embodiment, Tag _0 corresponds to Tag _ Valid [0], and other corresponding numbers may also be set to be similar one-to-one correspondence, and the value of Tag _ Valid [0] represents whether Tag _0 has been concatenated into a chain to become a node of a sub FIFO.

In a preferred embodiment, for the maintenance of the head pointer of the linked list, the update rule may be set as follows:

(1) when the number of the nodes of the linked list is 1 and the writing and reading operations occur simultaneously, the head pointer is updated to the label and the data corresponding to the new written value;

(2) when the number of the linked list nodes is 0 and write-in operation occurs, the head pointer is updated to the label and the data corresponding to the new write-in value;

(3) and when the number of the nodes of the linked list is more than 1, and when the reading operation occurs, the head pointer is updated to the label and the data corresponding to the next node.

2. And (3) tail pointer maintenance:

as shown in fig. 6, the node TAG _2 corresponding to the last TAG is stored in the Tail pointer Tail _ Ptr, and at this time, it is preferable that valid data is not stored in the Tail pointer any more, and only the corresponding TAG is stored.

The update rule of the tail pointer is as follows:

and when new data is written, updating the new data to a tag corresponding to the new written value. Thus, it is ensured that the tail pointer always corresponds to the last tag in the FIFO during FIFO operation.

3. Maintaining the number of linked list nodes:

when the subsequent linked list output scheduling is carried out, because a plurality of sub-FIFOs (first in first out) are involved in the scheduling, namely a plurality of linked lists are formed, the invention sets a preferential judgment step, namely whether the linked list has data or not is judged, the corresponding linked list (namely the sub-FIFO) can participate in the scheduling only under the condition that the data exists, and the scheduling is not participated if the linked list is initially empty FIFO. In a preferred embodiment, the method may be implemented by maintaining a Counter (i.e., a Counter), that is, maintaining a corresponding Counter (i.e., a Counter) in each sub-FIFO, where the Counter adds 1 when the corresponding linked list is written, subtracts 1 when the corresponding linked list is read, and maintains the value when the value is read, so that when determining whether the linked list participates in scheduling, it is only necessary to directly determine the value of the Counter (i.e., the Counter), for example, when the value is greater than or equal to 1, it indicates that there is data in the linked list (i.e., the sub-FIFO), and it may participate in scheduling, otherwise, the linked list does not participate in scheduling. As can be seen from the above description, the Counter records the depth of the corresponding sub-FIFO, or the number of its corresponding linked list nodes.

Thirdly, RAM read-write control:

in order to realize larger FIFO depth, it is far from enough to simply use a register to build a storage structure, and an external RAM must be used. In this implementation, the RAM is used to store the pointer information of the node and to store data, and preferably the depth of the RAM may be set to coincide with the depth of the FIFO, with one TAG TAG for each RAM address, corresponding to the TAG _0/TAG _1 …/TAG _ (n-1) banks of FIG. 6.

The RAM write operation rule is that when the linked list to be written is not empty, that is, the number of nodes maintained by the linked list is not 0, the label and data corresponding to the newly written value are written into the address pointed by the tail pointer of the linked list.

The RAM read operation rule is that when the number of linked list nodes to be read out is more than 1, data is read out from the address pointed by the head pointer. And combining the updating rule of the head pointer, and updating the read data into the head pointer.

Fourthly, output scheduling:

the purpose of the output scheduling module is to select one output from the head pointer data of the multiple linked lists, and the adopted scheduling mode can be RR (round robin) or SP (strict priority) and the like.

In summary, through the processing of the above four main blocks, a linked list-based multi-queue FWFT FIFO is implemented, and compared with a common FWFT FIFO, a plurality of queues (or referred to as sub-FIFOs) can be merged into one FIFO structure, and can be selectively output through integrated scheduling. The FIFO structure is particularly suitable for a scene that a plurality of queues are needed in communication related design.

In another embodiment, the working principle of the FIFO is as follows:

during the writing of data:

1. the newly written data applies for the TAG label from the TAG management module, and the empty and full information of the FIFO, namely the empty and full indication, is updated;

2. the newly written data updates the selected queue (for example, according to the field specified in the data), and updates the information of a head pointer, a tail pointer, an intermediate node and the like of the queue form;

3. the newly written data updates the node number information of the selected queue so as to monitor the state of the selected queue;

4. the newly written data updates the data output of the FIFO according to the scheduling condition;

during the reading of the data:

5. after data is read out, information such as a head pointer, a tail pointer and an intermediate node of the queue where the data is located is updated;

6. after reading out the data, updating the node quantity information of the queue;

7. the read data returns the TAG and updates the FIFO's empty-full indication.

It should be noted that, there is no necessary strict sequence relationship between the data writing process and the data reading process, and the symbols of the steps are only used for convenience of explaining the execution principle of the invention. I.e. the writing of data is relatively independent of the reading of data.

In addition, in a more preferred embodiment, the present solution may also be implemented by means of an electronic device, which may include corresponding modules that execute the above-mentioned linked list-based FWFT FIFO system. Thus, each step or several steps of the above described embodiments may be performed by a respective module, and the device may comprise one or more of these modules. The modules may be one or more hardware modules specifically configured to perform the respective steps, or implemented by a processor configured to perform the respective steps, or stored within a computer-readable medium for implementation by a processor, or by some combination.

Any process or method descriptions otherwise herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present disclosure includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of implementation of the present disclosure. The processor performs the various methods and processes described above. For example, method embodiments in the present scheme may be implemented as a software program tangibly embodied in a machine-readable medium, such as a memory. In some embodiments, some or all of the software program may be loaded and/or installed via memory and/or a communication interface. When the software program is loaded into memory and executed by a processor, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform one of the methods described above by any other suitable means (e.g., by means of firmware).

The logic and/or steps otherwise described herein may be embodied in any readable storage medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (7)

1. The FWFT FIFO system based on the linked list is characterized in that the system is used for scheduling a plurality of sub FIFOs, each sub FIFO consists of the linked list, and the system comprises a TAG management module, a linked list maintenance module, an RAM read-write control module and an output scheduling module;

the TAG management module is used for distributing node numbers for input write data, completing linked list connection operation and generating empty and full indications of all sub FIFOs according to the using condition of the TAG label;

the linked list maintenance module is used for maintaining the head pointer, the tail pointer and the linked list node information; the link table node information is stored in an external RAM;

the RAM read-write control module comprises an externally arranged RAM and is used for controlling the read and write operations of the RAM; the RAM stores pointer information and storage data of each sub FIFO;

the output scheduling module selects one from the head pointer data of the multi-chain table for output;

the TAG management module is realized through bitmap, and when data are written in the sub FIFO, an idle TAG is applied from the TAG TAG; when the sub FIFO has data read, the TAG label corresponding to the read data is returned to the TAG management module;

the linked list maintenance module comprises a head pointer maintenance unit, a tail pointer maintenance unit and a linked list node number maintenance unit;

the linked list maintenance module independently maintains a set of head pointer and tail pointer for each sub FIFO, and the middle nodes of the sub FIFOs are mutually shared;

the number of the sub FIFO is configured by a parameter; the paramter is a parameter, and the value of the paramter represents the number of the sub FIFOs;

the head pointer maintenance unit is used for maintaining a head pointer;

the head pointer points to a TAG label TAG _0 corresponding to the first node of the corresponding sub FIFO, and the node corresponding to the TAG _0 stores a label corresponding to the next node; and effective data are respectively stored on the head pointer and the nodes corresponding to the labels.

2. The system of claim 1, wherein the TAG management module maintains a same number of TAG _ Valid indications in the TAG as the sub-FIFO depth, the TAG _ Valid indications indicating whether the corresponding node of the linked list is already allocated or occupied.

3. The system of claim 2, wherein when a write operation occurs to a sub-FIFO, Tag values indicated as empty by Tag _ Valid are searched in order, and the indication of the corresponding Tag _ Valid is changed to non-empty after the write is completed.

4. The system of claim 2, wherein when a read operation occurs in the sub-FIFO, the TAG corresponding to the read data is returned to the resource pool and the indication of the corresponding TAG _ Valid is changed to empty.

5. The system of claim 1, wherein the RAM read-write control module controls the read and write operations of the RAM in a manner that:

for write operation, when the linked list to be written is not empty, writing the label and data corresponding to the new written value into the address pointed by the tail pointer of the linked list;

for a read operation, when the number of linked list nodes to be read is greater than 1, data is read from the address pointed by the head pointer, and the read data is updated to the head pointer.

6. A chained list-based FWFT FIFO implementation method, applied to the chained list-based FWFT FIFO system of any one of claims 1-5, the method comprising data writing and data reading;

for data writing, the steps include:

step 11, the newly written data applies for TAG labels from the TAG management module, and the empty and full indications of each sub FIFO are updated;

step 12, the newly written data updates the selected sub FIFO queue, and the head pointer, the tail pointer and the middle node information of the sub FIFO queue are updated;

step 13, the newly written data updates the node number information of the selected sub FIFO queue;

step 14, updating the data output of the FIFO according to the scheduling condition of the output scheduling module by the newly written data;

for data readout, the steps include:

step 21, updating a head pointer, a tail pointer and intermediate node information of the sub FIFO queue where the data are read out;

step 22, updating the node quantity information of the sub FIFO queue after reading the data;

and step 23, reading out the data and returning the TAG label, and updating the empty and full indications of each sub FIFO.

7. A linked list based FWFT FIFO device, characterized in that the device comprises a processor, a memory;

the processor calls an instruction in the memory to perform the linked list-based FWFT FIFO implementation of claim 6.

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