CN111274173A

CN111274173A - ZYNQ-based multi-node SRIO communication design method and device

Info

Publication number: CN111274173A
Application number: CN202010223318.1A
Authority: CN
Inventors: 陈晓红; 李建军
Original assignee: Sichuan Hongchuang Electronic Technology Co ltd
Current assignee: Sichuan Hongchuang Electronic Technology Co ltd
Priority date: 2020-03-26
Filing date: 2020-03-26
Publication date: 2020-06-12

Abstract

The invention discloses a ZYNQ-based multi-node SRIO communication design method, which comprises the following steps: s1: PL processing response and request protocol packets to obtain protocol types of data and giving an indication mark; s2: classifying and caching the user interface data according to the indication marks, putting each complete frame into a cache queue, and judging a queue space; s3: the PS receives and transmits data; s4: in the process of receiving and sending data by the PS, the PL carries out multi-node data processing to obtain different data sending completion interrupts or receiving completion interrupts and sends the data sending completion interrupts to the PS, and a plurality of data query registers are provided; s5: the PS completes interruption according to the received data sending or completes interruption and reads corresponding data, clears the interruption after completing the reading operation, inquires whether remaining instructions are executed, and returns to S1; not only multi-node communication is satisfied, but also flexible processing of an application layer is satisfied.

Description

ZYNQ-based multi-node SRIO communication design method and device

Technical Field

The invention relates to the field of electronic communication, in particular to a ZYNQ-based multi-node SRIO communication design method.

Background

High-speed ADC collection or high-speed GTX/GTH data transmission is needed in the field of high-speed AD, SRIO communication and data transmission are needed, devices such as DSP and the like cannot meet the requirements of ADC collection and the like, and FPGA is needed to realize the SRIO communication, however, most of the existing SRIO communication based on FPGA is single-point communication or data transmission, and FPGA using multiple nodes to communicate or transmit cannot transplant the SRIO processing application of the traditional DSP.

The Serial RapidIO Gen2 IP core provided by the FPGA implements protocols below an application layer, but does not provide multi-node control application, so that the SRIO communication based on the FPGA is limited by node control, point-to-point communication and point-to-point data transmission are frequently carried out, and the multi-node communication limits the application of the application layer due to the lack of flexibility of the DSP.

Disclosure of Invention

The invention aims to solve the technical problem that multi-node communication based on an FPGA is not flexible when high-speed ADC acquisition or high-speed GTX/GTH data transmission is required and SRIO communication and data transmission are required, and provides a multi-node SRIO communication design method based on ZYNQ, so that the problems are solved.

The invention is realized by the following technical scheme:

a multi-node SRIO communication design method based on ZYNQ comprises the following steps:

s1: PL processing response and request protocol packets to obtain protocol types of data and giving an indication mark;

s2: classifying and caching the user interface data according to the indication marks, putting each complete frame into a cache queue, and judging a queue space;

s3: the PS receives and transmits data;

s4: in the process of receiving and sending data by the PS, the PL carries out multi-node data processing to obtain different data sending completion interrupts or receiving completion interrupts and sends the data sending completion interrupts to the PS, and provides a plurality of data query registers for the PS;

s5: the PS sends a completion interrupt or receives a completion interrupt to read corresponding data according to the received data, clears the interrupt after completing the reading operation, inquires whether there is any remaining instruction to execute, and returns to S1.

The invention utilizes the PL + PS framework of ZYNQ to realize the communication design by the advantages of multi-node communication, and data processing of different types of protocols is carried out by PL and PS.

Further, the PS receives data: and sending the cache data to the FIFO hung on the DMA, and simultaneously using the PL to control the DMA controller to send the related data to the DDR3 of the PS.

Further, the PS sends data: the PL controls DMA according to the address and length of the data fetch to be transmitted, reads the data into the PL FIFO, and transmits it.

Further, the protocol type of the data obtained by the PL processing the response and request protocol packets includes: doorbell, Message, and DIO, where DIO includes Nwrite and Nread.

Further, when the storage of the queue space is gradually full, a data full mark is given, and a packet header which cannot be received by data is fed back through a bottom layer protocol packet, so that the data is not received any more.

In the invention, the packet header which can not be received by the data is fed back by the bottom layer protocol packet, so that the link failure and disconnection can be prevented while the data is not received.

Further, the plurality of data query registers include: source ID, Doorbell data, address of Nwrite write DDR3, write length, and mailbox number.

In the present invention, the above operations are performed to give a data transmission completion interrupt or a reception completion interrupt to the PS, and a data query register is provided, including: source ID, Doorbell data, address of Nwrite write DDR3, write length, mailbox number, etc., as follows:

when a Response protocol packet is received, interrupt information generated by different data types and a data query register are provided, including:

doorbell data: providing a PS external interrupt and a data query register, wherein the data query register comprises a source ID and Doorbell data;

DIO Nwrite data: reading a Nwrite address, sending data to a DMA plug-in FIFO, controlling a DMA controller to give a write length by using PL, sending the data to DDR3 of PS by using the write address, giving an external interrupt, and providing a data query register, wherein the data query register comprises a source ID, an address and a length of writing the Nwrite into the DDR 3;

when complete package analysis of ID data is completed, namely, data is subjected to queue caching, the cached queue data is sent to a DMA (direct memory access) plug-in FIFO, a PL (programmable logic device) is used for controlling a DMA controller to give a write length and a write address, the data is sent to a DDR (double data rate) 3 of a PS (packet switching), an external interrupt is given, and meanwhile, a data query register is provided and comprises a source ID (identity) and an address and a length written into a DDR3 by Nwrite;

the data obtained by analyzing the complete packet of the ID data comprises a source ID, a data length and an address field of a write DDR3 of the Nwrite;

nread data for DIO: reading an Nread read address, controlling a DMA (direct memory access) controller by using PL (programmable logic device), giving a read length and an address, sending related data of DDR3 of PS (packet data center) to FIFO of PL, and sending out the data;

message data: the PS allocates N address fields for caching Message data of different nodes; according to the indication mark, the ID number of the Message is identified, then the data is cached in different ID types according to the ID number, and the last byte data is judged according to msg _ len and msg _ seg;

when complete package analysis of ID data is completed, namely, the data is subjected to queue caching, the cached queue data is sent to a DMA (first in first out) plug-in, a PL (programmable logic device) is used for controlling a DMA controller, writing length and address are given, the data is sent to DDR3 of PS (packet data processing), external interruption is given, and meanwhile, a data query register is provided, wherein the address, the length and the mailbox number of source ID and Message written into DDR 3;

the data obtained by analyzing the complete package of the ID data comprises a source ID, a mailbox number, a data length and an address field distributed by a PS.

When a Request protocol packet is received, interrupt information generated by different data types and a data query register are provided, wherein the interrupt information comprises:

doorbell data: PL provides a doorbell data register, an opposite end ID register, a transmission enable register and a transmission completion register; the PS stores the data and the ID into a PL register, gives out sending enable, and then detects a completion mark;

DIO Nwrite data: PL provides Nwrite local data fetch address, opposite storage address, opposite ID, sending data length, enabling, completing flag register; the PS stores the address, the data and the ID into a PL register, gives a sending enable, and then detects a completion mark;

nread data for DIO: PL provides Nread's opposite end data fetch address, local memory address, opposite end ID, read data length, enable, complete flag register;

PS stores the address, data and ID into PL register to give out read enable;

the PL sends out a request data packet according to the read enable, caches the returned data, and simultaneously caches Response related data in a cache queue;

the data to be processed queue buffer memory after the complete packet analysis is completed comprises a source ID, a data length and a local memory address; sending the cache queue data to a DMA (first in first out) plug-in FIFO (first in first out), using PL (programmable logic device) to control a DMA controller, giving out a write length and a write address, sending the data to a DDR (double data rate) 3 of a PS (packet switched), giving out external interruption, and simultaneously providing a data query register comprising a source ID (identity), a local storage address and a length;

message data: the PL provides a local data access address, an opposite terminal ID, a mailbox number, a data sending length, an enable and completion flag register of the Message data; the PS stores the mailbox number, data and ID into the PL register, gives the send enable, and then detects the completion flag.

Further, the types of the PS reception data include: PL passively receives Nwrite, PL passively receives Message, and PS actively calls Nread.

Further, the types of PS transmission data include: the PL passively sends Nread, PS active Call Message, and PS active Call Nwrite.

In the present invention, the PS receives data, and the PL multi-node data processing flow includes:

when the type of the received data is PL passive receiving Nwrite, performing Nwrite frame header judgment, and when the judgment result is not the Nwrite frame header, performing Nwrite frame header judgment again;

when the judgment result is the Nwrite frame header, locking the ID and the address, receiving and counting the data, and judging whether the data is the last data;

when the judgment result is not the last data, repeatedly judging whether the data operation is the last data operation; when the judgment result is the last data, caching the ID, the address needing to be written into the DDR3, the data and the data length into the FIFO, storing the data into one FIFO, and storing the data length into the other FIFO;

judging whether data exist or not according to the length FIFO, wherein one length value corresponds to one frame data completion of one ID, and when the FIFO is empty, repeating the operation of judging whether data exist or not according to the length FIFO and one frame data completion of one length value corresponding to one ID;

when the FIFO is not empty, taking out the data corresponding to the length and writing the data into an external PL cache register of the PS, and simultaneously calling the DMA by the PL to write the data into the DDR3 of the PS;

after the operation is finished, giving out an interrupt and an interrupt mark and sending the interrupt and the interrupt mark to the PS; after receiving the interrupt, the PS reads the Nwrite data length, the address and the ID; after the operation is completed, the interrupt and the corresponding interrupt flag bit are cleared.

When the type of the received data is PL passive Message receiving, performing Message frame header judgment and judging whether the received data is a first packet;

when the judgment result is that the packet is the first packet, locking the ID and setting the cache BUSY, and giving a flag bit of the received data corresponding to the ID;

when the judgment result is not the first packet, judging whether the ID is the ID which is not received completely, and when the judgment result is not the ID which is not received completely, judging the Message frame header again and judging whether the ID is the first packet;

when the judgment result shows that the ID which is not received completely exists or the locking ID and the setting buffer BUSY are completed, after the flag bit operation of the received data corresponding to the ID is given, whether the data corresponding to the ID is received as the last packet and is a TLAST signal is judged according to msg _ len and msg _ seg;

when the packet is the last packet, the received data is stored in a first-level cache FIFO and counted;

when the packet is not the last packet, the PS allocates N node data storage addresses, and selects one address according to the current data receiving state;

giving out the data length, ID and DDR3 cache address of the current packet and writing the data length, ID and DDR3 cache address into the second-level cache FIFO, judging the remaining space of the second-level cache FIFO in the process, stopping receiving immediately when the cache space is gradually full, and giving out a receiving stop mark;

judging whether the second-stage FIFO has data or not, and repeatedly judging whether the second-stage FIFO has data operation or not when the FIFO is empty;

when the FIFO is not empty, reading the length, the ID, the DDR3 cache address, the mailbox number and the received complete sequence number packet of the second-level cache data, writing the data into the PS external PL cache register, and calling the DMA by the PL to write the data into the DDR3 of the PS;

after the operation is finished, giving out an interrupt and an interrupt mark and sending the interrupt and the interrupt mark to the PS; after receiving the interrupt, the PS reads the Message data length, the ID, the DDR3 cache address, the mailbox number and the received complete sequence number packet; after the operation is completed, the interrupt and the corresponding interrupt flag bit are cleared.

When the type of the received data is PS to actively call Nread, the PL sends a frame packet header according to the reading opposite end address, the length and the ID set by the PS;

receiving and counting data, judging whether the data is the last data, and when the data is not the last data, repeatedly receiving and counting the data, and judging whether the data is the last data operation;

when the data is the last data, storing the received data and the length into different FIFOs respectively;

judging whether the length FIFO has data or not, and repeatedly judging whether the FIFO has data operation or not when the FIFO is empty;

when the FIFO is not empty, taking out the data corresponding to the length, writing the data into an external PL cache register of the PS, and calling the DMA by the PL to write the data into the DDR3 of the PS;

after the operation is finished, giving out an interrupt and an interrupt mark and sending the interrupt and the interrupt mark to the PS; after receiving the interrupt, the PS reads the length, address and ID of the Nread data; after the operation is completed, the interrupt and the corresponding interrupt flag bit are cleared.

PS sends data, and the PL multi-node data processing flow comprises the following steps:

when the type of the transmitted data is PL passive transmission Nread, Nread frame header judgment is carried out, and when the type of the transmitted data is not a frame header, Nread frame header judgment is carried out again;

when the frame is a frame header, the ID, the address and the length are locked, and the PL calls a DMA controller to read DDR3 data of the PS to a PL cache;

and after the operation is finished, data is sent according to the sending interface control signal.

When the type of the sending data is PS to actively call the Message, the PL sends the local address and the length of the data according to the PS;

the PL calls a DMA controller to read DDR3 data of the PS to a PL cache, the data is read for several times according to the size of the cache, and the base address of the data read each time is accumulated according to the read data;

PL detects the data reading completion mark, and sends data according to a frame protocol, and single packet data does not exceed 256 bytes;

When the type of the sending data is that the PS actively calls Nwrite, the PL sends the local address and the length of the data according to the PS, and the length of the data does not exceed 4096 bytes;

the PL calls the DMA controller to read the DDR3 data of the PS to the PL cache;

PL detects the data reading completion mark, sends data according to a frame protocol, calculates and sends several packet data to obtain msg _ len and msg _ seg, and single packet data does not exceed 256 bytes;

A multi-node SRIO communication device based on ZYNQ comprises a Serial RapidIO switch and a ZYNQ module;

the ZYNQ module comprises a Serial RapidIO Gen2 IP core module, a PL module and a PS module;

the Serial RapidIO switch and the Serial RapidIO Gen2 IP core module perform data interaction so as to generate a response and request protocol packet;

the Serial RapidIO Gen2 IP core module transmits the response and the request to the PL module;

the PL module processes the response and request protocol packets to obtain the protocol type of the data and gives an indication mark;

classifying and caching the user interface data according to the indication marks, putting each complete frame into a cache queue, and judging a queue space;

and the PS module performs data receiving and data sending operations, completes interruption according to the received data sent by the PL module or completes interruption in receiving and reading corresponding data, clears the interruption after the reading operation is completed, and inquires whether a residual instruction is executed.

Further, the DDR3 module is also included;

the PL module comprises a response processing module, a request processing module and a DMA controller;

the PS module includes a function processing module, a DDR3 controller and a PS DDR3 module.

Compared with the prior art, the invention has the following advantages and beneficial effects:

the invention relates to a ZYNQ-based multi-node SRIO communication design method, which adopts a ZYNQ framework, uses PL to carry out application protocol analysis and multi-node data queue cache to realize data communication, and PL to control data reading, and PS to carry out data processing and instruction control, thereby solving the problems of portability and processing of an application layer to a bottom layer protocol, meeting the requirements of multi-node communication and flexible processing of the application layer, and being capable of carrying out mixed communication with a plurality of nodes simultaneously.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a flow chart of a ZYNQ-based multi-node SRIO communication design of the present invention;

FIG. 2 is a block diagram of the overall structure of ZYNQ-based multi-node SRIO communication according to the present invention;

FIG. 3 is a block diagram of a routine for an IP core of an SRIO of the FPGA of the present invention;

FIG. 4 is a flow chart of response and request data stream processing according to the present invention;

FIG. 5 is a PS receive data, PL multi-node data processing flow in accordance with the present invention;

FIG. 6 shows the PS data transmission and PL multi-node data processing flow of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Example 1

As shown in fig. 1, fig. 3 and fig. 4, a multi-node SRIO communication design method based on ZYNQ includes:

s3: the PS receives and transmits data;

PS stores the address, data and ID into PL register to give out read enable;

As shown in fig. 5, the PS receiving data, PL multi-node data processing flow includes:

As shown in fig. 6, the PS transmit data, PL multi-node data processing flow includes:

As shown in FIG. 2, the ZYNQ-based multi-node SRIO communication device comprises a Serial RapidIO switch and a ZYNQ module;

Further, the DDR3 module is also included;

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A multi-node SRIO communication design method based on ZYNQ is characterized by comprising the following steps:

s3: the PS receives and transmits data;

2. The ZYNQ-based multi-node SRIO communication design method as claimed in claim 1, wherein the PS receives data: and sending the cache data to the FIFO hung on the DMA, and simultaneously using the PL to control the DMA controller to send the related data to the DDR3 of the PS.

3. The ZYNQ-based multi-node SRIO communication design method as claimed in claim 1, wherein the PS sends data: the PL controls DMA according to the address and length of the data fetch to be transmitted, reads the data into the PL FIFO, and transmits it.

4. The ZYNQ-based multi-node SRIO communication design method as claimed in claim 1, wherein the protocol type of the data obtained by PL processing response and request protocol packet includes: doorbell, Message, and DIO, where DIO includes Nwrite and Nread.

5. The ZYNQ-based multi-node SRIO communication design method as claimed in claim 1, wherein when the queue space is full, a data full flag is given, and a packet header that the data cannot be received is fed back through a bottom layer protocol packet, so that the data is no longer received.

6. The ZYNQ-based multi-node SRIO communication design method as claimed in claim 1, wherein the plurality of data query registers include: source ID, Doorbell data, address of Nwrite write DDR3, write length, and mailbox number.

7. The ZYNQ-based multi-node SRIO communication design method as claimed in claim 1, wherein the types of the PS receiving data include: PL passively receives Nwrite, PL passively receives Message, and PS actively calls Nread.

8. The ZYNQ-based multi-node SRIO communication design method as claimed in claim 1, wherein the type of PS sending data comprises: the PL passively sends Nread, PS active Call Message, and PS active Call Nwrite.

9. A multi-node SRIO communication device based on ZYNQ is characterized by comprising a Serial RapidIO switch and a ZYNQ module;

10. The ZYNQ-based multi-node SRIO communication device of claim 9, further comprising a DDR3 module;

the PS module includes a function processing module, a DDR3 controller, and a PSDDR3 module.