CN101087256B - Message transmission method and system - Google Patents
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- CN101087256B CN101087256B CN2007101187814A CN200710118781A CN101087256B CN 101087256 B CN101087256 B CN 101087256B CN 2007101187814 A CN2007101187814 A CN 2007101187814A CN 200710118781 A CN200710118781 A CN 200710118781A CN 101087256 B CN101087256 B CN 101087256B
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Abstract
The invention discloses message transmitting method and system. The receiving EP processor distributes spare buffer for the sending EP processor, and the address of spare buffer is send to the sending EP processor; the sending message is written in corresponding buffer region by the sending EP processor, and inform the receiving EP processor that there is message, and the receiving EP processor fetches the message to process from said spare buffer. The invention makes that when the sending EP processor sends message, there is no need to get the address of spare buffer distributed by receiving EP processor via PCI-E memory Read, and it can send message according to the address of spare buffer sent by the receiving EP processor, and reduce the time to transmit message, and improve the transmission efficiency of message.
Description
Technical field
The present invention relates to technical field of data transmission, be specifically related to message transmitting method and system.
Background technology
High performance distribution router needs very high intercommunication bandwidth, based on peripheral component interconnect upgrading (PCI-E, Peripheral Components Interconnect Express) agreement can realize aggregating into a very high bandwidth by multilink, satisfies the communication requirement of high-performance router equipment.
Fig. 1 has provided the schematic diagram based on the distribution router of PCI-E agreement, as shown in Figure 1, distribution router mainly is made up of a main control card and polylith ply-yarn drill, connect by switching equipment between main control card and every ply-yarn drill, root device (RC on the main control card, Root Complex) processor is finished the configuration in distribution router whole system territory, end equipment (EP on the ply-yarn drill, EndPoint) processor is then finished the configuration of local domain, and data flow mainly occurs between the EP processor on the different ply-yarn drills.
Fig. 2 provide one typical on distribution router based on the transfer of data flow process figure of PCI-E agreement, as shown in Figure 2, its concrete steps are as follows:
Step 201:EP processor B is distributed the freebuf of some for the EP processor A, the address of all freebufs is placed among the buffering area FreeQ that safeguards into the EP processor A, and the initial condition of the buffering area PostQ that will safeguard for the EP processor A is changed to sky.
PostQ is used for indicating the EP processor A whether to write message to freebuf.
Step 202:EP processor A will be when the EP processor B sends message, reads (Memory read) operation by the PCI-E storage and reads the free buffer regional address that an EP processor B is distributed for the EP processor A from the FreeQ of EP processor B.
The EP processor A can learn in the following manner that the EP processor B is the address information of the FreeQ and the PostQ of self maintained, thereby according to this address information FreeQ is carried out PCI-E Memory read operation:
Mode one, the address information with FreeQ, the PostQ of EP processor B is configured on the EP processor A in advance.
Mode two, EP processor B are notified the EP processor A with the address information of FreeQ and PostQ, FreeQ that the EP processor A receives and preservation EP processor B is sent and the address information of PostQ.
Step 203:EP processor A takes out a free buffer regional address from FreeQ, write a message to the freebuf of this address correspondence.
Step 204:EP processor A is write the state that PostQ is upgraded in (Write) operation by PCI-E Memory, and writes by message of PCI-E MSI interrupt notification EP processor B.
Step 205:EP processor B receives interrupt notification, checks the PostQ of self in Interrupt Process, finds that the state of PostQ upgrades, and then defines new message and writes, and takes out message and handle from the corresponding buffering area of buffer zone address of FreeQ.
From above scheme as can be seen, when transmit leg EP processor A sends message at every turn, all need to go to read the free buffer regional address that recipient EP processor B is distributed for the EP processor A by PCI-E Memory read operation.Because PCI-E memory read is very time-consuming operation, transmit leg EP processor A must be waited for after the free buffer regional address is returned just can carry out next step operation, and this has just reduced message transmissions efficient.When especially crossing over a plurality of bridge sheet between transmit leg EP processor A and recipient EP processor B, the transmission delay of free buffer regional address is longer, thereby PCI-E Memory read operation is more obvious to the message transmissions Effect on Performance.
Summary of the invention
The invention provides message transmitting method and system, to improve message transmissions efficient.
Technical scheme of the present invention is achieved in that
A kind of message transmitting method comprises:
Receive the EP processor and be transmission EP processor distribution freebuf, and this freebuf address notification is arrived transmission EP processor;
Send the EP processor message to be sent is write in the described free buffer regional address corresponding buffer region, and notify reception EP processor to have message to write, reception EP processor takes out message and handles from the corresponding buffering area of described free buffer regional address.
Described reception EP processor further comprise before sending after the EP processor distribution freebuf, this buffer zone address notice is sent the EP processor: receive the EP processor and will write for the address of the freebuf that sends the EP processor distribution and receive in the buffer memory descriptor BD table, and be mode bit of each address setting in receiving the BD table, and the init state position is effective for indication;
Described reception EP processor sends the EP processor with this freebuf address notification and comprises: reception EP processor writes this free buffer regional address and corresponding mode bit respectively and sends among EP processor each BD for the transmission BD table of reception EP processor foundation.
Described transmission EP processor further comprises when writing message to be sent in the buffering area: it is invalid for indicating that transmission EP processor will send the BD table and receive state position corresponding with the address of described buffering area in the BD table;
Described reception EP processor takes out message and handles and comprise from buffering area: receive the EP processor detect receive the mode bit that buffer zone address is arranged in the BD table indicate invalid, then from the corresponding buffering area of this buffer zone address, take out message and handle, and will receive the BD table and send the state position of the address correspondence of this buffering area in the BD table effective for indication.
Described transmission EP processor notice receive the EP processor have message write after, described receptions EP processor further comprised take out message from the corresponding buffering area of free buffer regional address before: reception EP processor is received this notice, detecting to receive has the indication of the mode bit of buffer zone address invalid in the BD table, then this buffer zone address is taken out from receive the BD table, simultaneously from local buffer pond application freebuf;
And, when receiving the application of EP processor to freebuf, the address of this freebuf write receive the BD table and send in the BD table, among the BD corresponding, and receive the BD table and send that the mode bit among the BD is set to indicate effective described in the BD table with the buffer zone address that is taken out.
Transmission EP processor further comprises before writing message to be sent in the buffering area: send the EP processor and start timer;
And transmission EP processor further comprises after writing message to be sent in the buffering area: send the EP processor and judge whether timer is overtime, if notice receives the EP processor has message to write; Otherwise the buffer zone address corresponding buffer region that continues the next BD in sending the BD table writes message.
A kind of message transfer system comprises: receives the EP processor and sends the EP processor, wherein:
Receive the EP processor, for sending EP processor distribution freebuf, this freebuf address notification is sent the EP processor, receive and send the message that the EP processor sends and write notice, from handling for taking out message the freebuf that sends the EP processor distribution;
Send the EP processor, message to be sent is write receive the EP processor, and write notice to receiving EP processor transmission message in the free buffer regional address corresponding buffer region of self distributing.
Described transmission EP processor comprises:
Send the BD table and set up module, set up transmission BD table for receiving the EP processor, this sends BD table storage reception EP processor for sending the free buffer regional address of EP processor distribution;
The message sending module, determine and to send message to receiving the EP processor, send the startup indication to timer module, from being taking-up free buffer regional address the transmission BD table that receives the foundation of EP processor, message to be sent is write in this free buffer regional address corresponding buffer region, when receiving the overtime indication that timer module is sent, stop to write message, and write notice to receiving EP processor transmission message to buffering area;
Timer module after receiving the startup indication that the message sending module sends, starts timer, when timer expiry, sends overtime indication to the message sending module.
A kind of EP processor comprises:
The buffer memory distribution module is transmission EP processor distribution freebuf, and this freebuf address notification is sent the EP processor;
Message processing module (MPM) receives and sends the message that the EP processor sends and write notice, from handling for taking out message the freebuf that sends the EP processor distribution.
This EP processor further comprises: buffer memory is returned module, and take out message from for the freebuf that sends the EP processor distribution after, the address notification transmission EP processor with this buffering area can write message to the corresponding buffering area of this buffer zone address with indication.
This EP processor further comprises: buffer memory application module, be used for receive send message that the EP processor sends and write notice after, to local buffer pond application freebuf, the address notification of the freebuf applied for is sent the EP processor, can write message to the corresponding buffering area of this buffer zone address with indication.
Compared with prior art, the present invention is by receiving the EP processor after being to send EP processor distribution freebuf, initiatively the address notification with freebuf sends the EP processor, make and send the EP processor at every turn when sending message, need not to operate to obtain to receive the free buffer regional address of EP processor for self distribution by PCI-E memory Read, and can be directly according to receiving the free buffer regional address transmission message that the EP processor is sent, significantly reduce the message transmissions duration, improved message transmissions efficient.
Description of drawings
Fig. 1 is the schematic diagram based on the distribution router of PCI-E agreement;
Fig. 2 is based on the message transmissions flow chart of PCI-E agreement on the existing distributed router;
On the distribution router that Fig. 3 provides for the embodiment of the invention one based on the message transmissions flow chart of PCI-E agreement;
On the distribution router that Fig. 4 provides for the embodiment of the invention two based on the message transmissions flow chart of PCI-E agreement;
Initialization procedure schematic diagram in the message transmissions flow process that Fig. 5-1 provides for the embodiment of the invention one;
Message process of transmitting schematic diagram in the message transmissions flow process that Fig. 5-2 provides for the embodiment of the invention one;
Message in the message transmissions flow process that Fig. 5-3 provides for the embodiment of the invention one is handled and the free buffer regional address is upgraded schematic diagram;
On the distribution router that Fig. 6 provides for the embodiment of the invention based on the message transfer system composition diagram of PCI-E agreement.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Based on the transfer of data flow process figure of PCI-E agreement, as shown in Figure 3, its concrete steps are as follows on the distribution router that Fig. 3 provides for the embodiment of the invention one:
Step 301:EP processor B is set up for the EP processor A in advance and is received buffer memory descriptor (BD) table, preserve the address of EP processor B in each BD in this table for a freebuf of EP processor A distribution, and each address has a Valid mode bit, and, the EP processor B is provided with a read pointer for receiving the BD table, points to first BD that receives the BD table when this read pointer is initial.
The Valid mode bit is used to represent that whether existing buffer zone address corresponding buffer region message write, and is on duty when being " 1 ", represents that this buffering area does not have message to write; On duty when being " 0 ", represent that the existing message of this buffering area writes.
Step 302:EP processor A is set up for the EP processor B in advance and is sent the BD table, be used to preserve free buffer regional address and the corresponding Valid mode bit that the EP processor B is distributed for the EP processor A, the initial condition that sends the BD table is empty, and the EP processor A is provided with a write pointer for sending the BD table, points to first BD that sends the BD table when this write pointer is initial.
In the transmission BD table that the content update that step 303:EP processor B will receive BD table is safeguarded for the EP processor B to the EP processor A, that is: will receive free buffer regional address among each BD of BD table and Valid mode bit and write respectively and send among each BD that BD shows.
The EP processor B can be learnt the address information of the transmission BD table of EP processor A in the following manner:
Mode one, the address information that will send BD table in advance are configured on the EP processor B.
Mode two, EP processor A will send the address information notice EP processor B of BD table, and the EP processor B receives and the address information of the transmission BD table that preservation EP processor A is sent.
Step 304:EP processor A is determined and will be sent a message to the EP processor B, is " 0 " with the Valid state position among the BD of write pointed in the transmission BD table, writes to represent the existing message of the corresponding buffering area of buffer zone address among this BD; And write message in the buffer zone address corresponding buffer region in the BD of write pointed, with the next BD of write pointed.
In the reception BD table that step 305:EP processor A is set up the EP processor B for the EP processor A by PCI-E Memory Write operation, the Valid mode bit that writes the buffer zone address of message is updated to " 0 ", and writes by message of PCI-E MSI interrupt notification EP processor B.
The EP processor A can be learnt the address information of the reception BD table of EP processor B in the following manner:
Mode one, the address information that will receive BD table in advance are configured on the EP processor A.
Mode two, EP processor B will receive the address information notice EP processor A of BD table, and the EP processor A receives and the address information of the reception BD table that preservation EP processor B is sent.
Step 306:EP processor B receives interruption, in Interrupt Process, check the reception BD table of self, Valid mode bit among the BD of discovery read pointed is " 0 ", the message that then takes out in the buffer zone address corresponding buffer region among this BD is handled, and be " 1 " with the Valid state position among this BD, to represent that the corresponding buffering area of buffer zone address among this BD can write message, with the next BD of read pointed; Simultaneously, the EP processor B is " 1 " with the Valid state position of this buffer zone address in the transmission BD table of EP processor A.
In order to accelerate message transmissions speed, step 306 also can following steps be replaced:
Step 306-1:EP processor B receives PCI-E MSI and interrupts, and directly the buffer zone address among the BD of read pointed is taken out, and write down this buffer zone address, simultaneously, again to freebuf of local buffer pond application.
Step 306-2:EP processor B judges whether to apply for successfully, if, execution in step 306-3; Otherwise, execution in step 306-4.
The BD of the read pointed that receives the BD table is put in the address of the freebuf that step 306-3:EP processor B will be applied for, and be " 1 " with the Valid state position of the BD of read pointed, simultaneously with read pointed next one BD; And the address of this freebuf is written in the transmission BD table of EP processor A, among the BD at the buffer zone address place of in step 306-1, being write down, and be " 1 " with the Valid state position among this BD; And the EP processor B is put into the local buffer pond with the address of this buffering area after message is taken out from buffering area, and this flow process finishes.
Step 306-4:EP processor B is with the packet loss in the corresponding buffering area of buffer zone address that is taken out.
Embodiment illustrated in fig. 3 what provide is the situation that the EP processor A only sends a message at every turn, and in actual applications, the EP processor A also can send more than one message at every turn.
The flow chart of the message transmissions that Fig. 4 provides for the embodiment of the invention two, as shown in Figure 4, its concrete steps are as follows:
Step 401～403 are identical with step 301～303.
Step 404:EP processor A is determined and will be sent message to the EP processor B, starts timer.
The timing length of timer equals the product that writes the duration that a message expends that predefined each writeable message number and statistics obtain.
The Valid state position that step 405:EP processor A will send among the BD of write pointed in the BD table is " 0 "; Write a message in the buffer zone address corresponding buffer region in the BD of write pointed then, and with the next BD of write pointed.
The Valid mode bit that writes the buffer zone address correspondence of message is updated to " 0 " in the reception BD table that step 406:EP processor A is set up the EP processor B for the EP processor A by PCI-E Memory Write operation.
Step 407:EP processor A judges whether timer is overtime, if, execution in step 408; Otherwise, return step 405, to carry out the processing that writes of next message.
Step 408:EP processor A has message to write by PCI-E MSI interrupt notification EP processor B.
Step 409:EP processor B receives interruption, checks the reception BD table of self in Interrupt Process.
Step 410:EP processor B judges whether the Valid mode bit among the BD of read pointed is " 0 ", if, execution in step 411; Otherwise this flow process finishes.
The message that step 411:EP processor B is taken out in the buffer zone address corresponding buffer region among the BD of read pointed is handled, and be " 1 " with the Valid state position among this BD, with read pointed next one BD; Simultaneously, the EP processor B is " 1 " with the Valid state position of this buffer zone address in the transmission BD table of EP processor A, returns step 410.
Fig. 5-1,5-2,5-3 have provided one respectively and have used the schematic diagram that the embodiment of the invention one is carried out message transmissions.
Wherein, what Fig. 5-1 provided is initialization procedure, shown in Fig. 5-1, the EP processor B for the freebuf that the EP processor A distributes is: buffering area 0-255, the address information of having stored buffering area 0-255 among each BD of the reception BD table of EP processor, the Valid mode bit of each buffer zone address all is changed to " 1 " simultaneously, does not also have message to write in this buffering area with expression; The EP processor will receive the content of each BD in the BD table: the address information of each buffering area and Valid mode bit all are written among each BD of transmission BD table of EP processor A.
What Fig. 5-2 provided is the EP processor A sends process from message to the EP processor B, shown in Fig. 5-2,1. the EP processor A reads the buffer zone address among the BD that sends write pointed in the BD table by the step among the figure, and write message to this address corresponding buffer region, and be " 0 " with the Valid state position among this BD, with the next BD of write pointed; Then by the step among the figure 2.: the Valid state position that will receive the buffer zone address that writes message in the BD table is " 0 ", 3. sends a PCI-E MSI to the EP processor B by the step among the figure simultaneously and interrupts, and has message to write with notice EP processor B.
What Fig. 5-3 provided is EP processor B processing message and the process of upgrading the free buffer regional address, shown in Fig. 5-3, the EP processor B receives the interruption that the EP processor A is sent, 4. read the Valid mode bit among the BD that receives read pointed in the BD table by the step among the figure, find that this Valid mode bit is " 0 ", then defines message to write; 5. from receive the BD table, take out buffer zone address among the BD of read pointed by the step among the figure then, write down this buffer zone address, then from freebuf X of local buffer pond application, the address of this freebuf X is put into the BD of read pointed, and be " 1 " with the Valid state position of this BD, simultaneously with the next BD of read pointed; 6. the address of freebuf X of application is written among the BD at the buffer zone address place of being write down that sends the BD table by the step among the figure then, and is " 1 " the Valid state position of this BD.
The message transfer system that Fig. 6 provides for the embodiment of the invention, as shown in Figure 6, this system mainly comprises: receive EP processor 61 and send EP processor 62, wherein:
Receive EP processor 61: distribute freebuf for sending EP processor 62, the address notification of this freebuf is sent EP processor 62, receive and send the message that EP processor 62 sends and write notice, from taking out message the freebuf that EP processor 62 distributes and handle for sending.
Send EP processor 62: message to be sent is write receive EP processor 61, and write notice to receiving EP processor 61 transmission messages in the free buffer regional address corresponding buffer region of self distributing.
As shown in Figure 6, receive EP processor 61 and mainly comprise: buffer memory distribution module 611, message processing module (MPM) 612 and buffer memory are returned module 613, wherein:
Buffer memory distribution module 611: set up reception BD table for sending EP processor 62 in advance, the address information of this reception BD table is sent to message processing module (MPM) 612 and buffer memory is returned module 613, save as the address of a freebuf that sends 62 distribution of EP processor in each BD in this table, and each address has a Valid mode bit, and be to receive the BD table read pointer is set, point to receive first BD of BD table when this read pointer is initial, and the content update that will receive the BD table is to sending EP processor 62 for during the transmission BD that receives the EP processor and safeguard shows.
Message processing module (MPM) 612: the address information that the reception EP processor 61 that reception and preservation buffer memory distribution module 611 are sent is shown for the reception BD that sends 62 foundation of EP processor, receive and send the interruption that EP processor 62 is sent, address information according to described reception BD table finds reception BD table, check that in Interrupt Process this receives the BD table, Valid mode bit among the BD of discovery read pointed is " 0 ", the message that then takes out in the buffer zone address corresponding buffer region among this BD is handled, and returns module 613 transmissions to buffer memory and return indication.
Buffer memory is returned module 613: the address information that the reception EP processor 61 that reception and preservation buffer memory distribution module 611 are sent is shown for the reception BD that sends 62 foundation of EP processor, receive the indication of returning that message processing module (MPM) 612 sends, address information according to described reception BD table finds reception BD table, with the Valid state position among the BD of read pointed in this reception BD table is " 1 ", to represent that the corresponding buffering area of buffer zone address among this BD can write message, with the next BD of read pointed; Simultaneously, with send in the transmission BD table of EP processor 62, the described Valid state position of having returned the address of buffering area is " 1 ".
In actual applications, buffer memory is returned module 613 and also can be replaced by buffer memory application module, buffer memory application module is used for after receiving the application indication of carrying read pointer buffer zone address pointed that message processing module (MPM) is sent, to freebuf of local buffer pond application, judge whether to apply for successfully, if success, the address of the freebuf applied for is put into the BD of the read pointed that receives the BD table, and be " 1 " with the Valid state position of the BD of read pointed, simultaneously with the next BD of read pointed; And be written to the address of this freebuf in the transmission BD table that sends EP processor 62, among the BD at buffer zone address place that the application indication is carried, and be " 1 " with the Valid state position among this BD; If unsuccessful, then with the packet loss in the corresponding buffering area of buffer zone address that is taken out.
Simultaneously, the functionality change of message processing module (MPM) is: receive send that EP processor 62 sends in have no progeny, directly the buffer zone address among the BD of read pointed is taken out, send the application indication of the buffer zone address that carries this taking-up simultaneously to buffer memory application module, from the corresponding buffering area of buffer zone address of described taking-up, take out message then and handle, the corresponding buffering area of buffer zone address of described taking-up is put in the local buffer pond.
As shown in Figure 6, send EP processor 62 and mainly comprise: send the BD table and set up module 621 and message sending module 622, wherein:
Send the BD table and set up module 621: be used to receive EP processor 61 foundation transmission BD tables, be used to store and receive EP processor 61 for sending the free buffer regional address that EP processor 62 distributes, the address information of this transmission BD table is sent to message sending module 622, and, point to first BD that sends the BD table when this write pointer is initial for this transmission BD table is provided with a write pointer.
Message sending module 622: receive to send the BD table and set up transmission EP processor 62 that module 621 sends address information for the transmission BD table that receives EP processor 61 and distribute, determine and to send message to receiving EP processor 61, address information according to described transmission BD table finds transmission BD table, send the BD table from this, take out the free buffer regional address among the BD of write pointed, message to be sent is write in this free buffer regional address corresponding buffer region, and be " 0 " with the Valid state position among this BD, and, whenever write a message write pointer is moved down a BD, message writes and finishes, and receiving EP processor 61 by PCI-E MSI interrupt notification has message to write.
In actual applications, send EP processor 62 and also can comprise: timer module 623, be used for after receiving the startup indication that message sending module 62 sends, starting timer, when timer expiry, send overtime indication to message sending module 622.
And, message sending module 622 is further used for, in that determine will be when receiving EP processor 61 and send messages, send the startup indication to timer module 623, after receiving the overtime indication that timer module 623 is sent, stop to write message, and have message to write by PCI-E MSI interrupt notification reception EP processor 61 to buffering area.
The above only is process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a message transmitting method is characterized in that, comprising:
Receiving device EP processor is for sending EP processor distribution freebuf; Sending the EP processor is that receiving device EP processor is set up transmission buffer memory descriptor BD table in advance, and for sending the BD table write pointer is set, and sensing sent first BD of BD table when this write pointer was initial; Receiving device EP processor will write for the free buffer regional address that sends the EP processor distribution among each BD of the transmission BD table that sends the foundation of EP processor;
Send in the free buffer regional address corresponding buffer region in the transmission BD table that the EP processor writes message to be sent write pointers point, write pointers point is sent the next BD of BD table, and notify receiving device EP processor to have message to write, receiving device EP processor takes out message and handles from the corresponding buffering area of described free buffer regional address.
2. the method for claim 1, it is characterized in that, described receiving device EP processor further comprised before sending after the EP processor distribution freebuf, this buffer zone address notice is sent the EP processor: receiving device EP processor will write for the address of the freebuf that sends the EP processor distribution and receive in the buffer memory descriptor BD table, and be mode bit of each address setting in receiving buffer memory descriptor BD table, and the init state position is effective for indication;
Described receiving device EP processor will write for the free buffer regional address that sends the EP processor distribution among each BD that sends the transmission BD table that the EP processor sets up and comprise: receiving device EP processor writes this free buffer regional address and corresponding mode bit respectively and sends among each BD that the EP processor is the transmission BD table set up of receiving device EP processor.
3. method as claimed in claim 2, it is characterized in that described transmission EP processor further comprises when message to be sent being write in the free buffer regional address corresponding buffer region in the transmission BD table of write pointers point: send the EP processor will send the BD table and receive state position corresponding in the buffer memory descriptor BD table with the address of described buffering area invalid for indicating;
Described receiving device EP processor takes out message and handles and comprise from buffering area: receiving device EP processor detects to receive has the mode bit indication of buffer zone address invalid in the buffer memory descriptor BD table, then from the corresponding buffering area of this buffer zone address, take out message and handle, and will receive buffer memory descriptor BD table and send the state position of the address correspondence of this buffering area in the BD table effective for indication.
4. method as claimed in claim 2, it is characterized in that, described transmission EP processor notice receiving device EP processor have message write after, described receiving device EP processor further comprised take out message from the corresponding buffering area of free buffer regional address before: receiving device EP processor is received this notice, detecting to receive has the mode bit indication of buffer zone address invalid in the buffer memory descriptor BD table, then this buffer zone address is taken out from receive buffer memory descriptor BD table, simultaneously from local buffer pond application freebuf;
And, when freebuf is arrived in the application of receiving device EP processor, the address of this freebuf write receive buffer memory descriptor BD table and send among the BD corresponding in the BD table, and receives buffer memory descriptor BD table and send the mode bit among the BD described in the BD table that to be set to indication effective with the buffer zone address that is taken out.
5. the method for claim 1 is characterized in that,
Described transmission EP processor further comprises before message to be sent being write in the free buffer regional address corresponding buffer region in the transmission BD table of write pointers point: send the EP processor and start timer;
And, described transmission EP processor further comprises after message to be sent being write in the free buffer regional address corresponding buffer region in the transmission BD table of write pointers point: send the EP processor and judge whether timer is overtime, if notice receiving device EP processor has message to write; Otherwise the buffer zone address corresponding buffer region that continues the next BD in sending the BD table writes message.
6. a message transfer system is characterized in that, comprising: receive the EP processor and send the EP processor, wherein:
Receive the EP processor, for sending EP processor distribution freebuf, to write for the free buffer regional address that sends the EP processor distribution among each BD of the transmission BD table that sends the foundation of EP processor, receive and send the message that the EP processor sends and write notice, from handling for taking out message the freebuf that sends the EP processor distribution;
Send the EP processor, set up transmission BD table for receiving the EP processor in advance, and for sending the BD table write pointer is set, sensing sent first BD of BD table when this write pointer was initial; Message to be sent is write in the free buffer regional address corresponding buffer region in the transmission BD table of write pointers point, write pointers point is sent the next BD of BD table, and send message and write notice to receiving the EP processor.
7. system as claimed in claim 6 is characterized in that, described transmission EP processor comprises:
Send the BD table and set up module, set up transmission BD table for receiving the EP processor, this sends BD table storage reception EP processor is the free buffer regional address that sends the EP processor distribution, and shows a write pointer is set for sending BD, and sensing sent first BD of BD table when this write pointer was initial;
The message sending module, determine and to send message to receiving the EP processor, send the startup indication to timer module, from for receiving the transmission BD table that the EP processor sets up, taking out the free buffer regional address among the BD of write pointers point, message to be sent is write in this free buffer regional address corresponding buffer region, and write pointer is moved down a BD; When receiving the overtime indication that timer module is sent, stop to write message, and write notice to receiving EP processor transmission message to buffering area;
Timer module after receiving the startup indication that the message sending module sends, starts timer, when timer expiry, sends overtime indication to the message sending module.
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| CN2007101187814A CN101087256B (en) | 2007-07-13 | 2007-07-13 | Message transmission method and system |
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| CN2007101187814A CN101087256B (en) | 2007-07-13 | 2007-07-13 | Message transmission method and system |
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| CN101355523B (en) * | 2008-09-26 | 2010-12-08 | 福建星网锐捷网络有限公司 | Control method and system for data transmission |
| CN102594708A (en) * | 2012-03-22 | 2012-07-18 | 北京星网锐捷网络技术有限公司 | Flow control method and device, line cards and distributed network equipment |
| CN103389950B (en) * | 2013-07-15 | 2015-03-04 | 武汉中元华电科技股份有限公司 | Anti-jamming multichannel data transmission method based on capacity prediction |
| CN104468404B (en) * | 2014-11-07 | 2017-08-29 | 迈普通信技术股份有限公司 | A kind of buffer configuration method and device |
| CN108021438A (en) * | 2016-10-31 | 2018-05-11 | 联芯科技有限公司 | A kind of internal memory sharing method and the terminal device based on multiprocessor |
| CN109697022B (en) * | 2017-10-23 | 2022-03-04 | 深圳市中兴微电子技术有限公司 | Method and device for processing message descriptor PD and computer readable storage medium |
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