CN101355523B - Control method and system for data transmission - Google Patents
Control method and system for data transmission Download PDFInfo
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- CN101355523B CN101355523B CN2008102233655A CN200810223365A CN101355523B CN 101355523 B CN101355523 B CN 101355523B CN 2008102233655 A CN2008102233655 A CN 2008102233655A CN 200810223365 A CN200810223365 A CN 200810223365A CN 101355523 B CN101355523 B CN 101355523B
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Abstract
The invention provides a method and a system for controlling data transmission, which are used for solving the problem that the load is large when a CPU receives and transmits serial data. The method comprises the following steps that the CPU generates first notification information which is appointed by the CPU and provided with a writable CPU memory space; and a transmitting device writes target data from a data storage device into the CPU memory space according to the first notification information. According to the technical proposal of the embodiment of the invention, the read/write operation of the CPU memory is completed by an external device of the CPU which is only required to provide corresponding control information, thereby reducing the load of the CPU when the CPU receives and transmits the serial data.
Description
Technical field
The present invention relates to computer technology, relate to a kind of data transfer control method and system especially.
Background technology
The transmitting-receiving of serial data of the prior art is controlled by central processor CPU (Center Process Unit).As shown in Figure 1, when CPU1 passed through interface arrangement 3 from data storage device 2 reception data, interface arrangement 3 received the data from data storage device 2 earlier, then by interrupt signal notice CPU1; After CPU1 received interrupt signal, by bus interface, for example peripheral element extension interface PCI (PedpherdComponent Interconnect) read data from interface arrangement 3.When CPU1 passed through transmitting device 3 from data storage device 2 transmission data, CPU write interface arrangement 3 by pci interface with data, and interface arrangement 3 sends data by serial data mouth (abbreviation serial ports) to data storage device 2.
In aforesaid way, the data transmit-receive process need take cpu resource, causes system effectiveness to reduce.Specifically, CPU reads the data of a byte at every turn, just need carry out a PCI read operation, and is same, writes a byte at every turn, also needs to carry out the PCI write operation one time.PCI read-write operation in the different system is consuming time not to be waited, and in the system of multistage bridge was arranged, a read operation is consuming time can to reach 1 microsecond; Write operation consuming time about 0.2 microsecond.Be that practical operation speed is 1 byte/1.2 microseconds.If the speed of serial ports is 115200 bps, i.e. 14400 byte per seconds are 14400 * 1.2 microseconds=17280 microseconds to the processing time that the action need of data in the serial ports 1 second takies CPU then, and promptly 0.017280 second, the occupancy of CPU was 1.7%.If CPU connects a plurality of serial port chip by PCI, cpu busy percentage rises thereupon.For example in the modular router, may connect a plurality of serial port boards, each serial port board has a plurality of serial ports again.In a route system that 32 serial ports are arranged, CPU promptly rises to 32 * 1.7%=54% to the shared time of the read-write operation of serial ports, takies the over half of cpu performance, and the load of CPU is bigger.Therefore need a kind of method effectively to reduce the load of CPU when the transmitting-receiving serial data.
Summary of the invention
In view of this, the embodiment of the invention provides data transfer control method and system, the load when being used to reduce CPU transmitting-receiving serial data.
A kind of data transfer control method in the embodiment of the invention is applied to comprise comprise the system of central processor CPU, data storage device and transmitting device:
A, CPU generate the data transmit-receive record, described data transmit-receive record comprises two above clauses and subclauses and arranges in order, first announcement information that the CPU memory headroom of the CPU appointment of every entry record CPU generation can be write, and the memory location of last item entry record first term clauses and subclauses, the memory location of next clauses and subclauses of non-these clauses and subclauses of last item entry record; Described first announcement information comprises: first controlled flag that the CPU memory headroom of the address of CPU memory headroom and this address of sign can be write;
The target data that B, transmitting device will come from data storage device according to described first announcement information writes described CPU memory headroom, comprise: b1, transmitting device are judged if comprise first controlled flag in the clauses and subclauses of data transmit-receive record, are confirmed that then the CPU memory headroom of the address correspondence in the current clauses and subclauses can be write; B2, transmitting device receive and preserve the target data that comes from data storage device, according to described address described target data are write the CPU internal memory then.
Another data transfer control method in the embodiment of the invention is applied to comprise comprise the system of central processor CPU, data storage device and transmitting device:
A, CPU deposit target data in the CPU internal memory and generate the second readable announcement information of described target data place CPU memory headroom, comprise: CPU generates the data transmit-receive record, described data transmit-receive record comprises two above clauses and subclauses and arranges in order, every described second announcement information of entry record, and the memory location of last item entry record first term clauses and subclauses, the memory location of next clauses and subclauses of non-these clauses and subclauses of last item entry record; Described second announcement information comprises: store the address of the CPU memory headroom of target data, the length of target data and the 3rd readable controlled flag of CPU memory headroom that indicates this address;
B, transmitting device read described target data according to described second announcement information from the CPU internal memory, comprise: step b1, transmitting device are judged if comprise the 3rd controlled flag in the clauses and subclauses of data transmit-receive record, are confirmed that then the CPU memory headroom of the address correspondence in the current clauses and subclauses is readable; Step b2, transmitting device read described target data according to the length of address in the described current clauses and subclauses and target data from the CPU internal memory;
C, transmitting device send described target data to data storage device.
A kind of data transfer control system in the embodiment of the invention is used for the transfer of data between Controlled CPU and the data storage device, comprises CPU and transmitting device, wherein,
Described CPU is used to generate first announcement information that the CPU memory headroom of CPU appointment can be write;
Described transmitting device is used for writing described CPU memory headroom according to the target data that described first announcement information will come from data storage device;
Described CPU comprises acquisition module and generation module, and described transmitting device comprises memory module, first judge module and write operation module, wherein,
Described acquisition module is used to obtain the address of the CPU memory headroom of CPU appointment;
Described generation module is used to generate first controlled flag that the described CPU memory headroom of sign can be write;
Described memory module is used to receive and preserve the target data that comes from data storage device;
Described first judge module is used for judging according to described first controlled flag whether described CPU memory headroom can be write;
Described write operation module is used for if described CPU memory headroom can be write, and then the target data that will come from data storage device according to described address writes the CPU internal memory.
Another data transfer control system in the embodiment of the invention is used for the transfer of data between Controlled CPU and the data storage device, comprises CPU and transmitting device, wherein,
Described CPU is used for depositing target data in the CPU internal memory and generating the second readable announcement information of described target data place CPU memory headroom;
Described transmitting device is used for reading described target data and sending to data storage device from the CPU internal memory according to described second announcement information;
Described CPU comprises writing module, acquisition module and generation module, and described transmitting device comprises first judge module, read operation module, memory module and sending module, wherein,
The said write module is used for target data is write the CPU internal memory;
Described acquisition module is used to obtain the address of the CPU memory headroom of CPU appointment;
Described generation module is used to generate the 3rd readable controlled flag of the described CPU memory headroom of sign;
Described first judge module is used for judging according to described the 3rd controlled flag whether described CPU memory headroom is readable;
Described read operation module is used for if described CPU memory headroom is readable, and then the length according to described address and target data reads described target data from the CPU internal memory;
Described memory module is used to preserve the target data that the read operation module is read;
Described sending module is used for the data of memory module are sent to data storage device.
Technical scheme according to the embodiment of the invention, when data are transferred to CPU from the data storage device of CPU outside, write operation to the CPU internal memory is finished by the device of CPU outside, when data when CPU transfers to the data storage device of CPU outside, read operation to the CPU internal memory is also finished by the device of CPU outside, CPU provides corresponding control information in said process, the data interaction of CPU and external data storage device need not CPU and operates in person, thereby has reduced the load when CPU receives and dispatches serial data.
Description of drawings
Fig. 1 is the receive-transmit system schematic diagram of serial data of the prior art;
Fig. 2 is the method step of inventive embodiments;
Fig. 3 is the receive-transmit system schematic diagram of the serial data in the embodiment of the invention;
Fig. 4 is a serial ports transceiver controller internal structure schematic diagram;
Fig. 5 A is a serial ports receiver module internal structure schematic diagram;
Fig. 5 B is a serial ports sending module internal structure schematic diagram;
Fig. 6 A is for writing the flow chart of data to the internal memory of CPU;
Fig. 6 B is the flow chart from the internal memory sense data of CPU;
Fig. 7 is a kind of structural representation of data transfer control system in the embodiment of the invention;
Fig. 8 is the another kind of structural representation of data transfer control system in the embodiment of the invention.
Embodiment
Load when receiving and dispatching serial data in order to reduce CPU, in embodiments of the present invention, CPU generates Data Transmission Controlling information and is kept in the data transmit-receive record, and transmitting device carries out read/write operation according to the Data Transmission Controlling information in the data transmit-receive record to the CPU internal memory.Specifically comprise following steps as shown in Figure 2:
Step 21:CPU generates Data Transmission Controlling information.Be specially CPU and specify that self one section memory headroom is readable maybe can be write, and generate announcement information.Comprise the information representation mode of CPU and transmitting device agreement in the announcement information, for example comprise a kind of controlled flag, transmitting device is according to this controlled flag, learns that the CPU memory headroom of CPU appointment is readable maybe can write.And, when transmitting device when the CPU internal memory writes data, also comprise the address of CPU internal memory in the announcement information, when transmitting device from the CPU internal memory during sense data, comprise the address of CPU internal memory in the announcement information and the length of the data that need read.
The announcement information that CPU generates can be directly to be sent to data transmission device, also can be stored in certain device in the system, for example is stored in CPU inside, obtains this announcement information by transmitting device.
Step 22: transmitting device carries out read/write operation according to the announcement information that CPU generates to the CPU internal memory.Be specially, when transmitting device when the CPU internal memory writes data, according to the address in the data transmit-receive record data are write in the CPU internal memory, setting according to CPU, can be data to be write the CPU memory headroom from this address, or determine one section CPU memory headroom by the neighborhood of this address, again data are write this section CPU memory headroom; When transmitting device during sense data, according to address and the data packet length in the data transmit-receive record, is read the data of this length from this address from the CPU internal memory.
The method and apparatus that the embodiment of the invention is provided elaborates below.Earlier in conjunction with a kind of device implementation in Fig. 3-5B explanation embodiment of the invention, further specify data transfer control method in the embodiment of the invention in conjunction with this device then.
Transmitting device when providing a kind of serial data mouth (abbreviation serial ports) transceive data in the embodiment of the invention, serial ports transceiver controller 30 as shown in Figure 3, it has replaced the interface arrangement 3 among Fig. 1 as can be seen.The function of serial ports transceiver controller 30 is according to the Data Transmission Controlling information in the data transmit-receive record, the read/write operation that the internal memory of CPU is carried out.Fig. 4 shows a kind of internal structure of serial ports transceiver controller 30, comprising: serial ports receiver module 31, and serial ports sending module 32, internal bus moderator 33 and pci interface 34, they are connected respectively on the internal bus, as shown in FIG..
Serial ports receiver module 31 is used for CPU1 and receives serial data from data storage device 2, serial ports sending module 32 is used for CPU1 and sends serial data to data storage device 2, and internal bus moderator 33 is used to control serial ports receiver module or serial ports sending module taking internal bus.Pci interface 34 is used to realize the standard interface of PCI agreement.Serial ports receiver module 31, internal bus moderator 33 and pci interface 34 are used for CPU internal memory write operation as can be seen, and serial ports sending module 32, internal bus moderator 33 and pci interface 34 are used for the read operation of CPU internal memory.
Fig. 5 A shows a kind of internal structure of serial ports receiver module 31, comprising: serial ports receiving interface 311, and serial ports receives buffer memory 312, and PCI receives controller 313.Serial ports receiving interface 311 and serial ports receive buffer memory 312 interconnection, and PCI receives controller 313 and serial ports reception buffer memory 312 is connected on the internal bus.
Serial ports receiving interface 311 receives serial data from data storage device 2, deposits data in serial ports and receives buffer memory 312.PCI receives controller 313 and is used for autopolling reception block descriptor BD (BlockDescription) table, the application internal bus, and control data sends address and length.Use when serial ports receives data to receive the BD table, illustrated hereinafter about the BD table.
Fig. 5 B shows a kind of internal structure of serial ports sending module 32, comprising: serial ports transmission interface 321, serial ports sends buffer memory 322, PCI transmit control device 323.Serial ports transmission interface 321 and serial ports send buffer memory 322 interconnection, and PCI transmit control device 323 and serial ports send buffer memory 322 and be connected on the internal bus.
Serial ports transmission interface 321 is used for sending the data that are stored in serial ports transmission buffer memory to data storage device 2.Serial ports sends buffer memory 322 and is used to store the data that receive on the pci bus.PCI transmit control device 323 is used for autopolling and sends the BD table, application internal bus, and control data receiver address and length.
Data transmit-receive record in the embodiment of the invention is the BD table, comprise Data Transmission Controlling information in the BD table, be used for the control of transfer of data between serial ports transceiver controller 30 and the CPU1, create initialized the time by CPU, be stored in the CPU1 internal memory or in other storage devices with the structure of circular linked list.If be stored among the CPU1, then CPU1 need arrange memory space to store the BD table.Being stored among the CPU1 with the BD table below is that example describes.The memory address of BD table is determined that by CPU1 serial ports transceiver controller 30 is from agreed address visit chained list.A BD table is made up of N clauses and subclauses of arranging in order.When visiting N clauses and subclauses of pointed of BD table, next pointer just points to the 1st clauses and subclauses, constitutes circular linked list thus.
When the data of data storage device 2 are written into the internal memory of CPU1,30 visits of serial ports transceiver controller receive the BD table, each clauses and subclauses that receives the BD table are stored in the memory module, and the content that comprises comprises controlled flag, data address pointer and next clauses and subclauses pointer at least.When reading the data of CPU1 internal memory, 30 visits of serial ports transceiver controller send the BD table, and each clauses and subclauses that sends the BD table are stored in the memory module, and the content that comprises comprises controlled flag, data address pointer, data length and next clauses and subclauses pointer at least.
The controlled flag that receives in the BD table comprises first controlled flag and second controlled flag, and the controlled flag that sends in the BD table comprises the 3rd controlled flag and the 4th controlled flag.Only store the two one in the BD table clause, first controlled flag and the 3rd controlled flag represent that its place clauses and subclauses should be by 30 controls of serial ports transceiver controller, that is to say when serial ports transceiver controller 30 these clauses and subclauses of visit, serial ports transceiver controller 30 carries out the data read/write operation according to the information in these clauses and subclauses, and does not carry out the corresponding operating at these clauses and subclauses when CPU1 visits these clauses and subclauses; Second controlled flag and the 4th controlled flag represent that its place clauses and subclauses should be controlled by CPU1, promptly carry out the corresponding operating to these clauses and subclauses when CPU1 visits these clauses and subclauses, and do not operate when serial ports transceiver controller 30 is visited these clauses and subclauses.When CPU created the BD table, the controlled flag of reception/transmission BD was first controlled flag.The operation of CPU1 or serial ports transceiver controller 30 is described below.
The data address pointer is the initial addresses of the pairing data of current BD clauses and subclauses in internal memory.Expression writes data from this start address the internal memory of CPU1 in receiving the BD table; Expression is from this start address in sending the BD table, is stored in data length in the same clauses and subclauses according to sending in the BD table with this start address, reads the data of this length from the internal memory of CPU1.
If BD table comprises N item clauses and subclauses, then next the clauses and subclauses pointer in the N item clauses and subclauses is used to indicate the memory address of the 1st clauses and subclauses, and next the clauses and subclauses pointer in all the other every clauses and subclauses is used to indicate the memory address of the next item down clauses and subclauses of these clauses and subclauses.For the data address pointer, need between adjacent two pointers, leave enough spaces with store data.Design or agreement according to application system are determined this space size, for example in the transfer of data based on IP (Internet Protocol) agreement, length of data package is 1518 bytes to the maximum, and then the interval between the data address pointer should be not less than 1518 bytes, for example is the 2K byte.
The BD table also can only comprise clauses and subclauses.An address in the entry record CPU internal memory of reception BD table, and write down first controlled flag or second controlled flag.Send in the entry record CPU internal memory of BD table address and from the length of data package of this address, and write down the 3rd controlled flag or the 4th controlled flag.
The following describes the workflow of serial ports transceiver controller 30, be divided into that internal memory to CPU1 writes the flow process of data and from the flow process of the internal memory sense data of CPU1.
After the CPU1 initialization, generate BD table and storage.In the clauses and subclauses of BD table at this moment, controlled flag is first controlled flag.When data storage device when CPU1 sends data, these data need write the internal memory of CPU1, this moment serial ports transceiver controller 30 workflow as shown in Figure 6A.
Step S61: serial ports transceiver controller 30 reads and receives the BD table.
Step S62: visit receives the clauses and subclauses of BD table, judges whether controlled flag is first controlled flag, if, change step S63 over to, otherwise repeating step S62.
Step S63: whether serial ports transceiver controller 30 interpretation serial ports receive buffer memory 312 data, if, change step S64 over to, otherwise repeating step S63.
Step S64: data are write the CPU1 internal memory.
Step S65: serial ports transceiver controller 30 is judged whether a complete packet sends and is finished, if change step S66 over to, otherwise change step S63 over to.
Step S66: serial ports transceiver controller 30 is revised the current clauses and subclauses that receive the BD table.
Step S67: serial ports transceiver controller 30 is determined the memory address of next clauses and subclauses according to next the clauses and subclauses pointer in the current clauses and subclauses, changes step S62 then over to.
What step S61-S67 provided is the workflow of serial ports transceiver controller 30, and wherein step S61-S65 has finished a write operation to CPU1.After step S65, be written to the data of CPU1 internal memory among the CPU1 read step S63-S65.In above-mentioned steps S62, when serial ports transceiver controller accesses entry 30 first time, the controlled flag of these clauses and subclauses is first controlled flag, this first controlled flag is provided with when generating the BD table by CPU1, by first controlled flag is set, realized sending the announcement information that shows that the CPU1 memory headroom can be write to serial ports transceiver controller 30.Last clauses and subclauses when serial ports transceiver controller 30 visit BD tables, then when first clauses and subclauses visited the BD table clause successively, if CPU1 does not also finish above-mentioned reading of data, control address in these clauses and subclauses still is second controlled flag so, and serial ports transceiver controller 30 needs repeating step S62 to wait at this moment.
In above-mentioned steps S64, before data write the CPU1 internal memory, PCI receives controller 313 application internal buss, receive buffer memory 312 by internal bus moderator 33 to serial ports and distribute internal buss, serial ports receives buffer memory 312 address of data by the data address pointer indication of internal bus from the current clauses and subclauses that receive the BD table that distribute is begun to write the CPU1 internal memory then.Current clauses and subclauses are the clauses and subclauses of visiting among the step S62.
Among the step S66, serial ports transceiver controller 30 is revised the current clauses and subclauses that receive the BD table, to realize that CPU1 is sent the readable announcement information of current BD table clause.Specifically be that PCI receives controller 313 original first controlled flag in the clauses and subclauses is revised as second controlled flag, and be written to the data packet length information of CPU1 internal memory among the obtaining step S63-S65 and be recorded in the clauses and subclauses.
CPU1 receives every clauses and subclauses of BD table by the time interval poll of setting, when the controlled flag in the clauses and subclauses of visit is second controlled flag, the CPU1 memory address that then from these clauses and subclauses, writes down, length has been read by CPU1 for the data of the data packet length that writes down in these clauses and subclauses, this moment, CPU1 was revised as first controlled flag with this second controlled flag, it specifically is the address that CPU1 writes down from the clauses and subclauses of visit, by data packet length reading of data from the CPU1 internal memory of writing down in the clauses and subclauses of visit, generate first controlled flag then and be stored in these clauses and subclauses of BD table.This clauses and subclauses place memory cell of BD table receives this first controlled flag, and deletes original second controlled flag.
If receive the BD table 1 clauses and subclauses is only arranged, then after step 66, after CPU1 reads the data of write memory, second controlled flag is revised as first controlled flag; And skips steps S67 after step S66 directly changes step S62 over to, and the clauses and subclauses of the reception BD table of the visit among the step S62 are the unique clauses and subclauses that receive the BD table.
After the CPU1 initialization, when from the internal memory sense data of CPU1, flow process is shown in Fig. 6 B.
Step S71: serial ports transceiver controller 30 reads and sends the BD table.
Step S72: visit sends the clauses and subclauses of BD table, judges whether controlled flag is the 3rd controlled flag, if, change step S73 over to, otherwise repeating step S72.
Step S73: whether serial ports transceiver controller 30 interpretation serial ports send buffer memory 322 and have living space, if, input step S74, otherwise repeating step S73.
Step S74: data are read from the CPU1 internal memory.
Step S75: serial ports transceiver controller 30 is judged whether a complete packet is read and is finished, if change step S76 over to, otherwise change step S73 over to.
Step S76: serial ports transceiver controller 30 is revised and is sent the BD table, and the 3rd controlled flag in the current clauses and subclauses is revised as the 4th controlled flag.
Step S77: serial ports transceiver controller 30 is determined the memory address of next clauses and subclauses according to next the clauses and subclauses pointer in the current clauses and subclauses, changes step S72 then over to.
Step S71-S75 has finished a read operation to CPU1, and serial ports sent in the buffer memory 322 and had complete packet this moment, and this packet will be sent to data storage device 2.In above-mentioned steps S74, before data are read from the CPU1 internal memory, PCI transmit control device 323 application internal buss, send buffer memory 322 by internal bus moderator 33 to serial ports and distribute internal bus, serial ports transmission buffer memory 322 begins also to store by internal bus sense data from the CPU1 internal memory of distributing according to the address of the data address pointer indication in the current clauses and subclauses of reception BD table then.Current clauses and subclauses are the clauses and subclauses of visiting among the step S72.Judge whether to read according to the data length that writes down in the current clauses and subclauses among the step S75 and finish.
Among the step S76, serial ports transceiver controller 30 is revised and is received the BD table, specifically is to send by PCI transmit control device 323 generation the 4th controlled flag and to CPU1, and CPU1 stores it, and deletes original the 3rd controlled flag.
CPU1 receives every clauses and subclauses of BD table by the time interval poll of setting, when the controlled flag in the clauses and subclauses of visit is the 4th controlled flag, CPU1 is according to the data address pointer in these clauses and subclauses, from this address data are write the CPU1 internal memory, then the 4th controlled flag in these clauses and subclauses is revised as the 3rd controlled flag, and in these clauses and subclauses, writes down the length of institute's data packets.The packet here is 1 packet of the address from this BD table clause.CPU1 has realized sending the readable announcement information of CPU1 internal memory to serial ports transceiver controller 30 to the modification of clauses and subclauses.
If receive the BD table 1 clauses and subclauses is only arranged, then after step S76, be read out if need data in the CPU1 internal memory that writes down in the current clauses and subclauses, then CPU1 is revised as the 3rd controlled flag with the 4th controlled flag; And skips steps S77 after step S76 directly changes step S72 over to, and the clauses and subclauses of the reception BD table of the visit among the step S72 are the unique clauses and subclauses that receive the BD table.
A kind of concrete structure and the working method of serial ports transceiver controller 30 more than have been described.Data transfer control system under the general structure below is described, this system is used for the transfer of data between CPU and the external data storage device.
When data when external data storage device transfers to CPU, this system configuration comprises CPU71 and transmitting device 72 as shown in Figure 7, CPU71 is used to generate first announcement information that the CPU memory headroom of CPU appointment can be write.The target data that transmitting device 72 is used for will coming from according to first announcement information data storage device writes the CPU71 memory headroom.First announcement information here is to show to realize by BD, also can directly send announcement information between CPU71 and the transmitting device 72 in addition to the other side, but so relatively expend both sides' resource, and because data are that serial mode writes CPU71, CPU71 generally can continue to read another section memory headroom after one section memory headroom is read, rather than require transmitting device at once data to be write the memory headroom of having read, so revise the BD table with a side between CPU71 and the transmitting device 72, the mode (i.e. step S66 above and S76 and CPU poll BD table) that the opposing party inquires about the BD table exchanges information, and need not real-time tranception information between the two.
As shown in Figure 7, a kind of internal structure of CPU71 and transmitting device 72 is that CPU71 comprises acquisition module 711 and generation module 712, and transmitting device 72 comprises memory module 721, first judge module 722 and write operation module 723.Acquisition module 711 is used to obtain the address of the CPU71 memory headroom of CPU71 appointment, can be stored among the CPU71 after obtaining.Generation module 712 is used to generate first controlled flag that the described CPU memory headroom of sign can be write, and also can be stored among the CPU71.Memory module 721 is used to receive and preserve the target data that comes from data storage device.First judge module 722 is used for judging according to described first controlled flag whether the CPU71 memory headroom can be write.Write operation module 723 is used for if the CPU71 memory headroom can be write, and then the target data that will come from data storage device according to the address of the CPU71 memory headroom of CPU71 appointment writes the CPU71 internal memory.
In the embodiment of the invention tape deck 73 can be set, it is positioned at CPU71 inside, with being shown among Fig. 7, be that CPU71 is provided with a part of memory headroom and constitutes tape deck 73, the sign that the CPU71 memory headroom that is used to preserve CPU71 memory headroom corresponding address and indicate this address can be write, tape deck 73 is preserved and is received the BD table in the embodiment of the invention, comprise two above logging modles and arrangement in order, each logging modle is used to preserve first announcement information, and the position that position, end logging modle is further used for writing down the first logging modle, all the other logging modles are further used for writing down the position of next logging modle.Acquisition module 711 is further used for sending to tape deck 73 address of the CPU71 memory headroom of CPU71 appointment.Generation module 712 is further used for sending first controlled flag to tape deck 73;
And first judge module comprises reads entry elements and judging unit, read the next record module position that entry elements is used for writing down according to logging modle and determine the current record module, first judging unit is used for judging if the current record module comprises first controlled flag, confirms that then the CPU71 memory headroom of the address correspondence in the current record module can be write.The write operation module comprises positioning unit and writing unit, positioning unit is used for when judging unit confirms that the CPU71 memory headroom of the address correspondence of current record module can be write, obtain described address from read the definite logging modle of entry elements, the address that writing unit is used for obtaining according to positioning unit writes the CPU71 internal memory with target data.
For can continuing to read transmitting device 72, CPU71 writes data in the CPU71 internal memory, transmitting device further comprises Registration Module 724, be used for writing the length of target data, and first controlled flag is wherein changed to the second readable controlled flag of CPU memory headroom that indicates the CPU appointment in the current record module.Logging modle is further used for writing down the length of the data that writing unit writes according to the CPU71 memory address in the current record module.CPU71 further comprises second judge module 713 and read module 714, with being shown among Fig. 7.Second judge module 713 is used for judging whether the current record module comprises second controlled flag, read module 714 is used for then reading target data according to the CPU71 memory address in the current record module and the length of target data if current clauses and subclauses comprise second controlled flag.Generation module 712 is further used for second controlled flag in the current record module is changed to first controlled flag.
When data when CPU transfers to external data storage device, the data transfer control system structure in the embodiment of the invention comprises CPU81 and transmitting device 82 as shown in Figure 8.CPU81 is used for depositing target data in the CPU81 internal memory and generating the second readable announcement information of target data place CPU81 memory headroom.Transmitting device 82 is used for reading target data and sending to data storage device from the CPU81 internal memory according to second announcement information.
As shown in Figure 8, a kind of internal structure of CPU81 and transmitting device 82 is in the embodiment of the invention, CPU81 comprises writing module 811, acquisition module 812 and generation module 813, and transmitting device 82 comprises first judge module 821, read operation module 822, memory module 823 and sending module 824.Writing module 811 is used for target data is write the CPU81 internal memory, and acquisition module 812 is used to obtain the address of the CPU81 memory headroom of CPU81 appointment, can be stored among the CPU81 after obtaining.Generation module 813 is used to generate the 3rd readable controlled flag of sign CPU81 memory headroom, also can be stored among the CPU81.First judge module 821 is used for judging according to the 3rd controlled flag whether the CPU81 memory headroom is readable.Read operation module 822 is used for if the CPU81 memory headroom is readable, and then the length according to CPU81 memory headroom corresponding address in the tape deck 83 and target data reads target data from the CPU81 internal memory.Memory module 823 is used to preserve the target data that read operation module 822 is read.Sending module 824 is used for the data of memory module 823 are sent to data storage device.
For having preserved the transmission BD table that comprises two above clauses and subclauses, in the embodiment of the invention tape deck 83 can be set, it is positioned at CPU81 inside, with being shown among Fig. 8, tape deck 83 comprises two above logging modles and arranges in order, each logging modle is used to preserve second announcement information, and the end position logging modle position that is further used for writing down the first logging modle, and all the other logging modles are further used for writing down the position of next logging modle.This structure corresponding to tape deck 83, acquisition module 812 is further used for sending to tape deck 83 address of the CPU81 memory headroom of CPU81 appointment in the embodiment of the invention, and generation module 813 is further used for sending the 3rd controlled flag to tape deck 83.
In order to make CPU81 continue to write data to the CPU81 internal memory, transmitting device 82 further comprises Registration Module 825, with being shown among Fig. 8, is used for the 3rd controlled flag of current record module is changed to the 4th controlled flag.And CPU81 further comprises second judge module 814, be used for judging whether described current record module comprises the 4th controlled flag, writing module 811 is further used for then the CPU81 memory address in the data based current record module being write the CPU81 internal memory if comprise the 4th controlled flag in the current record module.Generation module 813 is further used for writing module 811 writes the CPU81 internal memory according to the CPU81 memory address in the current record module after the 4th controlled flag in the current record module being changed to the 3rd controlled flag.
In embodiments of the present invention, by transmitting device and data transmit-receive flow process, realize finishing automatically the transmitting-receiving of serial data.When data transfer to the CPU internal memory from external memory, be with the data CPU internal memory that writes direct by the serial ports transceiver controller; When data transfer to external memory by the CPU internal memory, be data directly to be read from the CPU internal memory by the serial ports transceiver controller.This method makes that CPU need not in person the interface arrangement between CPU and the external memory to be carried out read-write operation, so the load of CPU when having reduced transmitting serial data has improved the disposal ability of system.In specific implementation, transmitting device can use pci interface, can be connected with all CPU with pci interface.Owing to can connect a plurality of serial ports controllers on a pci bus, realize the flexible expansion of system.PCI in the embodiment of the invention receives controller, PCI transmit control device, serial ports transmission interface, serial ports receiving interface, serial ports transmission buffer memory, serial ports receives buffer memory and pci interface can use logic control device and memory device to realize, also can use on-site programmable gate array FPGA (Field Programmable Gate Way) to realize.In real application systems, CPU comprises each functional module of the CPU71 of Fig. 7 and the CPU81 inside among Fig. 8, data transmission device also comprises each functional module of transmitting device 82 inside of the transmitting device 72 of Fig. 7 and Fig. 8, and comprise the tape deck 73 of Fig. 7 and the tape deck 83 of Fig. 8 in the system, be that CPU can preserve reception BD table simultaneously and send the BD table, such system just can realize the operation control to the read and write of CPU internal memory, is used for the data contact between CPU and the external data storage device.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. data transfer control method is applied to comprise it is characterized in that the system of central processor CPU, data storage device and transmitting device, comprising:
A, CPU generate the data transmit-receive record, described data transmit-receive record comprises two above clauses and subclauses and arranges in order, first announcement information that the CPU memory headroom of the CPU appointment of every entry record CPU generation can be write, and the memory location of last item entry record first term clauses and subclauses, the memory location of next clauses and subclauses of non-these clauses and subclauses of last item entry record; Described first announcement information comprises: first controlled flag that the CPU memory headroom of the address of CPU memory headroom and this address of sign can be write;
The target data that B, transmitting device will come from data storage device according to described first announcement information writes described CPU memory headroom, comprise: b1, transmitting device are judged if comprise first controlled flag in the clauses and subclauses of data transmit-receive record, are confirmed that then the CPU memory headroom of the address correspondence in the current clauses and subclauses can be write; B2, transmitting device receive and preserve the target data that comes from data storage device, according to described address described target data are write the CPU internal memory then.
2. method according to claim 1 is characterized in that, further comprises after the described step b2:
Transmitting device writes down the length of the target data of writing in described current clauses and subclauses, and first controlled flag in the described current clauses and subclauses is changed to the second readable controlled flag of sign CPU memory headroom;
Transmitting device is visited next clauses and subclauses according to the memory location of next clauses and subclauses of described current entry record;
CPU judges that then the length according to address in the described current clauses and subclauses and described target data reads described target data, then second controlled flag in the described current clauses and subclauses is changed to first controlled flag if comprise second controlled flag in the described current clauses and subclauses.
3. data transfer control method is applied to comprise it is characterized in that the system of central processor CPU, data storage device and transmitting device, comprising:
A, CPU deposit target data in the CPU internal memory and generate the second readable announcement information of described target data place CPU memory headroom, comprise: CPU generates the data transmit-receive record, described data transmit-receive record comprises two above clauses and subclauses and arranges in order, every described second announcement information of entry record, and the memory location of last item entry record first term clauses and subclauses, the memory location of next clauses and subclauses of non-these clauses and subclauses of last item entry record; Described second announcement information comprises: store the address of the CPU memory headroom of target data, the length of target data and the 3rd readable controlled flag of CPU memory headroom that indicates this address;
B, transmitting device read described target data according to described second announcement information from the CPU internal memory, comprise: step b1, transmitting device are judged if comprise the 3rd controlled flag in the clauses and subclauses of data transmit-receive record, are confirmed that then the CPU memory headroom of the address correspondence in the current clauses and subclauses is readable; Step b2, transmitting device read described target data according to the length of address in the described current clauses and subclauses and target data from the CPU internal memory;
C, transmitting device send described target data to data storage device.
4. as method as described in the claim 3, it is characterized in that, further comprise after the described step b2:
Transmitting device changes to the 3rd controlled flag in the described current clauses and subclauses and indicates the 4th controlled flag that the CPU memory headroom can be write;
Transmitting device is visited next clauses and subclauses according to the memory address of next clauses and subclauses of described current entry record;
CPU judges if comprise the 4th controlled flag in the described current clauses and subclauses, then writes data according to the address in the described current clauses and subclauses to the CPU internal memory, then the 4th controlled flag in the described current clauses and subclauses is changed to the 3rd controlled flag.
5. a data transfer control system is used for the transfer of data between Controlled CPU and the data storage device, it is characterized in that, comprises CPU and transmitting device, wherein,
Described CPU is used to generate first announcement information that the CPU memory headroom of CPU appointment can be write;
Described transmitting device is used for writing described CPU memory headroom according to the target data that described first announcement information will come from data storage device;
Described CPU comprises acquisition module and generation module, and described transmitting device comprises memory module, first judge module and write operation module, wherein,
Described acquisition module is used to obtain the address of the CPU memory headroom of CPU appointment;
Described generation module is used to generate first controlled flag that the described CPU memory headroom of sign can be write;
Described memory module is used to receive and preserve the target data that comes from data storage device;
Described first judge module is used for judging according to described first controlled flag whether described CPU memory headroom can be write;
Described write operation module is used for if described CPU memory headroom can be write, and then the target data that will come from data storage device according to described address writes the CPU internal memory.
6. as system as described in the claim 5, it is characterized in that, further comprise tape deck, described tape deck comprises two above logging modles and arranges in order, each logging modle is used to preserve the address and described first controlled flag of the CPU memory headroom of described CPU appointment, and the position that position, end logging modle is further used for writing down the first logging modle, all the other logging modles are further used for writing down the position of next logging modle;
Described acquisition module is further used for sending to tape deck the address of the CPU memory headroom of described CPU appointment;
Described generation module is further used for sending described first controlled flag to tape deck;
Described first judge module comprises reads entry elements and judging unit, wherein,
The described entry elements of reading, the next record module position that is used for writing down according to logging modle is determined the current record module,
Described judging unit is used for judging if described current record module comprises first controlled flag, confirms that then the CPU memory headroom of the described address correspondence in the described current record module can be write;
Described write operation module comprises positioning unit and writing unit,
Positioning unit is used for obtaining described address from described current record module when judging unit confirms that the CPU memory headroom of the described address correspondence of described current record module can be write,
Writing unit is used for according to the described address that positioning unit obtains target data being write the CPU internal memory.
7. as system as described in the claim 6, it is characterized in that, described transmitting device further comprises Registration Module, be used for length, and first controlled flag is wherein changed to the second readable controlled flag of CPU memory headroom that indicates the CPU appointment in the described target data of described current record module record;
Described logging modle is further used for writing down the length of described target data;
Described CPU further comprises second judge module and read module, wherein,
Described second judge module is used for judging whether described current record module comprises second controlled flag,
Described read module is used for if described current record module comprises second controlled flag, and then the length according to address in the described current record module and described target data reads described target data;
Described generation module is further used for second controlled flag in the described current record module is changed to first controlled flag.
8. a data transfer control system is used for the transfer of data between Controlled CPU and the data storage device, it is characterized in that, comprises CPU and transmitting device, wherein,
Described CPU is used for depositing target data in the CPU internal memory and generating the second readable announcement information of described target data place CPU memory headroom;
Described transmitting device is used for reading described target data and sending to data storage device from the CPU internal memory according to described second announcement information;
Described CPU comprises writing module, acquisition module and generation module, and described transmitting device comprises first judge module, read operation module, memory module and sending module, wherein,
The said write module is used for target data is write the CPU internal memory;
Described acquisition module is used to obtain the address of the CPU memory headroom of CPU appointment;
Described generation module is used to generate the 3rd readable controlled flag of the described CPU memory headroom of sign;
Described first judge module is used for judging according to described the 3rd controlled flag whether described CPU memory headroom is readable;
Described read operation module is used for if described CPU memory headroom is readable, and then the length according to described address and target data reads described target data from the CPU internal memory;
Described memory module is used to preserve the target data that the read operation module is read;
Described sending module is used for the data of memory module are sent to data storage device.
9. as system as described in the claim 8, it is characterized in that, further comprise tape deck, described tape deck comprises two above logging modles and arranges in order, each logging modle is used to preserve the address and described the 3rd controlled flag of the CPU memory headroom of described CPU appointment, and the position that position, end logging modle is further used for writing down the first logging modle, all the other logging modles are further used for writing down the position of next logging modle;
Described acquisition module is further used for sending to tape deck the address of the CPU memory headroom of described CPU appointment;
Described generation module is further used for sending described the 3rd controlled flag to tape deck;
Described first judge module comprises reads entry elements and judging unit, wherein,
The described entry elements of reading, the next record module position that is used for writing down according to logging modle is determined the current record module,
Described judging unit is used for judging if described current record module comprises the 3rd controlled flag, confirms that then the CPU memory headroom of the described address correspondence in the described current record module is readable;
Described read operation module comprises positioning unit and sensing element, wherein,
Described positioning unit is used for obtaining described address and data length from described current record module when judging unit confirms that the CPU memory headroom of described address correspondence of current record module is readable,
Described sensing element, the described address and the data length that are used for obtaining according to positioning unit are read described target data from the CPU internal memory.
10. as system as described in the claim 9, it is characterized in that described transmitting device further comprises Registration Module, be used for the 3rd controlled flag with described current record module and change to the 4th controlled flag that the CPU memory headroom that indicates the CPU appointment can be write;
Described CPU further comprises second judge module, is used for judging whether described current record module comprises the 4th controlled flag;
The said write module is further used for then the described address in the data based described current record module being write the CPU internal memory if comprise the 4th controlled flag in the described current record module;
Described generation module is further used for writing module writes the CPU internal memory according to the described address in the described current record module after the 4th controlled flag in the described current record module being changed to the 3rd controlled flag.
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