CN101237346B - Network processor and method for network processor to read and write serial port - Google Patents
Network processor and method for network processor to read and write serial port Download PDFInfo
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Abstract
The invention provides a network processor and a method of the read-write serial port of the network processor, wherein the network processor comprises a control engine, a plurality of accelerating engines and a read-write serial port accelerating engine set unit; a user selects at least one accelerating engine idler than other accelerating engines as a read-write serial port accelerating engine. Moreover, the read-write serial port accelerating engine, relative to a memory, meets at least one of the following conditions: the read-write serial port accelerating engine has an instruction for direct read and write of the memory; the read-write serial port accelerating engine realizes read and write of the memory through a direct memory access controller. Meanwhile, the read-write serial port accelerating engine, relative to a read-write serial port, meets at least one of the following conditions: the read-write serial port accelerating engine has an instruction for direct read and write of a serial port register; the read-write serial port accelerating engine completes read and write of a serial port register mapped to a memory address space through a direct memory access controller.
Description
Technical field
The present invention relates to network processing unit and communication technical field, relate in particular to the read and write serial port of a kind of network processing unit and network processing unit method, be to use UART (UART Universal Asynchronous Receiver Transmitter) read and write serial port method for communicating on the network processor platform.
Background technology
At present, network processing unit has been widely used in the diverse network product.Generally, network processing unit comprises a Control Engine that plays the master control effect, one or more accelerating engines that are used to accelerate the message forwarding rate.Usually, accelerating engine can participate in Ethernet interface, ATM mouth, WLAN mouth etc. in the data transmit-receive process of high-speed interface, and for the such low-speed interface of UART serial ports, then is the transmitting-receiving of directly being responsible for data by Control Engine.
Because serial port chip inside has only several usually even has only the spatial cache of a byte; So when the serial ports baud rate is higher; No matter Control Engine is to adopt interruption or poll type of drive to come read and write serial port, its result, and not only the load of Control Engine can be higher; The situation that also occurs obliterated data etc. easily is especially for more like this at receive direction.In this case, if by Control Engine direct read serial ports, for obliterated data not, baud rate generally can not surpass 38400.
On the other hand, some is connected to the external equipment of network processing unit through serial ports, and for example, Bluetooth chip etc. can propose higher requirement to data transfer rate.If baud rate can only reach 38400, then data transfer rate can only reach more than 30 kbps, the high requirement of the external equipment that can not meet the demands.
Summary of the invention
In view of the above problems; The object of the invention is to provide the method for the read and write serial port of a kind of network processing unit and network processing unit; It has improved the read-write speed of read and write serial port, thereby has improved the traffic rate of the external equipment that links to each other with network processing unit through read and write serial port.
According to an aspect of the present invention; A kind of network processing unit is provided, has comprised Control Engine, a plurality of accelerating engine, network processing unit also comprises: read and write serial port accelerating engine setup unit; Be used for the user in a plurality of accelerating engines of network processing unit; Select at least one said accelerating engine, wherein selected at least one said accelerating engine is compared with other accelerating engines in a plurality of accelerating engines and is in more idle state, and with it as the read and write serial port accelerating engine; Wherein, the read and write serial port accelerating engine with respect to internal memory satisfied below at least one situation: the read and write serial port accelerating engine has the instruction of direct read internal memory; And the read and write serial port accelerating engine comes read/write memory through the direct memory access controller, and the read and write serial port accelerating engine with respect to read and write serial port satisfied below at least one situation: the read and write serial port accelerating engine has the instruction of direct read read and write serial port register; And the read and write serial port accelerating engine is mapped to the read and write serial port register of memory address space through the read-write of direct memory access controller.
Wherein, in network processing unit, being used to read serial ports is identical accelerating engine or different accelerating engines with the accelerating engine of writing serial ports.
In above-mentioned network processing unit, the read and write serial port accelerating engine comprises counter, and the byte number that is used for the read and write serial port accelerating engine is received data is counted.
In above-mentioned network processing unit, the read and write serial port accelerating engine comprises timer, is used for the time of read and write serial port accelerating engine reception data is carried out timing.
According to a further aspect in the invention; A kind of method of operation read and write serial port of above-mentioned network processing unit is provided; It comprises: step 1; The user sets the accelerating engine that is used for carrying out through read and write serial port the data write operation through read and write serial port accelerating engine setup unit, and by Control Engine initialization read and write serial port; And step 2, carry out the data write with external equipment by read and write serial port accelerating engine and Control Engine through read and write serial port.
In step 2, may further comprise the steps: read step; The read and write serial port accelerating engine is reading of data from read and write serial port byte-by-byte ground; And with the data that the read reception buffer memory in the data block ground write memory one by one; Then, read and write serial port accelerating engine notice Control Engine receives data, and Control Engine is directly fetched data from receiving cache read according to the notice of sending from the read and write serial port accelerating engine.
In addition; In step 2, can also may further comprise the steps: the transmission buffer memory in the data write memory that write step, Control Engine will be wanted to send, the read and write serial port accelerating engine reads to data block one by one and wants the data of sending from sending buffer memory; And byte-by-byte write read and write serial port; And, to write under the some or all of data conditions, read and write serial port accelerating engine notice Control Engine is sent and is accomplished.
In read step, data block comprises the data smaller or equal to predetermined byte number, and read step may further comprise the steps: whether the read and write serial port accelerating engine adopts the mode of interruption or poll to detect at read and write serial port has data to read; Detecting at read and write serial port at the read and write serial port accelerating engine has under the situation that data can read; Byte-by-byte ground is from the reception buffer register reading of data of read and write serial port; Comprise at the read and write serial port accelerating engine under the situation of counter; Through counter the data that read are counted or comprised under the situation of timer at the read and write serial port accelerating engine, the data that read are carried out timing through timer; Data word joint number reading reaches predetermined number, and perhaps the time of reading of data reaches under the situation of the scheduled time, and the read and write serial port accelerating engine writes the reception buffer memory with the data that read, and the notice Control Engine; And Control Engine notified after, fetch data from receiving cache read.
Send to network processing unit at the external equipment that is connected with read and write serial port under the situation of transmission rate above the receiving velocity of Control Engine or read and write serial port accelerating engine of data; The read and write serial port accelerating engine uses the flow control mechanism of read and write serial port, sends data or makes external equipment reduce the transmission rate of data thereby external equipment is suspended.
In write step, data block comprises the data smaller or equal to predetermined byte number, and write step may further comprise the steps: send under the data conditions to read and write serial port in Control Engine, Control Engine writes the transmission buffer memory with data, and notice read and write serial port accelerating engine; After the read and write serial port accelerating engine receives the notice of sending from Control Engine, from sending buffer memory data block ground reading of data one by one; Whether the read and write serial port accelerating engine adopts the mode of interruption or poll to detect read and write serial port can send data; Detect read and write serial port at the read and write serial port accelerating engine and can send under the data conditions, with the data byte-by-byte write the transmission save register of read and write serial port; And under the some or all of data conditions in read and write serial port accelerating engine transmission buffer memory, read and write serial port accelerating engine notice Control Engine.
Send to the external equipment that is connected with read and write serial port at network processing unit under the situation of transmission rate above the transmission rate of Control Engine or read and write serial port accelerating engine of data; The read and write serial port accelerating engine uses the flow control mechanism of read and write serial port, so that suspend to outside equipment sending data or reduce the transmission rate to outside equipment sending data.
The low excessively problem of traffic rate when the present invention has overcome the Control Engine read and write serial port that uses network processing unit in the prior art.In addition, the present invention has not only alleviated the load on the Control Engine through the task of read and write serial port is transferred on the accelerating engine by Control Engine, has significantly improved the traffic rate of read and write serial port simultaneously.Therefore, through the present invention, the data transmit-receive speed of read and write serial port has improved more than ten times at least.
Other features and advantages of the present invention will be set forth in specification subsequently, and, partly from specification, become obvious, perhaps understand through embodiment of the present invention.The object of the invention can be realized through the structure that in the specification of being write, claims and accompanying drawing, is particularly pointed out and obtained with other advantages.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of specification, is used to explain the present invention with embodiments of the invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the structured flowchart according to network processing unit of the present invention;
Fig. 2 is the flow chart according to the method for the read and write serial port of network processing unit of the present invention;
Fig. 3 is the sketch map according to the structure of the network processing unit of the embodiment of the invention;
Fig. 4 is the overall flow figure according to the read-write flow process of read and write serial port in the accelerating engine of the embodiment of the invention;
Fig. 5 is the flow chart according to the sub-process of the Data Receiving of read and write serial port in the accelerating engine of the embodiment of the invention;
Fig. 6 is the flow chart according to the sub-process of the Data Receiving of read and write serial port in the accelerating engine of the embodiment of the invention;
Fig. 7 is according to the Control Engine of the embodiment of the invention flow chart from the flow process that receives cache read and fetch data; And
Fig. 8 is the sub-process figure that sends according to the data of read and write serial port in the accelerating engine of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for explanation and explains the present invention, and be not used in qualification the present invention.
Fig. 1 is the structured flowchart according to network processing unit of the present invention.
As shown in Figure 1, network processing unit 100 comprises Control Engine 102, a plurality of accelerating engine 1041～104n (wherein; N >=1); In addition, network processing unit 100 also comprises: read and write serial port accelerating engine setup unit 106 is used for the user in a plurality of accelerating engines of network processing unit 100; Select at least one to compare and be in idle more state accelerating engine with other accelerating engines in a plurality of accelerating engines; And with it as the read and write serial port accelerating engine, wherein, the read and write serial port accelerating engine with respect to internal memory satisfied below at least one situation: the read and write serial port accelerating engine has the instruction of direct read internal memory; And the read and write serial port accelerating engine comes read/write memory through the direct memory access controller, and the read and write serial port accelerating engine with respect to read and write serial port satisfied below at least one situation: the read and write serial port accelerating engine has the instruction of direct read read and write serial port register; And the read and write serial port accelerating engine is mapped to the serial ports register of memory address space through the read-write of direct memory access controller.
Wherein, in network processing unit 100, being used to read serial ports is identical accelerating engine or different accelerating engines with the accelerating engine of writing serial ports.
In above-mentioned network processing unit 100, the read and write serial port accelerating engine comprises counter, and the byte number that is used for the read and write serial port accelerating engine is received data is counted.
In above-mentioned network processing unit 100, the read and write serial port accelerating engine comprises timer, is used for the time of read and write serial port accelerating engine reception data is carried out timing.
Fig. 2 is the flow chart according to the method for the read and write serial port of network processing unit of the present invention.
As shown in Figure 2; Method based on the read and write serial port of above-mentioned network processing unit; It comprises: step S202, and the user sets the accelerating engine that is used for carrying out through read and write serial port the data write operation through read and write serial port accelerating engine setup unit, and by Control Engine initialization read and write serial port; And step S204, carry out the data write with external equipment by read and write serial port accelerating engine and Control Engine through read and write serial port.
In step S204, may further comprise the steps: read step; The read and write serial port accelerating engine is reading of data from read and write serial port byte-by-byte ground; And with the data that the read reception buffer memory in the data block ground write memory one by one; Then, read and write serial port accelerating engine notice Control Engine receives data, and Control Engine is directly fetched data from receiving cache read according to the notice of sending from the read and write serial port accelerating engine.
In addition; In step S204, also may further comprise the steps: the transmission buffer memory in the data write memory that write step, Control Engine will be wanted to send, the read and write serial port accelerating engine reads to data block one by one and wants the data of sending from sending buffer memory; And byte-by-byte write read and write serial port; And, to write under the some or all of data conditions, read and write serial port accelerating engine notice Control Engine is sent and is accomplished.
In read step, data block comprises the data smaller or equal to predetermined byte number, and read step may further comprise the steps: whether the read and write serial port accelerating engine adopts the mode of interruption or poll to detect at read and write serial port has data to read; Detecting at read and write serial port at the read and write serial port accelerating engine has under the situation that data can read, and byte-by-byte ground is from the reception buffer register reading of data of read and write serial port, and through counter or timer the data that read is counted or timing; Data word joint number reading reaches predetermined number, and perhaps the time of reading of data reaches under the situation of the scheduled time, and the read and write serial port accelerating engine writes the reception buffer memory with the data that read, and the notice Control Engine; And Control Engine notified after, fetch data from receiving cache read.
Send to network processing unit at the external equipment that is connected with read and write serial port under the situation of transmission rate above the receiving velocity of Control Engine or read and write serial port accelerating engine of data; The read and write serial port accelerating engine uses the flow control mechanism of read and write serial port, sends data or makes external equipment reduce the transmission rate of data thereby external equipment is suspended.
In write step, data block comprises the data smaller or equal to predetermined byte number, and write step may further comprise the steps: send under the data conditions to read and write serial port in Control Engine, Control Engine writes the transmission buffer memory with data, and notice read and write serial port accelerating engine; After the read and write serial port accelerating engine receives the notice of sending from Control Engine, from sending buffer memory data block ground reading of data one by one; Whether the read and write serial port accelerating engine adopts the mode of interruption or poll to detect read and write serial port can send data; Detect read and write serial port at the read and write serial port accelerating engine and can send under the data conditions, with the data byte-by-byte write the transmission save register of read and write serial port; And under the some or all of data conditions in read and write serial port accelerating engine transmission buffer memory, read and write serial port accelerating engine notice Control Engine.
Send to the external equipment that is connected with read and write serial port at network processing unit under the situation of transmission rate above the transmission rate of Control Engine or read and write serial port accelerating engine of data; The read and write serial port accelerating engine uses the flow control mechanism of read and write serial port, so that suspend to outside equipment sending data or reduce the transmission rate to outside equipment sending data.
Particularly, the network processing unit that is used to realize the read and write serial port method of the network processing unit that the present invention relates to need meet the following conditions simultaneously: (1) has at least an accelerating engine relatively more idle; (2) accelerating engine has the instruction of direct read internal memory, perhaps can pass through DMA (Direct Memory Access, direct memory access) controller read/write memory; Accelerating engine has the instruction of direct read serial ports register, perhaps can read and write the serial ports register that is mapped to memory headroom through the mode of DMA.In the prior art, there is the network processing unit that satisfies above-mentioned condition.And, the method for the read and write serial port of the network processing unit that the network processing unit that satisfies aforementioned three conditions all can be realized the present invention relates to.
The method of the read and write serial port of the network processor-based that the present invention relates to (below, abbreviate serial ports as) may further comprise the steps:
Steps A; Setting is used for carrying out through read and write serial port the read and write serial port accelerating engine of data write operation; And carry out the initialization serial ports by the Control Engine of network processing unit, and the reception shared of distribution and accelerating engine and send operation such as buffer memory, wherein; Reading serial ports can be same with the accelerating engine of writing serial ports, also can not be;
Step B, read and write serial port accelerating engine read a byte from the serial ports reading of data at every turn, then with the data block-by-block that reads write the reception buffer memory in the internal memory, and the notice Control Engine receives data.Control Engine is reading of data from receive buffer memory directly; And
Step C, the transmission buffer memory in the data write memory that Control Engine will be sent.The read and write serial port accelerating engine reads the data that will send block-by-block from send buffer memory, and writes serial ports, writes a byte at every turn.During intact some or all of data to be written, the notice Control Engine is sent and is accomplished.
Wherein, steps A was carried out before step B and C, the order on the carrying out of step B and step C is not free.Step B can be carried out by different read and write serial port accelerating engines with step C, also can on same accelerating engine, carry out.
In addition, this step B may further comprise the steps:
Whether step B1, read and write serial port accelerating engine can adopt the mode of interruption or poll to detect serial ports has data readable;
Step B2, when read and write serial port detected serial ports and has data readable, accelerating engine read the data of a byte at every turn from the RBR (Receive Buffer Register receives buffer register) of serial ports;
Step B3, read and write serial port accelerating engine write to data block the data that receive in the reception buffer memory of sharing with Control Engine one by one;
Step B4, Control Engine is reading of data from receive buffer memory; And
Step B5; To send data to network processing unit too fast when the external equipment that is connected with serial ports; And when having surpassed Control Engine or having received the receiving velocity of engine, the flow control mechanism that the read and write serial port accelerating engine uses serial ports to provide perhaps reduces transmission rate thereby external equipment is suspended send.
Wherein, the read and write serial port accelerating engine should comprise counter, and this counter with the reception buffer memory in the data write memory of this data block, and is notified Control Engine, then with counter O reset after the data that receive the predetermined number byte.This data block comprises the data of predetermined number byte, and predetermined number can limit according to the configuration and the actual demand of hardware.
In addition, accelerating engine also can also should comprise timer, and this timer picks up counting from first byte that receives a certain data block.After surpassing certain hour, even the byte number that receives does not also reach specified number or amount in the counter institute, also data block is write the reception buffer memory, and the notice Control Engine receives, then with the timer zero clearing, pick up counting again after waiting to receive next byte.
In step C, may further comprise the steps:
Step C1 is when Control Engine need with the transmission buffer memory in the data write memory, be notified the read and write serial port accelerating engine then when serial ports sends data;
Step C2 is after the read and write serial port accelerating engine is notified, from sending buffer memory data block ground reading of data one by one;
Whether step C3, read and write serial port accelerating engine can adopt the mode of interruption or poll to detect serial ports can send data;
Step C4, when the read and write serial port accelerating engine detected serial ports and can write, the read and write serial port accelerating engine write the data of a byte THR (Transmit HoldingRegister, transmit holding register) of serial ports at every turn;
Step C5, after the read and write serial port accelerating engine sends the some or all of data in the transmission buffer memory that is over, the notice Control Engine.
Step C6, the flow control mechanism that the read and write serial port accelerating engine should use serial ports to provide, thus avoid too fastly to outside equipment sending data.
Fig. 3 is the sketch map according to the structure of the network processing unit of the embodiment of the invention.
As shown in Figure 3, network processing unit satisfies the following requirement that proposes: have an accelerating engine 208 relatively more idle; Accelerating engine can pass through the dma controller access memory; And accelerating engine can also be through the serial ports register of dma controller access map to memory headroom.
And, in this network processing unit, can give accelerating engine with the interruption that external equipment produces and handle.Though when central stopping pregnancy is given birth to, can't interrupt the operation that accelerating engine is being carried out, a flag bit can be set, accelerating engine can check that this position judges whether to have taken place interruption.
The accelerating engine of this network processing unit is not supported a plurality of tasks of concurrent execution, and each task is to carry out in turn.Generally, when certain task is carried out dma operation, will dispatch next task and carry out.
Below, according to Fig. 3,, do further to specify through the idiographic flow that read and write serial port carries out reading and writing data by accelerating engine 308 and Control Engine 310 on network processing unit.
In this network processing unit, comprise four accelerating engines, wherein accelerating engine 302～306 will be responsible for the transmitting-receiving of the packet of ATM (asynchronous transfer mode) network interface or EMAC (the Ethernet medium are got involved control) network interface respectively, and is busier.And accelerating engine 308 is relatively idle, is set at read and write serial port accelerating engine (below, abbreviate accelerating engine 308 as) so will speed up engine 3 08, and on accelerating engine 308, realizes the operation of read and write serial port.During the register of accelerating engine access memory or external equipment, all can only pass through dma controller.In addition, in the present embodiment, this network processing unit is a Bluetooth chip through the external equipment that the UART serial ports connects, and supports the RTS/CTS flow control mechanism.
After the system start-up, Control Engine 310 is carried out initialization operation, may further comprise the steps:
Step 2 is provided with the parameter such as baud rate, data bit, parity check bit of serial ports.The chip that these parameters should be connected with serial ports or the parameter of equipment are consistent;
Step 3 is provided with interrupt control unit, the interruption of serial ports is given the accelerating engine of appointment and handles; And
Step 4 is provided with the OIER of serial ports, and beginning only enables the interruption that RBR produces when full.
Reception buffer memory in the internal memory is one section continuous space, is divided into several fritters.First byte of each fritter indicates the byte number of the data that comprise in this fritter, all should be set to 0 when initial.Each fritter constitutes ring-like buffering area.Like this, accelerating engine when block-by-block ground writes data in receiving buffer memory, Control Engine 310 also can be from receive buffer memory block-by-block ground reading of data, the time of minimizing wait.
Transmission buffer memory in the internal memory is one section continuous space, also is divided into several fritters (data block).First byte of each fritter also is to indicate the data word joint number that comprises in this fritter, all should be set to 0 when initial.Each fritter constitutes a linear pattern buffer memory.Second byte of each fritter indicates in the fritter after it whether include data.Control Engine 310 with a bulk of data be divided into a plurality of fritters be written to send buffer memory after, accelerating engine 308 could begin reading of data from send buffer memory.And send in the process of data at accelerating engine 308, Control Engine 310 can not be inserted new data in sending buffer memory.
Because accelerating engine 308 needs the mode ability access memory through DMA; In order to reduce number DMA time; So accelerating engine 308 inside also have one to receive buffer memory and a transmission buffer memory, its size equals the reception buffer memory and the size of sending a fritter in the buffer memory in the internal memory respectively.
In addition, though in the present embodiment, will receive the buffer memory setting and constitute ring-like buffering area; And will send buffer memory and set and to constitute the linear pattern buffering area; But the reception buffer memory in the internal memory is not limited thereto with the institutional framework of sending buffer memory, for example, receives buffer memory and also can constitute the linear pattern buffering area; Send buffer memory and also can constitute ring-like buffering area, can be provided with flexibly according to actual conditions.But, need to guarantee that accelerating engine 310 writes the data that receive to receiving buffer memory in data block ground one by one, can from send buffer memory, read the data that will send in block-by-block ground simultaneously.
And, in the present embodiment, carry out the reception data and transmission data of serial ports by same accelerating engine.
Fig. 4 is the overall flow figure according to the read-write flow process of read and write serial port in the accelerating engine of the embodiment of the invention.
As shown in Figure 4, may further comprise the steps according to the read-write flow process of read and write serial port in the accelerating engine of the embodiment of the invention:
Step S402, whether inspection receives timer overtime, if overtime, then stops timer, and forward the step S602 among Fig. 6 to, if do not have overtimely, then gets into step S404;
Step S404, the inspection interrupt flag bit has judged whether the serial ports interruption generating, if there is not the serial ports interruption generating, then enters step S412;
Step S406 reads the LSR (Line Status Register, line status register) of serial ports;
Step S408 judges whether RBR full, if LSR shows that RBR is full, then gets into step S502 among Fig. 5, if LSR show RBR less than, then get into the step S410 among Fig. 4;
Step S410, empty if LSR shows THR, then reexamine built-in variable uartTxFlag, if built-in variable uartTxFlag is 1, then get into the step S802 among Fig. 8, otherwise get into step S412.Be to be set to 0 when wherein, the uartTxFlag variable is initial; And
Step S412 carries out other task in the accelerating engine.
Fig. 5 is the flow chart according to the sub-process of the Data Receiving of read and write serial port in the accelerating engine of the embodiment of the invention.
As shown in Figure 5, the sub-process of the Data Receiving of the serial ports in the accelerating engine is handled and may further comprise the steps:
Step S502 reads the RBR register of serial ports;
Step S504 writes a byte that reads in the inner reception buffer memory of accelerating engine;
Step S506, whether the inner reception of inspection buffer memory is full, if full, then jumps to step S602 in the block diagram 6, if less than, then get into step S508;
Step S508 starts if receive timer this moment, then directly gets into the step S412 among Fig. 4, does not start if receive timer this moment, then gets into step S510; And
Step S510 starts the reception timer, picks up counting, and gets into step S412 among Fig. 4 then.
Fig. 6 is the flow chart according to the sub-process of the Data Receiving of read and write serial port in the accelerating engine of the embodiment of the invention.
As shown in Figure 6, reception buffer memory inner in accelerating engine is full, and perhaps timer expiry may further comprise the steps:
Step S602, inside receives the byte number that first byte in the buffer memory is set to data in the buffer memory;
Step S604, whether first byte that the interior call number of reception buffer memory equals the fritter of RxWrIdx (call number of the current piece that will write of accelerating engine) in the inspection internal memory equals 0.If equal 0, then get into step S612, if be not equal to 0, then get into step S606;
Step S606, the reception buffer memory of annular is full in expression internal memory this moment, and the RTS pin then is set, and notice Bluetooth chip time-out sends;
Step S608 sends the RxOverrun signal to Control Engine;
Step S610 restarts the reception timer, and the time be set to less value, get into the step S412 among Fig. 4 then;
Step S612 is provided with the RTS pin, and the notice Bluetooth chip continues to send data;
Step S614, call number is in the fritter of RxWrIdx in the buffer memory with receiving in the reception buffer memory write memory of inside through dma mode;
Step S616 sends the RxDataRdy signal to Control Engine.Wherein, this signal can be to interrupt or other form; And
Step S618 adds 1 with RxWrIdx, and to the RxBlocksNum delivery, that is, if equal RxBlocksNum, then RxWrIdx is reverted to 0, gets into the step S412 among Fig. 4.
Fig. 7 is according to the Control Engine of the embodiment of the invention flow chart from the flow process that receives cache read and fetch data.
As shown in Figure 7, when Control Engine was received the RxDataRdy signal, it received handling process and may further comprise the steps:
Step S702, whether the 1st byte is 0 in the fritter that the interior call number of reception buffer memory is RxRdIdx in the inspection internal memory.If be 0, show free of data, then withdraw from the reception handling process.If be not 0, then get into step S604.
Step S704, reading call number is the interior data of fritter of RxRdIdx;
Step S706, after running through above-mentioned data, first byte of these above-mentioned data is set to 0;
Step S708 adds 1 with RxRdInx, if equal RxBlocksNum, then RxRdIdx is reverted to 0;
Step S710, whether inspection equals RxWrIndx.If be not equal to RxWrIndx, then get into step S704, if equal RxWrIndx, then get into step S712; And
Step S712 is assembled into a bulk of data with each the little blocks of data that reads, and gives the bluetooth protocol repertory on upper strata.
Wherein, when Control Engine receives the RxOverrun signal,, also can increase by one and receive wrong statistical figure except by receiving that RxDataRdy signal that kind operates.
When Control Engine has data to send, data are split into fritter, write and send in the buffer memory.Last comprises, and second byte is set to 0 in the fritter of data, and second byte of each fritter of front all is set to 1.After having write, send the TxBegin signal, and enable the interruption of generation when serial ports THR is empty to accelerating engine.
Receive at accelerating engine under the situation of TxBegin signal, the uartTxFlag variable of inside is set to 1.And first byte that buffer memory is sent in inside is set to 0, the second byte and is set to 1, and the TxRdIdx variable is set to 0.
Fig. 8 is the sub-process figure that sends according to the data of read and write serial port in the accelerating engine of the embodiment of the invention.
As shown in Figure 8, the processing that the data of read and write serial port are sent in the accelerating engine may further comprise the steps:
Step S802, inspection CTS pin, judge current whether can be to outside equipment sending data.If cannot then get into the step S412 among Fig. 4, if can then get into step S804 to outside equipment sending data to outside equipment sending data;
Step S804, inner first byte of sending buffer memory of inspection if first byte is not 0, then gets into step S810, if first byte is 0, then gets into step S806;
Step S806, inner second byte of sending buffer memory of inspection if second byte is 0, then gets into step S814, if second byte is not 0, then gets into step S808;
Step S808 through dma mode, is that the fritter of TxRdInx reads inner transmission buffer memory with sending call number in the buffer memory in the internal memory;
Step S810 sends the THR register that a byte in the buffer memory is write serial ports with inside;
Step S812, first byte of inside being sent buffer memory subtracts 1, gets into the step S412 among Fig. 4 then; And
Step S814 sends the TxComplete signal to Control Engine, and the uartTxFlag variable is set to 0, and inside sends second byte of buffer memory and be set to 1, gets into the step S412 among Fig. 4 then.
Wherein, when Control Engine is received the TxComplete signal, if also have data to send, then can write data in the transmission buffer memory in internal memory once more, and send the TxBegin signal to accelerating engine once more.If there are not data to send, then forbid the interruption that produces when serial ports THR is empty.
The low excessively problem of traffic rate when in sum, the present invention has overcome the Control Engine read and write serial port that uses network processing unit in the prior art.In addition, the present invention has not only alleviated the load on the Control Engine through the task of read and write serial port is transferred on the accelerating engine by Control Engine, has significantly improved the traffic rate of read and write serial port simultaneously.Therefore, through the present invention, the data transmit-receive speed of read and write serial port has improved more than ten times at least.
More than be merely the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a network processing unit comprises Control Engine, a plurality of accelerating engine, it is characterized in that said network processing unit also comprises:
Read and write serial port accelerating engine setup unit; Be used for the user in a plurality of said accelerating engine of said network processing unit; Select at least one said accelerating engine; Wherein selected at least one said accelerating engine is compared with other the said accelerating engines in a plurality of said accelerating engines and is in more idle state, and with it as the read and write serial port accelerating engine
Wherein, said read and write serial port accelerating engine with respect to internal memory satisfied below at least one situation: said read and write serial port accelerating engine has the instruction of the said internal memory of direct read; And said read and write serial port accelerating engine reads and writes said internal memory through the direct memory access controller, and
Said read and write serial port accelerating engine with respect to said read and write serial port satisfied below at least one situation: said read and write serial port accelerating engine has the instruction of the said read and write serial port register of direct read; And said read and write serial port accelerating engine is mapped to the said read and write serial port register of memory address space through the read-write of direct memory access controller.
2. network processing unit according to claim 1 is characterized in that,
In said network processing unit, being used to read serial ports is identical accelerating engine or different accelerating engines with the accelerating engine of writing serial ports.
3. network processing unit according to claim 1 is characterized in that,
Said read and write serial port accelerating engine comprises counter, is used for the byte number that said read and write serial port accelerating engine receives data is counted.
4. network processing unit according to claim 1 is characterized in that,
Said read and write serial port accelerating engine comprises timer, is used for the time of said read and write serial port accelerating engine reception data is carried out timing.
5. the method for the operation read and write serial port of each described network processing unit in the claim 1 to 4 is characterized in that, comprising:
Step 1, said user sets the said accelerating engine that is used for carrying out through said read and write serial port the data write operation through said read and write serial port accelerating engine setup unit, and by the said read and write serial port of said Control Engine initialization; And
Step 2 is carried out operating with the said data write of external equipment through said read and write serial port by said read and write serial port accelerating engine and said Control Engine.
6. method according to claim 5 is characterized in that,
In said step 2, may further comprise the steps:
Read step; Said read and write serial port accelerating engine is reading of data from said read and write serial port byte-by-byte ground; And the said data that will the read reception buffer memory in the data block ground write memory one by one; Then, said read and write serial port accelerating engine notifies said Control Engine to receive said data, and said Control Engine directly reads said data from said reception buffer memory according to the said notice of sending from said read and write serial port accelerating engine.
7. method according to claim 5 is characterized in that,
In said step 2, may further comprise the steps:
Write step; Transmission buffer memory in the said data write memory that said Control Engine will be wanted to send; Said read and write serial port accelerating engine reads to data block from said transmission buffer memory one by one wants the said data of sending, and byte-by-byte write said read and write serial port, and; Writing under the some or all of said data conditions, said read and write serial port accelerating engine notice Control Engine is sent and is accomplished.
8. method according to claim 6 is characterized in that,
In said read step, said data block comprises the said data smaller or equal to predetermined byte number, and said read step may further comprise the steps:
Whether said read and write serial port accelerating engine adopts the mode of interruption or poll to detect at said read and write serial port has said data to read;
Detecting at said read and write serial port at said read and write serial port accelerating engine has under the situation that said data can read; Byte-by-byte ground reads said data from the reception buffer register of said read and write serial port; Said read and write serial port accelerating engine comprises under the situation of said counter; Through said counter the said data that read are counted or comprised under the situation of said timer at said read and write serial port accelerating engine, the said data that read are carried out timing through said timer; Said data word joint number reading reaches predetermined number, and the time of perhaps reading said data reaches under the situation of the scheduled time, and the said data that said read and write serial port accelerating engine will read write said reception buffer memory, and notify said Control Engine; And
After said Control Engine is received said notice, read said data from said reception buffer memory.
9. method according to claim 8 is characterized in that,
Send to said network processing unit at the said external equipment that is connected with said read and write serial port under the situation of transmission rate above the receiving velocity of said Control Engine or said read and write serial port accelerating engine of said data; Said read and write serial port accelerating engine uses the flow control mechanism of said read and write serial port, sends said data or makes said external equipment reduce the said transmission rate of said data thereby said external equipment is suspended.
10. method according to claim 7 is characterized in that,
In the said write step, said data block comprises the said data smaller or equal to predetermined byte number, and the said write step may further comprise the steps:
Send under the said data conditions to said read and write serial port in said Control Engine, said Control Engine writes said transmission buffer memory with said data, and notifies said read and write serial port accelerating engine;
After said read and write serial port accelerating engine receives the said notice of sending from said Control Engine, read to data block said data one by one from said transmission buffer memory;
Whether said read and write serial port accelerating engine adopts the mode of interruption or poll to detect said read and write serial port can send said data;
Detect said read and write serial port at said read and write serial port accelerating engine and can send under the said data conditions, with said data byte-by-byte write the transmission save register of said read and write serial port; And
Sent under the some or all of said data conditions in the said transmission buffer memory at said read and write serial port accelerating engine, said read and write serial port accelerating engine is notified said Control Engine.
11. method according to claim 10 is characterized in that,
Send to the said external equipment that is connected with said read and write serial port at said network processing unit under the situation of transmission rate above the transmission rate of said Control Engine or said read and write serial port accelerating engine of said data; Said read and write serial port accelerating engine uses the flow control mechanism of said read and write serial port, sends said data or reduces the said transmission rate of sending said data to said external equipment so that suspend to said external equipment.
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| CN102495813B (en) * | 2011-12-02 | 2014-07-23 | 西安大唐电信有限公司 | Mining embedded multi-serial-port inquiring method |
| CN105656994B (en) * | 2014-12-31 | 2019-02-05 | 华为技术有限公司 | A kind of business acceleration method and device |
| KR102335649B1 (en) * | 2015-06-09 | 2021-12-03 | 한화테크윈 주식회사 | Apparatus and method for processing data |
| CN105955764A (en) * | 2016-04-22 | 2016-09-21 | 佛山市南海区欧谱曼迪科技有限责任公司 | Improvement method for STM32 single-chip microcomputer IAP serial program burning |
| CN106160946B (en) * | 2016-09-22 | 2019-03-29 | 广东电网有限责任公司电力科学研究院 | A kind of UART means of communication and system |
| CN113419989B (en) * | 2021-06-11 | 2023-01-20 | 上海壁仞智能科技有限公司 | Artificial intelligence chip and operation method thereof |
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| CN1643499A (en) * | 1999-12-28 | 2005-07-20 | 英特尔公司 | Thread signaling in multi-threaded network processor |
| CN1853379A (en) * | 2002-12-31 | 2006-10-25 | 肯奈克斯特公司 | System and method for providing quality of service in asynchronous transfer mode cell transmission |
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| CN1643499A (en) * | 1999-12-28 | 2005-07-20 | 英特尔公司 | Thread signaling in multi-threaded network processor |
| CN1853379A (en) * | 2002-12-31 | 2006-10-25 | 肯奈克斯特公司 | System and method for providing quality of service in asynchronous transfer mode cell transmission |
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