CN106227681B - A kind of dual port RAM access method of novel anti-collision - Google Patents
A kind of dual port RAM access method of novel anti-collision Download PDFInfo
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- CN106227681B CN106227681B CN201610424253.0A CN201610424253A CN106227681B CN 106227681 B CN106227681 B CN 106227681B CN 201610424253 A CN201610424253 A CN 201610424253A CN 106227681 B CN106227681 B CN 106227681B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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Abstract
The invention belongs to power distribution fields of automation technology, more particularly to a kind of dual port RAM access method of novel anti-collision, multidomain treat-ment is carried out to dual port RAM first, respectively hard real time area and weak projectivity area, corresponding software protocol is formulated, then above-mentioned great Qu is subjected to refinement subregion, and the corresponding data access addresses of each area definition and control are identified, last two CPU is transmitted, and the information of information transmission and CPU2 including CPU1 receives again in the mode that CPU is mutually transmitted.The program is by by twoport RMA multidomain treat-ment and in the way of hardware interrupts, realize the interaction of two sides cpu data information, dependence when relieving CPU operation collision detection to " busy " signal, CPU DSP requirements of type selecting is not only relaxed, but also ensure that the real-time of the information interaction of two sides CPU, reliability.
Description
Technical field
The invention belongs to a kind of access of the dual port RAM of power distribution field of automation technology more particularly to novel anti-collision
Method.
Background technique
The institute distribution terminal DTU that stands is larger due to acquiring data volume, general by the way of dual processors processing, one of CPU
It is responsible for the acquisition process of analog data specially as coprocessor, another CPU handles communication function and human-machine interface function,
Information exchange is carried out by dual port RAM between two CPU.Since dual port RAM requirement of real-time is higher, interaction data amount is big, warp
Often there is two sides CPU while operating collision problem caused by dual port RAM, it is serious to restrict data interactive efficiency.It is presently mainly logical
" busy " signal of CPU detection dual port RAM output is crossed to solve this operation conflict: can be exported when dual port RAM is busy with one's work
One " busy " signal will suspend operation of the side CPU to dual port RAM after either side CPU detects " busy " signal,
Conflict caused by evade two sides CPU while operate dual port RAM.This scheme needs the CPU of two sides all to have access
The ability of " busy " signal, limits the type selecting of CPU, while also having seriously affected the real-time of dual port RAM data interaction.
Summary of the invention
The present invention is directed to above-mentioned problem, devises a kind of " busy " signal for not needing access dual port RAM, that is, can avoid
Two sides CPU operates the dual port RAM access method of the novel anti-collision to conflict caused by dual port RAM simultaneously.
In order to achieve the above object, the technical solution adopted by the present invention is,
A kind of dual port RAM access method of novel anti-collision, which is characterized in that specifically includes the following steps:
1) by the way of address partition, dual port RAM is divided into hard real time area and identical with hard real time plot structure weak
Real-time area, and formulate corresponding software protocol；
2) real-time area is subdivided into down order area, uplink command area and data interaction area again, i.e. hard real time area and weak
Contain above three area in real-time area respectively, and corresponding data access addresses and control mark are all defined to above-mentioned each area；
3) information transmission in CPU is opened, CPU includes the CPU1 and CPU2 that dual port RAM both ends are arranged in, transmission process point
Have that information needs to be transmitted to the lower end side CPU2 and lower end CPU2 is flanked and received the side upper end CPU1 information two parts for the upper end side CPU1,
When the upper end side CPU1 has information to need to be transmitted to the lower end side CPU2, sequentially include the following steps:
A, CPU1 detects whether down order zone state can be used first；
B, if it is available, down order zone state is changed to " information occupancy " mode by CPU1；
C, down order is write down order area by CPU1；
D, the information of downlink is write dual port RAM hard real time data interaction area by CPU1；
E, the state in down order area is changed to " having downlink information " mode by " information occupancy " by CPU1；
F, CPU1 triggers the interruption of the side downlink CPU2；
Lower end CPU2, which is flanked, receives the side upper end CPU1 information, sequentially includes the following steps:
A, CPU2 detects the hardware interrupts from the side CPU1；
B, CPU2 detects whether down order area has data to downlink；
C, if so, down order zone state is changed to " reading " mode by " having downlink information " by CPU2；
D, CPU2 reads the information content in dual port RAM hard real time data interaction area；
E, CPU2 is changed to down order zone state by " reading " " interaction is completed "；
F, two sides cpu data interaction is completed.
Preferably, transmitting between two CPU for mutual information, information is transferred in CPU2 from CPU1 through dual port RAM
As the method being transferred in CPU1 with CPU2 through dual port RAM is.
Preferably, the command area uses double byte mode.
Compared with prior art, the advantages and positive effects of the present invention are,
The program realizes two sides cpu data information by by dual port RAM multidomain treat-ment and in the way of hardware interrupts
Interaction, dependence when relieving CPU operation collision detection to " busy " signal not only relax CPU DSP requirements of type selecting,
And it ensure that the real-time of the information interaction of two sides CPU, reliability.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without any creative labor, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is the dual port RAM block plan in the present invention；
INT is terminal signaling；
Fig. 2 sends data flowchart to the side CPU2 for the side CPU1 in the present invention；
Fig. 3 is that CPU2 flanks receipts data flowchart in the present invention.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawings and examples
The present invention will be further described.It should be noted that in the absence of conflict, in embodiments herein and embodiment
Feature can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
To be implemented using other modes described herein are different from, therefore, the present invention is not limited to the specific of specification is described below
The limitation of embodiment.
Embodiment 1, the present invention provides a kind of dual port RAM access method of novel anti-collision, the present invention primarily directed to
Dual port RAM is divided into hard real time area and weak projectivity area, and make first by the way of address partition by the processing that dual port RAM is made
Determine corresponding software protocol, it is identical in the structure of above-mentioned two information area, in order to be more convenient information transmission, as shown in Figure 1,
Inventor again segments the information area for down order area, uplink command area and data interaction area, and to above-mentioned each Qu Douding
Adopted corresponding data access addresses and control mark.
Specifically once how to realize that the information between two CPU is transmitted using the method mentioned in the present invention below,
The CPU at dual port RAM both ends is respectively CPU1 and CPU2, the transmission between CPU1 and CPU2 be it is mutual, it is of the present invention
Mode be also it is identical, specifically once information is transferred to the implementation process of CPU2 from CPU1 through dual port RAM, in the implementation process
In have including two parts, as shown in Figure 1, first is that the upper end side CPU1 has information to need to be transmitted to the lower end side CPU2, but lower end
The side CPU2 and lower end CPU2, which are flanked, receives the side upper end CPU1 information two parts；Hard real time area two sides CPU is by way of hardware interrupts
Information response is carried out, weak projectivity area two sides CPU carries out information response by way of inquiry.
When the upper end side CPU1 has information to need to be transmitted to the lower end side CPU2, it carries out according to the following steps, such as Fig. 2 institute:
3) information transmission in CPU is opened, CPU includes the CPU1 and CPU2 that dual port RAM both ends are arranged in, transmission process point
Have that information needs to be transmitted to the lower end side CPU2 and lower end CPU2 is flanked and received the side upper end CPU1 information two parts for the upper end side CPU1,
When the upper end side CPU1 has information to need to be transmitted to the lower end side CPU2, sequentially include the following steps:
A, CPU1 detects whether down order zone state can be used first；
B, if it is available, down order zone state is changed to " information occupancy " mode by CPU1；
C, down order is write down order area by CPU1；
D, the information of downlink is write dual port RAM hard real time data interaction area by CPU1；
E, the state in down order area is changed to " having downlink information " mode by " information occupancy " by CPU1；
F, CPU1 triggers the interruption of the side downlink CPU2；
Lower end CPU2, which is flanked, receives the side upper end CPU1 information, carries out according to the following steps, as shown in Figure 3:
A, CPU2 detects the hardware interrupts from the side CPU1；
B, CPU2 detects whether down order area has data to downlink；
C, if so, down order zone state is changed to " reading " mode by " having downlink information " by CPU2；
D, CPU2 reads the information content in dual port RAM hard real time data interaction area；
E, CPU2 is changed to down order zone state by " reading " " interaction is completed "；
F, two sides cpu data interaction is completed.
If the hard real time information of the lower end side CPU2 uplink in need is transmitted to the upper end side CPU1, operating process and hard real time
Info Down is similar, and the main distinction is that relevant information can only be uploaded to the upper end side CPU1 by uplink command area by lower end CPU2.
In order to solve two sides CPU while operate conflict caused by dual port RAM, the command format of command area is using double when design
Byte mode actively initiates side CPU from low address to high address write order；Other side CPU reads from high address to low address and orders
It enables.It requires the description of the two information must be consistent in definition command format, fundamentally solved in this way since two sides conflict is led
The case where dual port RAM operation exception of cause.
Dual port RAM interactive command frame format is as shown in table 1:
Table 1
| Attribute | Length (byte) |
| Command message head 1 | 2 |
| Command message head 2 | 2 |
| Frame head | 2 |
| Length | 2 |
| Command word | 2 |
| Information body length | 2 |
| Verification and | 2 |
Both ends CPU passes through the command message head in sense command area, judges the action behavior of this side CPU next step；Dual port RAM
The description of interactive command message is as shown in table 2:
Table 2
The above described is only a preferred embodiment of the present invention, being not that the invention has other forms of limitations, appoint
What those skilled in the art changed or be modified as possibly also with the technology contents of the disclosure above equivalent variations etc.
It imitates embodiment and is applied to other fields, but without departing from the technical solutions of the present invention, according to the technical essence of the invention
Any simple modification, equivalent variations and remodeling to the above embodiments, still fall within the protection scope of technical solution of the present invention.
Claims (2)
1. a kind of dual port RAM access method of novel anti-collision, which is characterized in that specifically includes the following steps:
1) by the way of address partition, dual port RAM is divided into hard real time area and weak projectivity identical with hard real time plot structure
Area, and formulate corresponding software protocol；
2) real-time area is subdivided into down order area, uplink command area and data interaction area, i.e. hard real time area and weak projectivity again
Contain above three area in area respectively, and corresponding data access addresses and control mark are all defined to above-mentioned each area；
3) information transmission in CPU is opened, CPU includes the CPU1 and CPU2 that dual port RAM both ends are arranged in, and transmission process is divided into
Holding the side CPU1 to have, information needs to be transmitted to the lower end side CPU2 and lower end CPU2 is flanked and received the side upper end CPU1 information two parts,
When the upper end side CPU1 has information to need to be transmitted to the lower end side CPU2, sequentially include the following steps:
A, CPU1 detects whether down order zone state can be used first；
B, if it is available, down order zone state is changed to " information occupancy " mode by CPU1；
C, down order is write down order area by CPU1；
D, the information of downlink is write dual port RAM hard real time data interaction area by CPU1；
E, the state in down order area is changed to " having downlink information " mode by " information occupancy " by CPU1；
F, CPU1 triggers the interruption of the side downlink CPU2；
Lower end CPU2, which is flanked, receives the side upper end CPU1 information, sequentially includes the following steps:
A, CPU2 detects the hardware interrupts from the side CPU1；
B, CPU2 detects whether down order area has data to downlink；
C, if so, down order zone state is changed to " reading " mode by " having downlink information " by CPU2；
D, CPU2 reads the information content in dual port RAM hard real time data interaction area；
E, CPU2 is changed to down order zone state by " reading " " interaction is completed "；
F, two sides cpu data interaction is completed；
The CPU at the dual port RAM both ends is respectively CPU1 and CPU2, the weak projectivity area connecting with the CPU1, with the CPU2
Connection is hard real time area, and the weak projectivity is divided into upper end down order area, upper end uplink command area and upper end data and handed over
Mutual area, the hard real time divide into lower end down order area, lower end uplink command area and lower end data interaction area；
It is transmitted between two CPU for mutual information, information is transferred in CPU2 from CPU1 through dual port RAM and CPU2 is through twoport
It is the same that RAM, which is transferred to the method in CPU1,.
2. a kind of dual port RAM access method of novel anti-collision according to claim 1, which is characterized in that the order
Area uses double byte mode.
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| CN113253723A (en) * | 2021-04-30 | 2021-08-13 | 江苏金陵智造研究院有限公司 | AGV vehicle-mounted controller |
| CN113626362A (en) * | 2021-07-07 | 2021-11-09 | 北京控制与电子技术研究所 | CPCI bus and control circuit communication interface based on dual-port RAM |
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| US5860021A (en) * | 1997-04-24 | 1999-01-12 | Klingman; Edwin E. | Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel |
| US6122713A (en) * | 1998-06-01 | 2000-09-19 | National Instruments Corporation | Dual port shared memory system including semaphores for high priority and low priority requestors |
| CN1119004C (en) * | 1999-01-19 | 2003-08-20 | 深圳市中兴通讯股份有限公司 | Method for transferring messages with dual control words |
| CN100543873C (en) * | 2006-11-23 | 2009-09-23 | 中兴通讯股份有限公司 | A kind of apparatus and method that realize data rate transition based on dual port RAM |
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| CN101398804A (en) * | 2007-09-29 | 2009-04-01 | 深圳迈瑞生物医疗电子股份有限公司 | Equipment with printing drive function and method for implementing printing drive |
| CN101655824A (en) * | 2009-08-25 | 2010-02-24 | 北京广利核系统工程有限公司 | Implementation method of double-port RAM mutual exclusion access |
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Application publication date: 20161214 Assignee: Zhongguancun Technology Leasing Co., Ltd Assignor: BEIJING HEXINRUITONG ELECTRIC POWER TECHNOLOGY Co.,Ltd. Contract record no.: X2021980012290 Denomination of invention: A new anti-collision dual port RAM access method Granted publication date: 20190823 License type: Exclusive License Record date: 20211112 |
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Denomination of invention: A new anti-collision dual port RAM access method Effective date of registration: 20211115 Granted publication date: 20190823 Pledgee: Zhongguancun Technology Leasing Co., Ltd Pledgor: BEIJING HEXINRUITONG ELECTRIC POWER TECHNOLOGY Co.,Ltd. Registration number: Y2021980012578 |