CN106227681B - A kind of dual port RAM access method of novel anti-collision - Google Patents
A kind of dual port RAM access method of novel anti-collision Download PDFInfo
- Publication number
- CN106227681B CN106227681B CN201610424253.0A CN201610424253A CN106227681B CN 106227681 B CN106227681 B CN 106227681B CN 201610424253 A CN201610424253 A CN 201610424253A CN 106227681 B CN106227681 B CN 106227681B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Description
Attribute | Length (byte) |
Command message head 1 | 2 |
Command message head 2 | 2 |
Frame head | 2 |
Length | 2 |
Command word | 2 |
Information body length | 2 |
Verification and | 2 |
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201610424253.0A CN106227681B (en) | 2016-06-15 | 2016-06-15 | A kind of dual port RAM access method of novel anti-collision |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201610424253.0A CN106227681B (en) | 2016-06-15 | 2016-06-15 | A kind of dual port RAM access method of novel anti-collision |
Publications (2)
Publication Number | Publication Date |
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CN106227681A CN106227681A (en) | 2016-12-14 |
CN106227681B true CN106227681B (en) | 2019-08-23 |
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Family Applications (1)
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CN201610424253.0A Active CN106227681B (en) | 2016-06-15 | 2016-06-15 | A kind of dual port RAM access method of novel anti-collision |
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CN (1) | CN106227681B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111679599B (en) * | 2020-05-22 | 2022-01-25 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
CN113253723A (en) * | 2021-04-30 | 2021-08-13 | 江苏金陵智造研究院有限公司 | AGV vehicle-mounted controller |
CN113626362A (en) * | 2021-07-07 | 2021-11-09 | 北京控制与电子技术研究所 | CPCI bus and control circuit communication interface based on dual-port RAM |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5860021A (en) * | 1997-04-24 | 1999-01-12 | Klingman; Edwin E. | Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel |
US6122713A (en) * | 1998-06-01 | 2000-09-19 | National Instruments Corporation | Dual port shared memory system including semaphores for high priority and low priority requestors |
CN1119004C (en) * | 1999-01-19 | 2003-08-20 | 深圳市中兴通讯股份有限公司 | Method for transferring messages with dual control words |
CN100543873C (en) * | 2006-11-23 | 2009-09-23 | 中兴通讯股份有限公司 | A kind of apparatus and method that realize data rate transition based on dual port RAM |
CN100511207C (en) * | 2007-02-14 | 2009-07-08 | 中兴通讯股份有限公司 | Communication method between two processors |
CN101398804A (en) * | 2007-09-29 | 2009-04-01 | 深圳迈瑞生物医疗电子股份有限公司 | Equipment with printing drive function and method for implementing printing drive |
CN101655824A (en) * | 2009-08-25 | 2010-02-24 | 北京广利核系统工程有限公司 | Implementation method of double-port RAM mutual exclusion access |
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2016
- 2016-06-15 CN CN201610424253.0A patent/CN106227681B/en active Active
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Legal Events
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GR01 | Patent grant | ||
GR01 | Patent grant | ||
EE01 | Entry into force of recordation of patent licensing contract | ||
EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20161214 Assignee: Zhongguancun Technology Leasing Co., Ltd Assignor: BEIJING HEXINRUITONG ELECTRIC POWER TECHNOLOGY Co.,Ltd. Contract record no.: X2021980012290 Denomination of invention: A new anti-collision dual port RAM access method Granted publication date: 20190823 License type: Exclusive License Record date: 20211112 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A new anti-collision dual port RAM access method Effective date of registration: 20211115 Granted publication date: 20190823 Pledgee: Zhongguancun Technology Leasing Co., Ltd Pledgor: BEIJING HEXINRUITONG ELECTRIC POWER TECHNOLOGY Co.,Ltd. Registration number: Y2021980012578 |