CN103605628A - PCI-E-based method and device for achieving command interaction between master equipment and slave equipment - Google Patents

PCI-E-based method and device for achieving command interaction between master equipment and slave equipment Download PDF

Info

Publication number
CN103605628A
CN103605628A CN201310633319.3A CN201310633319A CN103605628A CN 103605628 A CN103605628 A CN 103605628A CN 201310633319 A CN201310633319 A CN 201310633319A CN 103605628 A CN103605628 A CN 103605628A
Authority
CN
China
Prior art keywords
pci
card
command
bus
bus access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310633319.3A
Other languages
Chinese (zh)
Inventor
何三波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maipu Communication Technology Co Ltd
Original Assignee
Maipu Communication Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Maipu Communication Technology Co Ltd filed Critical Maipu Communication Technology Co Ltd
Priority to CN201310633319.3A priority Critical patent/CN103605628A/en
Publication of CN103605628A publication Critical patent/CN103605628A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Bus Control (AREA)

Abstract

The invention discloses a PCI-E-based method and device for achieving command interaction between master equipment and slave equipment. The PCI-E-based method for achieving the command interaction between the master equipment and the slave equipment comprises the steps that PCI-E bus access areas are set in a master card and a slave card respectively; command information is input into the master card, and the command information is written into the PCI-E bus access area in the slave card when it is detected that the command information is input into the master card; a CPU of the slave card reads out the command information and then processes the command information, and a processing result is written into the PCI-E bus access area of the master card through a PCI-E bus after processing of the command information is completed; the processing result is output after being detected by a CPU of the master card. The PCI-E-based method and system for achieving the command interaction between the master equipment and the slave equipment are easy to realize, no complicated protocol is needed, and the stability of a computer system is not affected.

Description

Command interaction method based between PCI-E master-slave equipment and system
Technical field
The invention belongs to data communication technology field, specifically a kind of command interaction method based between PCI-E master-slave equipment and the design of system.
Background technology
PCI-E(PCI Express) be bus interface of new generation, it has adopted at present popular point-to-point connected in series in the industry, compared with PCI(Peripheral Component Interconnect, peripheral element expansion interface) and the shared parallel architecture of more early stage computer bus, each equipment has the special use of oneself to connect, do not need to whole bus request bandwidth, and data transmission rate can be brought up to a very high frequency, reach the high bandwidth that PCI can not provide.In the computer system of the PCI-E master-slave equipment consisting of PCI-E bus, master-slave equipment can be respectively user management interface is provided, for example: be respectively user console management mouthful is provided, user can manage mouth by console and respectively master-slave equipment be managed.
The computer system forming due to PCI-E master-slave equipment is all still an equipment physically in logic, user manages respectively not only unreasonable but also bother to master-slave equipment, therefore, in described PCI-E master-slave equipment computer system, only need main equipment to provide management interface to user, user also can manage from equipment by this interface.
From data communication angle, consider, can connect respectively an Ethernet card at master-slave equipment, and build IP network interface, main equipment is by ICP/IP protocol access slave.But the method needs all to move ICP/IP protocol on master-slave equipment, and hardware formation or the software in computer system forms the complicacy that has all increased system like this.
Summary of the invention
Technical matters to be solved by this invention is in order to overcome in prior art all comparatively complicated shortcomings and a kind of command interaction method and system based between PCI-E master-slave equipment is provided of hardware and software that between PCI-E master-slave equipment, communication exists.
The technical scheme that the present invention solves its technical matters employing is: the command interaction method based between PCI-E master-slave equipment, comprises the steps:
S1, in master and slave card, distribute respectively a region of memory as PCI-E bus access region;
S2, in main card input command information, after the CPU of main card has detected command information input, by PCI-E bus, this command information is write to from the PCI-E bus access region of card;
S3, from card CPU sense command information command information is processed, after finishing dealing with, by PCI-E bus, result is write to the PCI-E bus access region of main card;
The CPU of S4, main card has detected after result, output result.
Further, described master and slave card comprises CPU and internal memory thereof, the CPU of main card with from the CPU of card, by PCI-E bus, be connected, from the CPU of card, by the PCI-E bus access region of PCI-E bus access main card, the CPU of main card is the PCI-E bus access region from card by PCI-E bus access.
Further, thereby the described CPU from card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region that main card distributes internal memory, thereby the CPU of described main card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region of distributing from be stuck in internal memory.
Further, the PCI-E bus access region of described main card comprises two fields: command execution attribute field and order output information field;
When if command execution attribute field is the first parameter, represent execution of order; If during the second parameter, represent command execution success; If during the 3rd parameter, represent command execution failure;
Output information when order output information represents from blocking command execution.
Further, the described PCI-E bus access region from card comprises two fields: command field and order attribute field;
When if order attribute field is the 4th parameter, represent that main card extremely completes from the PCI-E bus access region of card by PCI-E bus write order; If during the 5th parameter, represent that main card does not extremely complete from the PCI-E bus access region of card by PCI-E bus write order;
Command field represents to write to from the command information in the PCI-E bus access region of card by main card.
Further, described step S2 is specially: the CPU of main card detects after the command information of input, the command execution attribute field arranging in the PCI-E bus access region of main card is the first parameter, and command information is write to the command field in the command area from the PCI-E bus access region of card by PCI-E bus, by PCI-E bus, writing from the order attribute field of card is again the 4th parameter, wait command execution result.
Further, described step S3 is specially: when from card initialization, create an order and keep marquis's task, described order is kept marquis's task for detection of the order attribute field the PCI-E bus access region from card;
When order is kept marquis's task when order attribute field being detected and being the 4th parameter, sense command information by the command field from card, and command information is resolved;
If command analysis failure, output command is resolved failure information in the order output information field in the PCI-E bus access region of main card, then is the 3rd parameter by PCI-E bus write order execute flag field; If command analysis success, fill order, and the PCI-E bus of passing through of the output information of command execution is outputed to order output information field, then be the second parameter by PCI-E bus write order execute flag field.
The present invention also provides the system of the command interaction based between PCI-E master-slave equipment for technical solution problem, specifically comprise: main card, the PCI-E bus from blocking and connecting master and slave card, described main card comprises command input unit, order output unit, from card, comprises that command analysis and performance element, command execution results are redirected unit; Region of memory in described master and slave card all comprises a PCI-E bus access region; Described command input unit writes to this command information from the PCI-E bus access region of card for input command information and by PCI-E bus; Described command analysis and performance element are processed command information for after sense command information; Described command execution results is redirected unit for result being write to result by PCI-E bus to the PCI-E bus access region of main card; Described order output unit is used for exporting result.
Further, described master and slave card comprises CPU and internal memory thereof, the CPU of main card with from the CPU of card, by PCI-E bus, be connected, from the CPU of card, by the PCI-E bus access region of PCI-E bus access main card, the CPU of main card is the PCI-E bus access region from card by PCI-E bus access.
Further, thereby the described CPU from card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region that main card distributes internal memory, thereby the CPU of described main card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region of distributing from be stuck in internal memory.
Beneficial effect of the present invention: a kind of command interaction method and system based between PCI-E master-slave equipment of the present invention, the method is based on PCI-E bus and PCI-E master-slave equipment, the hardware resource that does not need other, from equipment, do not need to move ICP/IP protocol yet, thereby can not increase the complicacy of hardware and software; The realization of the method and system is simultaneously comparatively simple, does not need complicated agreement, does not affect the stability of computer system.
Accompanying drawing explanation
Fig. 1 is the FB(flow block) of a kind of command interaction method based between PCI-E master-slave equipment of the embodiment of the present invention;
Fig. 2 is the structured flowchart of a kind of command interaction system based between PCI-E master-slave equipment of the embodiment of the present invention;
Fig. 3 is the block diagram of a kind of shell-command reciprocal process based between PCI-E master-slave equipment of the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the invention will be further elaborated.
The FB(flow block) that is illustrated in figure 1 a kind of command interaction method based between PCI-E master-slave equipment of the embodiment of the present invention, it specifically comprises the steps:
S1, in master and slave card, distribute respectively a region of memory as PCI-E bus access region;
S2, in main card input command information, after the CPU of main card has detected command information input, by PCI-E bus, this command information is write to from the PCI-E bus access region of card;
S3, from card CPU sense command information command information is processed, after finishing dealing with, by PCI-E bus, result is write to the PCI-E bus access region of main card;
The CPU of S4, main card has detected after result, output result.
Wherein, master and slave card comprises CPU and internal memory thereof, and the CPU of main card is as PCI-E main equipment, from the CPU of card as PCI-E from equipment, from the CPU of card, be controlled by the CPU of main card, the CPU of main card with from the CPU blocking, by PCI-E bus, be connected.From the CPU of card, by the PCI-E bus access region of PCI-E bus access main card, the CPU of main card is the PCI-E bus access region from card by PCI-E bus access.Thereby from the CPU of card, by the address space of read-write PCI-E bus, read and write the PCI-E bus access region that main card distributes internal memory, thereby the CPU of main card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region of distributing from be stuck in internal memory.
In described step S2, the CPU of main card detects the command information of input by command input unit, and the character string of command information is write to from the PCI-E bus access region of card by PCI-E bus.
In described step S3, from card, adopt an order task of waiting for to read by main card and write from the command information in the PCI-E bus access region of card, and this command information is resolved and carried out.Be specially: when there being command information to be written to from the PCI-E bus access region of card from main card, task is waited in the order of activation from card, the described order task of waiting for is read this command information, and empty from the content in the PCI-E bus access region of card simultaneously, again this command information is resolved and carried out, the order of execution result in CPU is redirected unit and by PCI-E bus, writes to the PCI-E bus access region of main card.
Simultaneously, based on said method, the present invention also provides a kind of command interaction system based between PCI-E master-slave equipment, specifically comprise: main card, the PCI-E bus from blocking and connecting master and slave card, described main card comprises command input unit, order output unit, from card, comprises that command analysis and performance element, command execution results are redirected unit; Region of memory in described master and slave card all comprises a PCI-E bus access region; Described command input unit writes to this command information from the PCI-E bus access region of card for input command information and by PCI-E bus; Described command analysis and performance element are processed command information for after sense command information; Described command execution results is redirected unit for result being write to result by PCI-E bus to the PCI-E bus access region of main card; Described order output unit is used for exporting result.
For those skilled in the art can understand and implement technical solution of the present invention, below in conjunction with specific embodiments the command interaction method and the system that the present invention is based between PCI-E master-slave equipment are elaborated:
Be illustrated in figure 3 and take the reciprocal process of the order of shell-command between example explanation PCI-E master-slave equipment, wherein the CPU of master and slave card is connected by PCI-E bus, for simplified characterization, PCI-E bus access region on this definition main card is region A, PCI-E bus access region from card is B, main card can pass through the region B of PCI-E bus access from card, and meanwhile, the CPU from card also can be by region A on PCI-E bus access main card.
Region A comprises two fields: command execution attribute field and order output information field; When if command execution attribute field is the first parameter, represent that order do not carry out, if during the second parameter, represent command execution success; If during the 3rd parameter, represent command execution failure; Output information when order output information represents that from blocking shell-command is carried out.
Region B comprises two fields: command field and order attribute field; If order attribute field while being the 4th parameter, represents main card and complete to region B by PCI-E bus write order, if when order attribute field is the 5th parameter, represent that main card does not complete to region B by PCI-E bus write order; Command field represents to write to by main card the shell-command of region B.
Concrete flow process is: the command input unit on main card waits user and inputs shell-command, detect after the shell-command of user's input, command execution attribute field in the A of setting area is the first parameter, and shell-command is write to the command field in the B of region by PCI-E bus, then the order attribute field of writing in the B of region by PCI-E bus is the 4th parameter, then waits for shell-command execution result; Command execution attribute field in reading field A again, if command execution success or failure, output command runs succeeded or failed information, and output command is carrying out from card the information of exporting.
From blocking, when initialization, create a shell and keep marquis's task, described shell keeps marquis's task for detection of the shell-command attribute field in the B of region; When shell keeps marquis's task when order attribute field being detected and being the 4th parameter, in the command field from the B of region, read shell-command, shell-command is resolved;
If command analysis failure, output command is resolved failure information in the order output information field in the A of region, then is the 3rd parameter by PCI-E bus write order execute flag field; If command analysis success, fill order, and by the output information of command execution by PCI-E, output to the order output information field in the A of region, then be the second parameter by PCI-E bus write order execute flag field.
Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not depart from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (10)

1. the command interaction method based between PCI-E master-slave equipment, is characterized in that, comprises the steps:
S1, in master and slave card, distribute respectively a region of memory as PCI-E bus access region;
S2, in main card input command information, after the CPU of main card has detected command information input, by PCI-E bus, this command information is write to from the PCI-E bus access region of card;
S3, from card CPU sense command information command information is processed, after finishing dealing with, by PCI-E bus, result is write to the PCI-E bus access region of main card;
The CPU of S4, main card has detected after result, output result.
2. the method for claim 1, it is characterized in that, described master and slave card comprises CPU and internal memory thereof, the CPU of main card with from card CPU by PCI-E bus, be connected, from the CPU of card, by the PCI-E bus access region of PCI-E bus access main card, the CPU of main card is the PCI-E bus access region from card by PCI-E bus access.
3. method as claimed in claim 2, it is characterized in that, thereby the described CPU from card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region that main card distributes internal memory, thereby the CPU of described main card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region of distributing from be stuck in internal memory.
4. the method for claim 1, is characterized in that, the PCI-E bus access region of described main card comprises two fields: command execution attribute field and order output information field;
When if command execution attribute field is the first parameter, represent execution of order; If during the second parameter, represent command execution success; If during the 3rd parameter, represent command execution failure;
Output information when order output information represents from blocking command execution.
5. method as claimed in claim 4, is characterized in that, the described PCI-E bus access region from card comprises two fields: command field and order attribute field;
When if order attribute field is the 4th parameter, represent that main card extremely completes from the PCI-E bus access region of card by PCI-E bus write order; If during the 5th parameter, represent that main card does not extremely complete from the PCI-E bus access region of card by PCI-E bus write order;
Command field represents to write to from the command information in the PCI-E bus access region of card by main card.
6. method as claimed in claim 5, it is characterized in that, described step S2 is specially: the CPU of main card detects after the command information of input, the command execution attribute field arranging in the PCI-E bus access region of main card is the first parameter, and command information is write to the command field in the command area from the PCI-E bus access region of card by PCI-E bus, by PCI-E bus, writing from the order attribute field of card is again the 4th parameter, wait command execution result.
7. method as claimed in claim 6, is characterized in that, described step S3 is specially: when from card initialization, create an order and keep marquis's task, described order is kept marquis's task for detection of the order attribute field the PCI-E bus access region from card;
When order is kept marquis's task when order attribute field being detected and being the 4th parameter, sense command information by the command field from card, and command information is resolved;
If command analysis failure, output command is resolved failure information in the order output information field in the PCI-E bus access region of main card, then is the 3rd parameter by PCI-E bus write order execute flag field; If command analysis success, fill order, and the PCI-E bus of passing through of the output information of command execution is outputed to order output information field, then be the second parameter by PCI-E bus write order execute flag field.
8. the command interaction system based between PCI-E master-slave equipment, it is characterized in that, specifically comprise: main card, the PCI-E bus from blocking and connecting master and slave card, described main card comprises command input unit, order output unit, from card, comprises that command analysis and performance element, command execution results are redirected unit; Region of memory in described master and slave card all comprises a PCI-E bus access region; Described command input unit writes to this command information from the PCI-E bus access region of card for input command information and by PCI-E bus; Described command analysis and performance element are processed command information for after sense command information; Described command execution results is redirected unit for result being write to result by PCI-E bus to the PCI-E bus access region of main card; Described order output unit is used for exporting result.
9. system as claimed in claim 8, it is characterized in that, described master and slave card comprises CPU and internal memory thereof, the CPU of main card with from card CPU by PCI-E bus, be connected, from the CPU of card, by the PCI-E bus access region of PCI-E bus access main card, the CPU of main card is the PCI-E bus access region from card by PCI-E bus access.
10. system as claimed in claim 9, it is characterized in that, thereby the described CPU from card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region that main card distributes internal memory, thereby the CPU of described main card reads and writes by the address space of read-write PCI-E bus the PCI-E bus access region of distributing from be stuck in internal memory.
CN201310633319.3A 2013-11-29 2013-11-29 PCI-E-based method and device for achieving command interaction between master equipment and slave equipment Pending CN103605628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310633319.3A CN103605628A (en) 2013-11-29 2013-11-29 PCI-E-based method and device for achieving command interaction between master equipment and slave equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310633319.3A CN103605628A (en) 2013-11-29 2013-11-29 PCI-E-based method and device for achieving command interaction between master equipment and slave equipment

Publications (1)

Publication Number Publication Date
CN103605628A true CN103605628A (en) 2014-02-26

Family

ID=50123857

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310633319.3A Pending CN103605628A (en) 2013-11-29 2013-11-29 PCI-E-based method and device for achieving command interaction between master equipment and slave equipment

Country Status (1)

Country Link
CN (1) CN103605628A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105335330A (en) * 2015-12-09 2016-02-17 浪潮电子信息产业股份有限公司 Micro server cluster system based on master-slave architecture
CN113055387A (en) * 2021-03-15 2021-06-29 西安热工研究院有限公司 Servo master-slave card communication protocol for steam turbine
WO2022100148A1 (en) * 2020-11-16 2022-05-19 北京锐安科技有限公司 Backplane communication device and control method therefor, and storage medium

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090037609A1 (en) * 2007-07-30 2009-02-05 Riley Dwight D Middle management of input/output in server systems
CN101527735A (en) * 2009-04-07 2009-09-09 上海许继电气有限公司 Multi-serial port data communication card equipment based on CPCI bus and method thereof
CN101872335A (en) * 2010-03-05 2010-10-27 杭州海康威视数字技术股份有限公司 CPU console redirecting method and system and CPUs
CN101937326A (en) * 2010-08-31 2011-01-05 广东威创视讯科技股份有限公司 Multi-CPU parallel video processing system, cascade system and method thereof
US20120054557A1 (en) * 2010-08-27 2012-03-01 Hon Hai Precision Industry Co., Ltd. System and method for testing peripheral component interconnect express switch
CN102567944A (en) * 2012-03-09 2012-07-11 中国人民解放军信息工程大学 Computed tomography (CT) image reconstruction hardware accelerating method based on field programmable gate array (FPGA)
CN102855208A (en) * 2011-06-30 2013-01-02 杭州海康威视数字技术股份有限公司 System and method for achieving file interaction
US20130073767A1 (en) * 2010-06-23 2013-03-21 International Business Machines Corporation Input/output (i/o) expansion response processing in a peripheral component interconnect express (pcie) environment

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090037609A1 (en) * 2007-07-30 2009-02-05 Riley Dwight D Middle management of input/output in server systems
CN101527735A (en) * 2009-04-07 2009-09-09 上海许继电气有限公司 Multi-serial port data communication card equipment based on CPCI bus and method thereof
CN101872335A (en) * 2010-03-05 2010-10-27 杭州海康威视数字技术股份有限公司 CPU console redirecting method and system and CPUs
US20130073767A1 (en) * 2010-06-23 2013-03-21 International Business Machines Corporation Input/output (i/o) expansion response processing in a peripheral component interconnect express (pcie) environment
US20120054557A1 (en) * 2010-08-27 2012-03-01 Hon Hai Precision Industry Co., Ltd. System and method for testing peripheral component interconnect express switch
CN101937326A (en) * 2010-08-31 2011-01-05 广东威创视讯科技股份有限公司 Multi-CPU parallel video processing system, cascade system and method thereof
CN102855208A (en) * 2011-06-30 2013-01-02 杭州海康威视数字技术股份有限公司 System and method for achieving file interaction
CN102567944A (en) * 2012-03-09 2012-07-11 中国人民解放军信息工程大学 Computed tomography (CT) image reconstruction hardware accelerating method based on field programmable gate array (FPGA)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105335330A (en) * 2015-12-09 2016-02-17 浪潮电子信息产业股份有限公司 Micro server cluster system based on master-slave architecture
WO2022100148A1 (en) * 2020-11-16 2022-05-19 北京锐安科技有限公司 Backplane communication device and control method therefor, and storage medium
CN113055387A (en) * 2021-03-15 2021-06-29 西安热工研究院有限公司 Servo master-slave card communication protocol for steam turbine
CN113055387B (en) * 2021-03-15 2023-03-17 西安热工研究院有限公司 Communication method for servo master-slave cards of steam turbine

Similar Documents

Publication Publication Date Title
US10282192B1 (en) Updating device code through a bus
CN101983365B (en) Converting resets in shared i/o system
DE112016004300T5 (en) METHOD, DEVICE AND SYSTEM FOR ASSIGNING CACHE USING A TRAFFIC CLASS
CN103180817A (en) Storage expansion apparatus and server
DE102019109130A1 (en) SYSTEM, METHOD AND EQUIPMENT FOR DVSEC FOR AN EFFICIENT PERIPHERAL DEVICE MANAGEMENT
US8561064B2 (en) Retaining ownership of a virtual function while an adapter is replaced
US9026698B2 (en) Apparatus, system and method for providing access to a device function
US9448934B2 (en) Affinity group access to global data
CN203930811U (en) A kind of IO board of supporting NCSI
CN104123194A (en) Communication structure and method for kernel mode and user mode
CN109656844B (en) AT24xx EEPROM driving method and device
CN103649923A (en) NUMA system memory mirror impage configuration method, removing method, system and major node
CN103605628A (en) PCI-E-based method and device for achieving command interaction between master equipment and slave equipment
CN107209725A (en) Method, processor and the computer of processing write requests
CN106844263B (en) Configurable multiprocessor-based computer system and implementation method
CN105359122A (en) Enhanced data transfer in multi-CPU systems
CN105677606B (en) The hot-plug method and bus unit of bus apparatus
CN104461941B (en) A kind of memory system framework and management method
DE102022129397A1 (en) ACCELERATOR FABRIC FOR DISCREET GRAPHICS
CN105528319A (en) FPGA-based accelerator card and acceleration method thereof
WO2015035891A1 (en) Patching method, device, and system
CN103577382A (en) Method and device for configuring node controller
KR20180023543A (en) Apparatus and method for providing memory via serial communication
CN111427813A (en) Inter-core communication method based on serial port, terminal and storage medium
US9251101B2 (en) Bitmap locking using a nodal lock

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20140226