DE102019109130A1 - SYSTEM, METHOD AND EQUIPMENT FOR DVSEC FOR AN EFFICIENT PERIPHERAL DEVICE MANAGEMENT - Google Patents

Abstract

Aspects of the embodiments include systems, methods, apparatus, and computer program products for receiving, from the downstream component, an enhanced capability display; Determining, from the display, one or more configuration parameters for the downstream component; Applying the one or more configuration parameters and performing data signal or control signal transfers over the PCIe-compliant connection with the downstream component based at least in part on the one or more applied configuration parameters. The advanced features may be indicated by a definition of the advanced DVSEC function received from a downstream device. The advanced features of the downstream component may indicate the number of buses, the port type, the extensibility, the status of the D3Cold support, the host router indicator, and / or the requirements for safely ejecting the downstream component.

Description

BACKGROUND

Circuits can be used to provide communication between various devices in a system using some type of interconnect mechanism. A typical communication protocol for communication interconnections between devices in a computer system is a Peripheral Component Interconnect Express (PCI Express ™ (PCIe ^™ )) communication protocol. This communication protocol is an example of an input / output (I / O) switching system for loading / storing. The communication between the devices is usually performed serially according to this protocol at very high speeds.

list of figures

• 1 Figure 1 illustrates an embodiment of a block diagram for a computing system that includes a multicore processor.
• 2 FIG. 10 is a schematic illustration of an exemplary Peripheral Component Interconnect Express (PCIe) interconnect architecture according to embodiments of the present disclosure. FIG.
• 3 FIG. 10 is a schematic block diagram of a connected system that includes a hierarchy of a device connected to a host through a PCIe compliant connection, in accordance with embodiments of the present disclosure.
• 4 FIG. 10 is a schematic illustration of a definition of DVSEC functions that includes one or more attribute hint bits, according to embodiments of the present disclosure.
• 5 FIG. 10 is a process flow diagram for a host device for implementing one or more attributes of a downstream component based on a definition of DVSEC functions in accordance with embodiments of the present disclosure.
• 6 Figure 1 illustrates an embodiment of a computing system that includes a wiring architecture.
• 7 Figure 1 illustrates one embodiment of a circuit architecture including a layered stack.
• 8th FIG. 12 illustrates an embodiment of a request or packet to be created or received within an interconnect architecture.
• 9 illustrates an embodiment of a transceiver pair for a circuit architecture.
• 10 Figure 12 illustrates another embodiment of a block diagram for a computing system including a processor.
• 11 Figure 1 illustrates an embodiment of a computing system block including multiple processor sockets.
• 12 illustrates another embodiment of a block diagram for a computing system.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth, such as examples of specific processor types and system configurations, specific hardware structures, specific architectural and micro-architectural details, specific register configurations, specific types of instructions, specific system components, specific measurements / heights, specific processor pipeline stages and operation, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known components or techniques have been described, such as specific and alternative processor architectures, specific logic circuits / code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific fabrication techniques and materials, specific compiler techniques. Implementations, specific expressions of algorithms in code, specific shutdown and gate techniques / logic, and other specific operational details of computer systems are not described in detail to avoid unnecessarily obscuring the present invention.

Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as computer platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks ™. And they can also be used in other devices, such as handheld devices, tablets, other thin notebooks, system-on-a-chip (SOC) devices, and other embedded applications. Some examples of handheld devices include cell phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, digital signal processor (DSP), system-on-a-chip, network computer (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or the like any other system that can perform the functions and operations taught below. Moreover, the devices, methods, and systems described herein are not limited to physical computing devices, but may also address software optimizations for energy conservation and efficiency. As will be readily apparent in the following description, the methods, devices, and systems described herein (whether hardware, firmware, software, or a combination thereof) are indispensable for a performance-balanced "green technology" future.

With the development of computing systems, the components become more complex. As a result, the interconnect architecture for coupling and communicating between the components also experiences increasing complexity to ensure that bandwidth requirements for optimal component operation are met. Furthermore, different market segments require different aspects of interconnect architectures to meet the respective market requirements. For example, servers require higher performance, although the mobile ecosystem is sometimes able to sacrifice overall power savings performance. Yet, it is a singular task of most structures to provide the highest possible performance with maximum power savings. In the following, a number of interconnections are discussed that would potentially benefit from aspects of the invention described herein.

With reference to 1 Figure 1 illustrates one embodiment of a block diagram for a multicore processor computing system. A processor 100 includes any processor or processing device such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a hand-held processor, an application processor, a coprocessor, a system-on-a-chip (SOC), or a another device for executing code. The processor 100 in one embodiment, includes at least two cores, namely core 101 and 102 , which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, the processor can 100 include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a kernel, and / or any other element associated therewith is able to hold a state for a processor, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware that is capable of being independently assigned to a code, such as a software thread, an operating system, an application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit that potentially includes any number of other processing elements, such as cores or hardware threads.

One core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, with each independently maintained architectural state associated with at least some dedicated execution resources. Unlike cores, a hardware thread typically refers to any logic that resides on an integrated circuit that is capable of maintaining an independent architectural state, with the independently maintained architectural states sharing access to execution resources. As can be seen, the boundary between the nomenclature of a hardware thread and a kernel overlaps when certain resources are shared and others are for an architectural state. Nevertheless, an operating system often views a core and a hardware thread as a single logical processor, and the operating system is able to schedule operations on each logical processor individually.

The physical processor 100 , as in 1 illustrates, includes two cores, namely core 101 and 102 , on. Here are core 101 and 102 considered as symmetric cores, that is cores with the same configurations and functional units and / or the same logic. In another embodiment, the core closes 101 an out-of-order processor core while the core 102 includes an in-order processor core. The cores 101 and 102 however, may be made up individually of any type of core, such as a native kernel, a software-managed kernel, a kernel adapted to execute a native instruction set architecture (ISA), a kernel used to implement a translated instruction set architecture , ISA), a co-developed core or another known core. In a heterogeneous core environment (that is, asymmetric cores), one form of translation, such as a binary translation, can be used to plan or execute code on one or both cores. However, for further discussion, the functional units that are in the kernel 101 as described more fully below, as the units in the core 102 operate in a similar manner as in the illustrated embodiment.

As shown, the core closes 101 two hardware threads 101 and 101b one that also has hardware thread slots 101 and 101b can be called. Software entities, such as an operating system, thus see the processor 100 in one embodiment, potentially as four separate processors, that is, four logical processors or processing elements capable of executing four software threads concurrently. As mentioned above, a first thread is architectural state registers 101 Assigned is a second thread architecture state registers 101b associated with a third thread may be architectural state registers 102 and may be a fourth thread architecture state registers 102b be assigned. Here, each of the architecture state registers ( 101 . 101b . 102 and 102b) Processing elements, thread slots or thread units, as described above, are called. As illustrated, the architectural state registers 101 in architectural state registers 101b such that individual architectural states / contexts for the logical processor 101 and the logical processor 101b can be stored. In the core 101 can use other smaller resources, such as instruction pointers and rename logic, in a referrer and renamer block 130 , also for the threads 101 and 101b be replicated. Some resources, such as reorder buffers in a reorder / reset unit 135 , ILTB 120 , Load / store buffers and queues, can be shared by partitioning. Other resources, such as internal general purpose registers, page table base registers, low level data cache and data TLB 115 , Execution unit (s) 140 and sections of the out-of-order unit 135 potentially fully shared.

The processor 100 often includes other resources that may be fully shared, partitioned, or provided by / for processing elements. In 1 FIG. 3 illustrates one embodiment of a purely exemplary processor having logical unit logic / resources of a processor. It should be noted that a processor may include or omit any of these functional units as well as include other known functional units, logic, or firmware, not shown. As illustrated, the core concludes 101 a simplified, representative out-of-order (OOO) processor core. However, an in-order processor may be used in various embodiments. The OOO kernel closes a jump destination buffer 120 to predict hops to be made / received, and an Instruction Translation Buffer (I-TLB) 120 to store address translation entries for commands.

The core 101 further includes a decoding module 125 one with the polling unit 120 is coupled to decode retrieved elements. In one embodiment, fetch logic includes individual sequencers, each one of the thread slots 101 . 101b assigned. Usually, the core is 101 associated with a first ISA, the commands that are on the processor 100 executable, defined / specified. Often, machine code instructions associated with the first ISA include a portion of the instruction (called an opcode) that references / specifies an instruction to be performed or an operation to be performed. The decoding logic 125 includes circuits which recognize these instructions based on their opcodes and pass the decoded instructions in the pipeline for processing as defined by the first ISA. As discussed in more detail below, the decoders close 125 in one embodiment, logic adapted or adapted to recognize specific instructions, such as a transaction instruction. As a result of the recognition by the decoders 125 leads the architecture or the core 101 specific, predefined actions to perform tasks associated with the appropriate command. It is important to note that any of the tasks, blocks, operations, and methods described herein are in response to a single or multiple commands can be performed; some of them may be new or old commands. It should be noted that decoder 126 in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, the decoders recognize 126 in a heterogeneous core environment, a second ISA (either a subset of the first ISA or a different ISA).

In one example, the referrer and renamer block contains 130 an allocator for reserving resources, such as register files for storing instruction processing results. The threads 101 and 101b however, they are potentially capable of out-of-order execution, with the assignee and renamer block 130 also reserves other resources, such as reorder buffers, to track command results. The unit 130 may also include a register renamer to transfer program / instruction reference registers to other registers in the processor 100 rename. The reorganization / withdrawal unit 135 includes components such as the above-mentioned reorder buffers, load buffers, and memory buffers to support out-of-order execution and later in-order retraction of out-of-order commands.

A scheduler and execution unit (s) block 140 In one embodiment, includes a scheduler to schedule instructions / operation on execution units. For example, a floating point instruction is scheduled at a port of an execution unit having an available floating point execution unit. Register files associated with the execution units are also included to store informational instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a memory execution unit, and other known execution units.

Lower Level Data Cache and Data Translation Buffer (D-TLB) 150 are with the execution unit (s) 140 coupled. The data cache is intended to store recently used elements, such as data operands potentially held in memory coherency states. The D-TLB is intended to store recent virtual / linear to physical address translations. As a specific example, a processor may include a page table structure to split physical memory into multiple virtual pages.

Here are the cores 101 and 102 access to a higher-level or further-out cache, such as a second-level cache, an on-chip interface 110 assigned. It should be noted that higher-level or further-out refers to cache levels that increase or decrease further from the execution unit (s). In one embodiment, the higher level cache is a last level data cache - last cache in the memory hierarchy on the processor 100 such as a second or third level data cache. However, the higher level cache is not limited to this because it may be associated with or include an instruction cache. A trace cache - a type of instruction cache - can be used instead after the decoder 125 coupled to store recently decoded tracks. Here, a command potentially refers to a macroinstruction (that is, a general command recognized by the decoders) that can decode into a number of microinstructions (micro-operations).

In the illustrated configuration, the processor closes 100 also the on-chip interface module 110 on. Historically, a memory controller, which is described in more detail below, has become a computing system external to the processor 100 locked in. In this scenario, the on-chip interface is supposed to be 11 with devices outside the processor 100 such as a system memory 175 a chipset (often including a memory controller hub for connecting to the memory 175 and an I / O controller hub for connecting peripherals), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, the bus can 105 include a known interconnect such as a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (eg, cache-coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

The memory 175 can for the processor 100 be provided or shared with other devices in a system. Conventional examples of these types of memory 175 include DRAM, SRAM, nonvolatile memory (NV), and other known memory devices. It should be noted that the device 180 a graphics accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I / O controller hub, a wireless transceiver, a flash device, an audio controller , a network controller or other known device.

However, as more logic and devices are integrated on a single die, such as an SOC, each of these devices may now be on the processor 100 to get integrated. For example, in one embodiment, a memory controller hub is on the same package and / or with the processor 100 , Here concludes a section of the core (an "on-core" section) 110 one or more controllers for interfacing with other devices, such as the memory 175 or a graphics device 180 , on. The configuration, which includes interconnection and controllers for interfacing with such devices, is often called an "on-core" (or an "un-core" configuration). As an example, an on-chip interface is included 110 a ring interconnect for on-chip communication and a high-speed serial point-to-point connection 105 for off-chip communication. In the SOC environment, however, even more devices, such as the network interface, co-processors, memory, can be used 175 , Graphics processor 180 and any other known computer devices / interfaces may be integrated on a single die or single integrated circuit to provide a small form factor with high functionality and low power consumption.

In one embodiment, the processor is 100 capable of a compiler, optimization and / or translator code 177 to execute application code 176 to compile, translate and / or optimize to support or interface with the device and methods described herein. A compiler often includes a program or set of programs for translating source code into target text / code. Typically, compilation of program / application code with a compiler is done in multiple phases and passes to convert Hi-Level programming language code to low-level machine or assembly language code. However, single-pass compilers can still be used for easy compilation. A compiler may employ any known compilation technique and perform any known compiler operations such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion, and code optimization.

Larger compilers often include multiple phases, but these phases are mostly contained within two major phases: (1) a frontend, that is, generally, where syntactic processing, semantic processing, and part of conversion / optimization can take place, and (2) a backend, that is generally where analysis, transformations, optimizations, and code generation take place. Some compilers refer to a "middle" that demonstrates the blurring of a clear separation between a frontend and a backend of a compiler. As a result, a reference to the insertion, association, creation, or other operation of a compiler may take place in any of the above-mentioned phases or passes, as well as in any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, fetches, functions, etc. into one or more compilation phases, such as inserting fetch / operations in a front-end phase of the compilation, and then converting the fetch / operations into lower-level code during a conversion phase. It should be noted that during a dynamic compilation, compiler code or dynamic optimization code may insert such operations / fetch as well as optimize the code for execution at runtime. As a specific illustrative example, binary code (already compiled code) may be optimized dynamically during runtime. Here, the program code may include the dynamic optimization code, the binary code or a combination thereof.

Similar to a compiler, a translator, like a binary translator, translates code either statically or dynamically to optimize and / or translate code. Reference to execution of code, application code, program code, or other software environment may therefore refer to: (1) execution of compiler program (s), optimizer code optimizer, or translator, dynamic or static, to compile program code, maintain software structures perform other operations, optimize code or translate code; (2) executing a main program code that includes operations / fetches, such as application code that has been optimized / compiled; (3) executing other program code, such as libraries associated with the main program code, to maintain software structures, perform other software-related operations, or optimize code, or (4) a combination thereof.

2 FIG. 10 is a schematic illustration of an exemplary Peripheral Component Interconnect Express (PCIe) interconnect architecture. FIG 200 according to embodiments of the present disclosure. The PCIe connection architecture 200 closes a first component 202 which may be an upstream component, a root complex, or a switch compliant with the PCIe protocol. The first component 202 can have a downstream port 210 Include communications with upstream components over a connection 222 , as a PCIe compliant connection. The first component 202 can be attached to a second component 208 be coupled, which is a downstream component, a Endpoint or a switch compliant with the PCIe protocol. In some embodiments, the first component may include one or more intermediate components, such as a first retimer 204 and a second retimer 206 be connected.

In embodiments, the first component 202 a downstream port 210 include downstream communications (eg, to the second component 208 ) with the second component 208 (if directly connected) or with the upstream (pseudo) port 212 the retimer 204 to support. The second component 208 can be an upstream port 220 to include upstream communications (e.g., to the first component 202 ) with the first component 202 (if directly connected) or with the downstream (pseudo) port 212 the retimer 204 to support.

In the in 2 example shown, the first component 202 through a first connection segment 224 with a first retimer 204 be connected. Similarly, the first retimer 204 through a second connecting segment 226 with a second retimer 206 be connected. The second retimer 206 can through a connection segment 228 with the second component 208 be connected. The connection segments 224 . 226 and 228 can be the entire or a section of the connection 222 form.

The connection 222 can upstream and downstream communications between the first component 202 and the second component 208 support. In embodiments, upstream communications refer to data and control information received from the second component 208 to the first component 202 be transmitted; and relate downstream communications to data and control information received from the first component 202 to the second component 208 be transmitted. As indicated above, one or more retimers (e.g., retimers 204 and 206 ) used to determine the range of the connection 222 between the first component 202 and the second component 208 to enlarge.

A connection 222 containing one or more retimers (eg the Retimer 204 and 206 ) can form two or more separate electrical sub-connections at data rates comparable to data rates realized by connections using similar protocols but without retimers. For example, if the connection 222 contains a single retimer, the compound can 222 form a compound with two separate subcompounds, each operating at 8.0 GT / s or higher. As in 2 shown, several retimers can 204 . 206 used to connect 222 to expand. Three connection segments 222 . 224 and 226 can through the two retimers 204 . 206 be defined, wherein a first sub-connection 222 the first component 202 with the first retimer 204 connects, a second sub connection 224 the first retimer 204 with the second retimer 206 connects and the third sub-connection 226 the second retimer 206 with the second component 208 combines.

As in the example of 2 In some implementations, a retimer may include two ports (or pseudo-ports) and the ports may dynamically determine their respective downstream / upstream alignment. In embodiments, the retimer 204 an upstream port 212 and a downstream port 214 lock in. Similarly, the retimer 206 an upstream port 216 and a downstream port 218 lock in. Every retimer 204 . 206 may have an upstream path and a downstream path. Furthermore, the retimer 204 . 206 Support operating modes that include a forwarding mode and an execution mode. A retimer 204 . 206 In some cases, it may decode data received on the sub-connection and re-encode the data it is to forward down on its other sub-connection. Therefore, retimers can capture the received bitstream prior to regenerating and retransmitting the bitstream to another device or even another retimer (or redriver or repeater). In some cases, the retimer may change some values in the data it receives, for example, when processing and passing ordered record data. In addition, a retimer may potentially support any width option as its maximum width, such as a set of width options defined by a specification such as PCIe.

As the data rates of serial interconnects (e.g., PCIe, UPI, USB, etc.) increase, retimers are increasingly being used to increase the channel reach. Several retimers can be cascaded for an even longer channel range. It is expected that the channel range will usually decrease generally with increasing signal speeds. Accordingly, the use of retimers with accelerated interconnect technologies can become more widespread. As an example, with the adoption of PCIe Gen-4 with its 16 GT / s for PCIe Gen-3 (8 GT / s), the use of retimers in PCIe interconnections may increase, as may occur in other interconnections Speeds increase.

The downstream port 210 (eg in the first component 202 , which may be an upstream component such as a root complex or switch), is accessible to system software before a connection is established or if the connection 222 is unable to function properly. In embodiments, registers, such as the connectivity register, may be set to a clock mode selection in the downstream port 210 perform. System firmware / software can use the downstream port 210 configure to the expected mode, and if a change is required, it will be done by system firmware / software, not hardware.

PCIe supports hot-plugging (also known as hot-swap) functionality, but it may lack a consistent way of reporting certain core bits of information to system software, making it difficult to optimally manage PCIe subsystems, and leads to system limitations and low usability. These same limitations also apply to Converged Input / Output (CIO) or "open" Thunderbolt because these I / O configurations use PCIe as a tunneled I / O architecture.

Hot-plug is a term that refers to the ability to add components to a host system that would expand the host system without significant system interruptions. Hot swap can be defined as replacing or adding components without stopping or shutting down the host system. In this disclosure, the terms are used interchangeably.

If the host system has the appropriate hot-plug functionality software, a user can plug and unplug hot-pluggable components into a hot-pluggable downstream port without rebooting the host system. Examples of this hot-plug functionality include the Universal Serial Bus (USB), PCIe, and CIO protocols, each of which may allow a user peripheral components such as a monitor, a storage device, a mouse, a keyboard to add or remove a printer, a portable hard drive or other peripheral device.

PCIe defines a "Designated Vendor Specific Extended Capability" (DVSEC), which is an advanced capability that can be used by a vendor to determine a configuration register structure that can be implemented by silicon vendors while maintaining consistent hardware / Software interface is provided. This disclosure may use DVSEC in embodiments to overcome the reporting deficiencies described above. The PCIe DVSEC is an advanced capability that can be implemented by any PCIe feature. This allows PCIe component vendors to use the enhanced capability mechanism to provide vendor-specific registers that may be present in components from a variety of vendors.

The DVSEC functions defined herein are applicable to any PCIe subsystem. Most of the examples and software implementation notes in this document are provided in the context of CIO, but are not limited to CIO. CIO is used herein as an example architecture.

CIO is a tunnel for PCIe and DisplayPort. A CIO connection can be a single track or two aggregate tracks operating at 10 Gbps to 40 Gbps or more. The CIO can be powered by a Type C USB plug (as an alternative mode) and allows PCIe devices outside the system box. Daisy chain topologies with up to 6 CIO devices are supported.

ClO peripherals are particularly problematic because CIO peripherals appear system software like a large set of PCIe bridges and endpoints. System software may not be able to distinguish between internal PCI devices (with non-changing resource requirements) and externally connected devices (with changing resource requirements), which prevents optimal resource allocation. In particular, system software is incapable of predicting bus numbers and resource levels to reserve a hot-pluggable downstream port within a CIO hierarchy. System software is also unable to determine other attributes of the hierarchy, such as D3Cold support, or the requirement for a managed device removal. The lack of this information can lead to inefficient device enumeration and management resulting in low user friendliness or loss of functionality.

Aspects of the present disclosure provide more accurate information regarding resources and / or bus numbers used by a hot-pluggable device, such as a device in the root complex or a downstream device (e.g., an externally connected device) connected to a downstream port of a host device) rather than the required resources and / or Estimate bus numbers. As a result, there may be exceptional cases where the reservation is either not large enough or too large, resulting in a waste. Aspects of the embodiments enable D3Cold support without using additional BIOS functionality that may not be available for hot-plug devices. Aspects of the embodiments also allow for display of common attributes, such as the port type, which may be vendor-specific functions.

This disclosure describes definitions and implementations of PCIe Designated Vendor Specific Extended Capabilities (DVSEC) functions that provide for host root ports and downstream ports of CIO / PCIe peripherals or other devices that provide resource requirements and attribute information for system software. can be displayed and processed by them.

System software, such as the one managing host root ports and / or downstream ports for connected devices, can parse the DVSEC to determine resource requirements, allowing a successful enumeration of hot-plugged device and a waste of resources to a minimum (including bus / device / function (BDF) and memory-mapped input / output (MMIO)). Other information within the DVSEC displays that meets the requirements for robust D3Cold support, a note about "safe ejection" and a device / host router distinction allow for efficient device management.

Aspects of the embodiments may allow system software to apply differential policies for security, resource allocation, power management, etc., by providing a downstream component or hierarchy of downstream components (eg, a daisy-chain hierarchy of downstream components). identified as a CIO or hot-plug device (s). In embodiments, a port-type field in the definition of DVSEC functions allows system software to identify CIO ports.

To support full daisy-chain functionality, system software would need to pre-allocate enough bus numbers and resources (such as MMIO). A pre-allocation would have to be accurate so that there is no waste (especially for BDFs) and just enough so that hot-plugged devices will be enumerated successfully without failures or resource balancing (both resulting in low usability or loss of functionality) ). DVSEC can provide hints in a definition of DVSEC functions to enable the system software to determine whether or not a hot-pluggable port is expandable, and to indicate the number of buses that need to be reserved.

Additional guidance in the definition of DVSEC functions may allow system software to enumerate and manage the hierarchy below the port in an efficient manner. Such additional hints may include an indication that allows system software to distinguish between host and device routers. This distinction allows system software to differentially apply policies (eg, security). Other hints may include an indication that allows the system software to determine a need for "managed" removal of a device, allowing for better user notification (eg, notifications about secure unplugging); and / or a hint that allows system software to cause a bridge to support D3Cold, which helps system software determine that if the particular power resource is off, the respective port is able to transition to D0 / to actively return (wake back).

3 is a schematic block diagram of a connected system 300 , which includes a hierarchy of a device connected to a host through a PCIe compliant connection, in accordance with embodiments of the present disclosure. The system 300 can be a host 350 encapsulated by a PCIe compliant connection (such as a CIO) with one or more connected downstream components, such as device 1 360 and device 3 390 , connected is. The system 300 may also include one or more daisy-chain connected downstream components, such as device 2 370 that communicate with the host via device 1 360 (eg, through a daisy-chain connection). Other daisy-chain connected downstream components may be included by the device (s) 380 are shown.

Every device of the system 300 may include a variety of ports, as discussed above 2 discussed. For example, the host may have a root port 302 which is part of a root complex including a plurality of switches and switch ports. The root port 302 can one Upstream port 304 include that with one or more downstream ports 306 - 312 connected to the transmission and reception of data and control signals with downstream components, such as devices 1-n to enable. For example, device may 1 360 through an upstream port 316 that with the downstream port 308 of the host 350 is connected to the root port 302 be connected. Similarly, device can 3 390 through a downstream port 312 that with an upstream port 336 connected to the host 350 be connected.

One or more downstream ports may be hot-pluggable to enable hot-plug detection of connected devices, and in some embodiments, to enable daisy-chain connection of downstream components. For example, the downstream port 308 a hot-pluggable downstream port that also allows daisy-chain connection of other downstream devices. For example, device may 2 370 through an upstream port 324 that comes with an expandable hot-pluggable downstream port 322 in conjunction with device 1 360 is connected to the root port 302 be connected. Another downstream port 318 can be a non-expandable downstream port that comes with a device 320 connected is. device 2 370 can be an upstream port 324 include that with the downstream port 322 connected is. device 2 can have a downstream port 326 Include that with a device 328 (for example, a non-extensible downstream port connected to an endpoint device). device 2 can also have a downstream port 330 include, which is hot-pluggable and with an upstream port 332 of device (s) 380 connected is. Device (s) 380 depicts other daisy-chained downstream components through an expandable, hot-pluggable downstream port 330 in conjunction with device 2 370 with the root port 302 are connected.

Similarly, the downstream port 312 be a hot-pluggable downstream port through an upstream port 336 with device 3 390 connected is. device 3 can have a downstream port 338 and a hot-pluggable downstream port 342 lock in.

Downstream devices, as in 3 may include any peripheral device or any other type of device that has a PCIe compliant connection with the host 350 like those using CIO or Thunderbolt connection protocols. One or more of the devices 1 . 2 . 3 or n ( 360 . 370 . 390 respectively. 380 ) can use the definition of the DVSEC function described herein to describe the host 350 to inform about certain advanced features to the host 350 to allow certain attributes to be configured for the particular device (s) upon detection of the hot-plug detection.

4 is a schematic representation of a definition of DVSEC functions 400 including one or more attribute hint bits, according to embodiments of the present disclosure. As described above, the definition of DVSEC functions 400 include one or more indicators or cues, represented as register bits, that can inform a host device of how to configure or apply certain attributes when the host device connects (eg, a hot-plug connection) to a host device Downstream device detects. The DVSEC definition 400 can be communicated to the host device that can use system software to configure the resources or other attributes indicated by the DVSEC definition.

In a first example, the DVSEC definition 400 a bus number reservation notice 402 lock in. The bus number hint reservation may indicate to the system software of the host device to determine a number of buses to reserve for the hierarchy under the root port or intermediate switch downstream ports (eg, in a daisy-chain hierarchy). The bus number reservation notice 402 can be defined as follows: Bus number reservation hint (offset = 0x0C, size = 1 byte) bit position Description and Software Implementation Notice attributes 7: 0 or 23:16 0x00: Not implemented RO 0x01-0xFE: Required number of buses 0xFF: unknown This field is applicable for root ports or switch downstream ports. This hint allows system software to determine the number of buses to reserve for the hierarchy below. A bus reservation allows system software to successfully support an enumeration of long daisy chains without bus numbers going out.

The system software of the host device may be based on the bus number reservation hint 402 in the DVSEC definition 400 set a number of buses for the connected device. Although the bit position 7: 0 or 23:16 is displayed, other bit positions in the DVSEC definition may be used depending on the implantation choice 400 be used.

In a second example, the DVSEC definition 400 a port-type indicator 404 lock in. The port type indicator 404 can be used to identify the port type of the connected system software device. System software can use this field to differentially apply software policies based on the port type displayed. The port type indicator 404 can be defined as follows: Port type (offset = 0 × 0C, size = 4 bits) bit position Description and Software Implementation Notice attributes 9: 6 or 15: 8 0x00: Unknown RO 0x01: CIO 0x02-0xFF: RESERVED for future use The port type indicator can be used to identify the port type of the connected system software device. System software can use this field to differentially apply software policies based on the port type displayed.

The system software of the host device may establish policies for the connected device based at least in part on the port type provided by the port-type indicator 404 in the DVSEC definition 400 is shown. Although the bit position 9 : 6 or 15: 8 is displayed, depending on the implant choice, other bit positions in the DVSEC definition 400 be used.

In another example, the DVSEC definition 400 a D3Cold support indicator 406 lock in. The D3Cold support indicator 406 is applicable to root ports or switch downstream ports. The D3Cold support indicator includes a bit that is set when it indicates that when the particular power resource (s) are turned off, the port and connected device (s) are able to do so is / are, without problems to the condition D0 (fully on) to go back / active (wake back), including in hot-plug cases. The D3Cold state is one of two D3 (low power) substates, the other being the D3Hot state.

The D3Cold support indicator 406 can be defined as follows: D3Cold support (offset = 0x0C, size = 1 bit) bit position Description and Software Implementation Notice attributes 4 or 5 0: Not implemented RO 1: D3Cold supported This field is applicable for root ports or switch downstream ports. This bit may only be set if it is guaranteed that, if the respective power resource (s) are turned off, the port and associated device (s) are capable of doing so, without problems to D0 to transition / actively wake (wake back), including in hot-plug cases. Downstream ports indicating support for D3cold are expected to implement mechanisms for controlling the power delivered to the connected devices, for example, through a wire or control bus (such as I2C / SMbus or I3C) to a power level. However, the details of how this mechanism operates are not covered by this document. System software can use this information to qualify the use of runtime performance management, such as: Where a hierarchy is placed under a specific port in D3cold. In some cases, system software may "roll up" the information provided here to enable / disable D3cold for a larger hierarchy, e.g. On an extensible port that includes multiple non-expandable ports among switches. In such uses, system software must ensure that D3Cold support is announced by * all * devices and bridges under the control point where it is considering switching to D3cold.

The host device system software uses the D3Cold support indicator 406 for implementing power management mechanisms for the connected device and in some cases for a hierarchy of connected devices. Although the bit position 4 or 5 is displayed, depending on the implant choice other bit positions in the DVSEC definition 400 be used.

In another example, the DVSEC definition 400 a host router ad 408 lock in. The host router ad 408 is applicable to root ports or switch downstream ports on a host platform. The host router ad 408 allows system software to determine if the port of the connected device is part of a host router. This distinction allows system software to differentially apply policies (eg, security). Although the use of bit positions 3 : 2 or 4 is displayed, depending on the implementation choice, other bit positions in the DVSEC definition 400 be used. The host router ad 408 can be defined as follows: Host display (offset = 0x0C, size = 2 bits) bit position Description and Software Implementation Notice attributes 3: 2 or 4 00: Not implemented (no host) RO 01: Host - indicates a port that is physically part of the host system 10: Reserved 11: Host Outbound - indicates a port that is an outbound user-accessible port of a host system This field is applicable to root ports or switch downstream ports on a host platform. This display allows system software to determine if this port is part of a host router. This distinction allows system software to differentially apply policies (eg, security). Outbound ports of a host represent the physical boundary of a host system. It should not be indicated that a port to a port that is displayed as "11" is "01" or "11" and system software should be any to quarantine such hardware that is detected ..

In another example, the DVSEC definition 400 a note "Safe ejection" 410 lock in. The note "Safe ejection" 410 Applies to switch downstream ports and provides guidance for system software to enable system software to determine whether the PCIe endpoint associated with this port requires managed removal (e.g., a user can use a soft eject, before physically removing the device from the port). The note "Safe ejection" 410 can be defined as follows: Note "Safe ejection" (offset = 0x0C, size = 1 bit) bit position Description and Software Implementation Notice attributes 2 or 5 0: Not implemented RO 1: Safe eject requested This field applies only to switch downstream ports and provides guidance for system software to determine if the PCIe endpoint attached to this port requires managed removal. System software can use this hint to notify users and populate the Safe Eject menu with device details. However, this does not preclude the system software from the need to handle staggering removal events in a robust manner.

System Software May Display "Safe Ejecting" 410 to notify a user that safe ejection is preferred prior to device removal, and to populate the Safe Eject menu with device details. Although the bit position 2 or 5 is displayed, other bit positions for the note "Safe Eject" 410 in the DVSEC definition 400 be used.

In another example, the DVSEC definition 400 a port extensibility indicator 412 lock in. The port extensibility indicator 412 is applicable to root ports or switch downstream ports. The port extensibility indicator 412 Provides system software displays when this port is expandable. An example of an expandable root port are CIO ports on the host or daisy-chain capable ports on ClO peripherals. An example of a non-extensible port is a PCIe port permanently attached to a specific PCIe device, or a port where it is possible to determine the full resource requirements at the time of the initial enumeration, including for scenarios where a fixed resource request is pre-assigned, e.g. B. for a memory card reader. This information enables the operating system to allocate resources, such as MMIO, in an appropriate manner based on the port type. For example, sufficient resources may be allocated to a non-expandable port only for the enumerated PCIe device, while an expandable port may be assigned a larger set of resources to accommodate future additional resource requirements.

The port extensibility indicator 412 can be defined as follows: Port expandability (offset = 0x0C, size = 2 bits) bit position Description and Software Implementation Notice attributes 1: 0 00: Not implemented RO 01: Non-extensible port with fixed resource requirements 10: Expandable (or daisy-chain capable) port with resource requirements that may change at runtime 11: Reserved This field is applicable for root ports or switch downstream ports. This field provides system software displays when this port is expandable. An example of an expandable root port are CIO ports on the host or daisy-chain capable ports on ClO peripherals. An example of a non-extensible port is a PCIe port permanently attached to a specific PCIe device, or a port where it is possible to determine the full resource requirements at the time of the initial enumeration, including for scenarios where a fixed resource request is pre-assigned, e.g. B. for a memory card reader. This information enables the operating system to allocate resources, such as MMIO, in an appropriate manner based on the port type. For example, sufficient resources may be allocated to a non-expandable port only for the enumerated PCIe device, while an expandable port may be assigned a larger set of resources to accommodate future additional resource requirements.

The port extensibility indicator 412 allows the operating system (or more generally system software) to allocate resources, such as MMIO, appropriately based on the port type. For example, sufficient resources may be allocated to a non-extensible port for the enumerated PCIe device, while an expandable port may be assigned a larger set of resources to accommodate future additional resource requirements. Although the bit position 1 : 0 is displayed, depending on the implementation choice, other bit positions in the DVSEC definition 400 be used.

5 is a process flow diagram 500 for a host device to implement one or more attributes of a downstream component based on a definition of DVSEC functions in accordance with embodiments of the present disclosure. Initially, system software (on a host device or a switch downstream port) may connect a downstream component, such as a peripheral device or other type of downstream device (FIG. 502 ), recognize. Discovery of the connection may include hot-plug detection of a device connected to a hot-pluggable downstream port. Upon detection of the device, the system software may provide information about a definition of DVSEC functions from the connected device ( 504 ) received. The system software may read one or more indicators of the DVSEC function from the function definition information that the system software provides about one or more configuration parameters or attributes for the connected downstream device (FIG. 506 ) inform. The system software may use the DVSEC feature indicator (s) to provide one or more downstream component operating parameters, such as the number of buses, port type, extensibility, D3Cold support status, host Router indicator and / or the requirements for safely ejecting the downstream component. The system software may then provide data and control signal communications between the host device and the connected downstream device based on the applied configuration parameters and attributes ( 508 ) coordinate.

A circuit tree architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A key objective of PCIe is to allow components and devices from different manufacturers to interact in an open architecture spanning multiple market segments; Clients (desktops and mobile), servers (standard and enterprise) as well as embedded and communication devices. PCI Express is a universal, high-performance I / O interconnect designed for a wide variety of applications future computing and communication platforms. Some PCI attributes, such as the usage model, load memory architecture and software interfaces, have been retained through their revisions, while previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The newer versions of PCI Express take advantage of advances in point-to-point interconnects, the switch-based technology, and the packetized protocol to deliver new levels of performance and feature. Performance management, quality of service (QoS), hot-plug / hot-swap support, data integrity, and error handling are among the advanced features supported by PCI Express.

With reference to 6 FIG. 12 illustrates one embodiment of a structure consisting of point-to-point links interconnecting a set of components. A system 600 closes a processor 605 and a system memory 610 one, connected to a controller hub 615 are coupled. The processor 605 includes any processing element such as a microprocessor, a host processor, an embedded processor, a co-processor, or another processor. The processor 605 is through a front-side bus (FSB) 606 to the controller hub 615 coupled. In one embodiment, the FSB 606 a serial point-to-point interconnection as described below. In another embodiment, the compound closes 606 a serial, differential interconnect architecture that matches different interconnect standards.

The system memory 610 includes any storage device, such as random access memory (RAM), nonvolatile memory (NV), or other memory, on the devices in the system 600 can access. The system memory 610 is through a memory interface 616 to the controller hub 615 coupled. Examples of a memory interface include a Double Data Rate (DDR) memory interface, a dual channel DDR memory interface, and a Dynamic RAM (DRAM) memory interface.

In one embodiment, the controller hub is 615 a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of the controller hub 615 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH), a southbridge, and a root port controller / hub. Often, the term chipset refers to two physically separate controller hubs, that is, a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). It should be noted that current systems are often those in the processor 605 include integrated MCH while the controller 615 in a similar manner to I / O devices as described below. In some embodiments, peer-to-peer routing becomes optional through the root complex 615 supported.

Here is the controller hub 615 through a serial connection 619 with a switch / bridge 620 coupled. Input / Output modules 617 and 621 that also interfaces / ports 617 and 621 can be called, include or implement a layered protocol stack for communication between the controller hub 615 and the switch 620 provide. In one embodiment, multiple devices may be connected to the switch 620 be coupled.

The switch / bridge 620 conducts packets / messages from device 625 up, that is, a hierarchy up towards a root complex to the controller hub 615 , and down, that is, down a hierarchy from a root port controller of the processor 605 or system memory 610 to the device 625 , The switch 620 In one embodiment, it is called a logical arrangement of several PCI-to-PCI virtual bridge devices. The device 625 includes any internal or external device or component associated with an electronic system, such as an I / O device, a Network Interface Controller (NIC), an expansion card, an audio processor, a network processor, a hard disk, a hard disk Storage device, a CD / DVD-ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner and other input - / output devices to be coupled. Often, an endpoint is called PCIe colloquial, such as device. Although not specifically shown, the device may 625 include a PCIe to PCI / PCI-X bridge to support legacy PCI or PCI devices of other versions. Endpoint devices in PCIe are often classified as older, PCIe or Root Complex integrated endpoints.

A graphics accelerator 630 is via a serial connection 632 also with the controller hub 615 coupled. In one embodiment, the graphics accelerator is 630 coupled with an MCH, who with a I am coupled. The switch 620 and the I / O device accordingly 625 is then coupled to the ICH. I / O modules 631 and 618 should also implement a layered protocol stack to switch between the graphics accelerator 630 and the controller hub 615 to communicate. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 630 even in the processor 605 be integrated.

With reference to 7 An embodiment of a layered protocol stack is illustrated. A layered protocol stack 700 includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance compute interconnect stack, or another layered stack. Although the discussion is immediately below with reference to 6-9 in relation to a PCIe stack, the same concepts can be applied to other interconnect stacks. In one embodiment, the protocol stack is 700 a PCIe protocol stack that is a transaction layer 705 , a tie layer 710 and a physical layer 720 includes. An interface, like interfaces 617 . 618 . 621 . 622 . 626 and 631 in 1 , as a communication protocol stack 700 be shown. The representation as a communication protocol stack may also be referred to as a module or interface that implements / includes a protocol stack.

PCI Express uses packets to communicate information between components. Packages are in the transaction layer 705 and the data link layer 710 formed to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are augmented with additional information necessary to handle packets in those layers. On the receiving side, the reverse process occurs and packets are taken from their physical layer representation 720 in the representation of the data link layer 710 and finally (for transaction layer packets) in the form that the transaction layer 705 the receiving device can be processed.

transaction layer

In one embodiment, the transaction layer 705 an interface between a processing core of a device and the interconnect architecture, such as the data link layer 710 and the physical layer 720 , provide. In this context, a primary responsibility of the transaction layer 705 assembling and disassociating packages (that is, transaction layer packages or TLPs). The translation layer 705 typically manages credit-based flow control for TLPs. A PCIe translates shared transactions, that is, transactions with request and response separated by time, which allows one connection to carry other traffic while the destination device collects data for the response.

In addition, PCIe uses credit-based flow control. In this scheme, a device quits an initial credit amount for each of the receive buffers in the transaction layer 705 on. An external device at the opposite end of the connection, such as the controller hub 115 in 1 , counts the number of credits consumed by each TLP. A transaction can be transferred if the transaction does not exceed a credit limit. Upon receiving a response, a credit amount is restored. An advantage of a credit system is that the latency of the credit return does not affect the performance, provided that the credit limit is not reached.

In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more read requests and write requests to transfer data to / from a memory mapping location. In one embodiment, memory space transactions are capable of using two different address formats, for example a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access the configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Newsroom transactions (or simply messages) are defined to support in-band communication between PCIe agents.

Therefore, the transaction layer assembles 705 in one embodiment, a packet header / payload 706 , The format for current packet headers / payloads can be found in the PCIe specification on the PCIe specification web site.

With brief reference to 8th An embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, the transaction descriptor is 800 a mechanism for transferring transaction information. In this regard, the transaction descriptor supports 800 the identification of transactions in a system. Other potential uses include tracking changes to the standard transaction sequence and mapping transactions to channels.

The transaction descriptor 800 closes a global identifier field 802 , an attribute field 804 and a channel identifier field 806 on. In the illustrated example, the global identifier field is 802 representing a local transaction identifier field 808 and a source identifier field 810 includes. In one embodiment, the global transaction identifier is 802 unique for all pending requests.

According to one implementation, the local transaction identifier field is 808 a field generated by a requesting agent and it is unique to any pending requests that require completion for that requesting agent. Further, in this example, the source identifier identifies 810 the requesting agent within a PCIe hierarchy. Together with the source ID 810 Represents the local transaction identifier field 808 accordingly, a global identification of a transaction within a hierarchy domain ready.

The attribute field 804 specifies properties and relationships of the transaction. In this context, the attribute field 804 potentially used to provide additional information that allows modification of the standard processing of transactions. In one embodiment, the attribute field closes 804 a priority field 812 , a reserved field 814 , a regulatory field 816 and a no-snoop field 818 on. Here can the priority subfield 812 be changed by an initiator to prioritize the transaction. A reserved attribute field 814 remains reserved for future or provider-defined usage. Possible usage models that use priority or security attributes can be implemented using the reserved attribute field.

In this example, the order attribute field becomes 816 used to provide optional information that conveys the order type that can modify default rules. According to an example implementation, an ordering attribute "0" means that standard ordering rules are to be applied, where an ordering attribute "1" designates relaxed ordering, and writes can propagate in the same direction and read completions can pass writes in the same direction. The snoop attribute field 818 is used to determine if transactions are being snooped. As shown, the channel ID field identifies 806 a channel to which a transaction is assigned.

link layer

A connection layer 710 , also data link layer 710 called, acts as an intermediate between the transaction layer 705 and the physical layer 720 , In one embodiment, there is a responsibility of the data link layer 710 providing a reliable mechanism for exchanging transaction layer packets (TLPs) between two components of a connection. One side of the data link layer 710 accepts TLPs from the transaction layer 705 be assembled uses a packet sequence identifier 711 that is, an identification number or packet number, calculates an error detection code and applies it, that is, CRC 712 , and sends the modified TLPs to the physical layer 720 for transmission via a physical to an external device.

Physical layer

In one embodiment, the physical layer closes 720 a logical subblock 721 and an electrical sub-block 722 to physically transmit a packet to an external device. Here is the logical subblock 721 for the "digital" functions of the physical layer 721 responsible. In this connection, the logical sub-block includes a transmission section for outgoing information for transmission by the physical sub-block 722 and a receiver section to identify and prepare received information before going to the link layer 710 be passed on.

The physical block 722 includes a transmitter and a receiver. The sender is from the logical sub-block 721 supplied with symbols that the transmitter serializes and transmits to an external device. The receiver is supplied with serialized symbols from an external device and converts the received signals into a bitstream. The bit stream is de-serialized and becomes logical sub-block 721 delivered. In one embodiment, an 8b / 10b transmission code is employed in which ten-bit symbols are transmitted / received. Here are special icons for framing a packet with frames 723 used. In addition, in one example, the receiver also provides a symbol clock that is recovered from the incoming serial stream.

As stated above, although the transaction layer is 705 , the connecting layer 710 and the physical layer 720 with respect to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not limited thereto. In fact, any layered protocol can be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer to assemble packets, that is, a transaction layer; a second layer to sequence packets, that is, a link layer; and a third layer to transmit packets, that is, a physical layer. As a specific example, a Common Standard Interface (CSI) layer protocol is used.

Referring next to 9 Illustrated is an embodiment of a serial PCIe point-to-point structure. Although one embodiment of a PCIe serial point-to-point connection is illustrated, a point-to-point serial connection is not limited to this, as it includes any transmission path for transmitting serial data. In the illustrated embodiment, a base PCIe connection includes two differentially powered low voltage signal pairs: a transmission pair 906 / 911 and a reception couple 912 / 907 , Accordingly, a device closes 905 a transmission logic 906 to get data to a device 910 and a receive logic 907 to get data from the device 910 to receive one. In other words, there are two transmission paths, that is, paths 916 and 917 , and two reception paths, that is paths 918 and 919 , contained in a PCIe connection.

A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or another communication path. A connection between two devices, such as the device 905 and the device 910 , is referred to as a connection, such as connection 415 , A link may support a track - each track representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale the bandwidth, a link may aggregate multiple lanes named xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

A differential pair refers to two transmission paths, such as lines 416 and 417 to transmit differential signals. As an example, if the line 416 from a low voltage level to a high voltage level, that is, a rising edge, controls the line 417 from a high logic level to a low logic level, that is a falling edge. Differential signals potentially demonstrate better electrical properties, such as better signal integrity, that is, crosstalk, voltage overshoot / undershoot, noise, etc. This allows for a better time window, allowing for faster transmission frequencies.

It should be noted that the above-described devices, methods and systems can be implemented in any electronic device or system as mentioned above. As specific illustrations, the following figures provide exemplary systems for use with the invention as described herein. As the following systems are described in more detail, a number of different interconnections are disclosed, described, and reiterated from the foregoing discussion. And, as can be readily appreciated, the advances described above can be applied to any of those interconnections, structures, or architectures.

With reference to 10 FIG. 12 is a block diagram of an exemplary computer system configured with a processor including execution units for executing an instruction, wherein one or more of the interconnections implement one or more features in accordance with an embodiment of the present invention. system 1000 includes a component, such as a processor 1002 to employ execution units that include logic to execute process data algorithms according to the present invention, such as in the embodiment described herein. The system 1000 is representative of processing systems available on the PENTIUM III ™, PENTIUM 4 ^™ , Xeon ™, Itanium, XScale ™, and / or StrongARM ™ microprocessors available from Intel Corporation of Santa Clara, California. Although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may also be used. In an embodiment, the exemplary system performs 1000 a version of the WINDOWS ™ operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (UNIX and Linux, for example), embedded software and / or graphical user interfaces may also be used. Thus, embodiments of the present invention are not limited to any specific combination of hardware circuits and software.

Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices, such as hand-held devices and embedded applications. Some examples of handheld devices include cell phones, internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include a microcontroller, digital signal processor (DSP), system-on-a-chip, network computer (NetPC), set-top boxes, network hubs, Wide Area Network (WAN) switches, or any other system execute one or more instructions according to at least one embodiment.

In this illustrated embodiment, the processor completes 1002 one or more execution units 1008 to implement an algorithm that should execute at least one command. An embodiment may be described in the context of a single processor desktop or server system, but alternative embodiments may be included in a multiprocessor system. The system 1000 is an example of a "hub" system architecture. The computer system 1000 closes a processor 1002 to process data signals. The processor 1002 as an illustrative example, includes a Complex Instruction Set Computer (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any of them another processor device, such as a digital signal processor. The processor 1002 is with a processor bus 1010 coupled, the data signals between the processor 1002 and other components in the system 1000 transfers. The elements of the system 1000 (for example, graphics accelerator 1012 , Memory controller hub 1016 , Storage 1020 , I / O controller hub 1024 , wireless transceiver 1026 , Flash BIOS 1028 , Network controller 1034 , Audio controller 1036 , serial expansion port 1038 , I / O controllers 1040, etc.) perform their conventional functions well known to those skilled in the art.

In one embodiment, the processor completes 1002 an internal cache memory 1004 the level 1 ( L1 ) on. Depending on the architecture, the processor may 1002 have a single internal cache or multiple levels of internal caches. Other embodiments include a combination of both internal and external caches, depending on the particular implementation and requirements. A register file 1006 is intended to store different types of data in different registers, including integer registers, floating point registers, vector registers, stored registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

The execution unit 1008 which includes logic for performing integer and floating point operations is also in the processor 1002 , The processor 1002 In one embodiment, it includes a microcode (ucode) ROM for storing microcode that, when executed, should execute algorithms for particular macro instructions or handle complex scenarios. Here, microcode is potentially updatable to logical bugs / fixes for the processor 1002 handle. For one embodiment, the execution unit includes 1008 Logic to a packed instruction set 1009 handle. By including the packed instruction set 1009 in the instruction set of a general-purpose processor 1002 Along with associated circuits for executing the instructions, the operations used by many multimedia applications can be accomplished by using packed data in a general purpose processor 1002 be performed. Thus, many multimedia applications are sped up and executed more efficiently by using the full width of the data bus of a processor to perform packed data operations. This potentially eliminates the need to transmit smaller data units over the processor's data bus to perform one or more operations, one item at a time.

Alternative embodiments of an execution unit 1008 can also be used in microcontrollers, embedded processors, graphics devices, DSPs and other types of logic circuits. The system 1000 closes a store 1020 on. The memory 1020 includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device or other memory device. The memory 1020 stores instructions and / or data represented by data signals received from the processor 1002 to be executed.

It is to be understood that any or all of the above features or aspects of the invention are based on one or more of the 10 illustrated interconnections can be used. For example, an on-die interconnect (ODI), not shown, implements for coupling internal units of the processor 1002 one or more aspects of the invention described above. Or the invention is a processor bus 1010 (For example, Intel Quick Path Interconnect (QPI) or any other known high performance computing interconnect), a high-bandwidth storage path 1018 to the store 1020 , a point-to-point connection with the graphics accelerator 1012 (For example, a Peripheral Component Interconnect Express (PCIe) -compatible structure), a controller hub interconnect 1022 , an I / O or other interconnect (for example, USB, PCI, PCIe) for coupling the other illustrated components. Some examples of such components include the audio controller 1036 , the firmware hub (flash BIOS) 1028 , the wireless transceiver 1026 , the data store 1024 , the 1010 Legacy I / O Controller with User Input and Keyboard Interfaces 1042 , a serial expansion port 1038 , such as Universal Serial Bus (USB), and a network controller 1034 on. The data storage device 1024 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

Now referring to 11 is a block diagram of a second system 1100 according to an embodiment of the present invention. As in 11 shown is the multiprocessor system 1100 a point-to-point interconnect system and includes a first processor 1170 and a second processor 1180 a via a point-to-point interconnection 1150 are coupled. Each of the processors 1170 and 1180 can be a version of a processor. In one embodiment 1152 and 1154 Part of a coherent serial point-to-point interconnect structure, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the invention can be implemented within the QPI architecture.

Although only with two processors 1170 . 1180 It should be understood that the scope of the present invention is not limited thereto. In other embodiments, one or more additional processors may be present in a given processor.

The processors 1170 and 1180 are each integrated memory controller units 1172 and 1182 having shown. The processor 1170 closes the point-to-point (PP) interfaces as part of its bus controller units 1176 and 1178 on; the second processor 1180 similarly closes the PP interfaces 1186 and 1188 on. The processors 1170 and 1180 can provide information via a point-to-point (PP) interface 1150 using the PP interface circuits 1178 . 1188 change. As in 11 shown, pair the IMCs 1172 and 1182 the processors to respective memory, namely a memory 1132 and a memory 1134 , which may be portions of a main memory that is bound locally to the respective processors.

The processors 1170 . 1180 exchange information about individual PP interfaces 1152 . 1154 with a chipset 1190 using the point-to-point interface circuits 1176 . 1194 . 1186 . 1198 out. The chipset 1190 Also exchanges information with a high performance graphics circuit 1138 via an interface circuit 1192 along a high performance graphics interconnect 1139 out.

A shared cache (not shown) may be included in either or both of the processors, but may be connected to the processors via a PP interconnect such that the local cache information may be stored by one or both processors in the shared cache when a processor is placed in a low power mode.

The chipset 1190 can via an interface 1196 with a first bus 1116 be coupled. In an embodiment, the first bus 1116 a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or other third generation I / O interconnect bus, although the scope of the present invention is not limited thereto.

As in 11 shown are different I / O devices 1114 together with a bus bridge 1118 that the first bus 1116 to a second bus 1120 connects to the first bus 1116 coupled. In one embodiment, the second bus closes 1120 a low pin count (LPC) bus. Various devices are in one embodiment with a second bus 1120 coupled, for example, a keyboard and / or mouse 1122 , Communication devices 1127 and a storage unit 1128 Like a disk drive or other mass storage device, often commands / code and data 1130 includes, coupled. There is also an audio I / O 1124 to the second bus 1120 shown coupled. It should be noted that other architectures are possible, with the included components and interconnect architectures varying. For example, a system instead of the point-to-point architecture of 11 implementing a multi-drop bus or other such architecture.

Using the various inertial and environmental sensors present in a platform, many different applications can be realized. These applications allow for advanced computational operations, including perceptual computing, and also allow for performance management / battery life, security, and system responsiveness improvements.

For example, in terms of power management / battery life issues, ambient light conditions, at least in part based on information from an ambient light sensor, are determined at a location of the platform and the intensity of the display is controlled accordingly. Thus, the power consumption during operation of the display is reduced under certain lighting conditions.

Regarding security operations, based on context information obtained from the sensors, such as location information, it may be determined whether a user is allowed to access certain secure documents. For example, a user may be allowed to access such documents at a workstation or at home. However, the user is prevented from accessing such documents when the platform is in a public place. This determination is based in one embodiment on location information, e.g. B. determined by a GPS sensor or camera recognition of landmarks. Other security operations may include providing for pairing devices within short distances of each other, e.g. A portable platform as described herein, and a desktop computer, a cell phone, etc. of a user. Some sharing is realized in some implementations via near field communication when these devices are so paired. However, if the devices exceed a certain distance, such sharing may be disabled. Further, when a platform and a smartphone described herein are paired, a warning may be configured to be triggered when the devices move farther apart than a predetermined distance when in a public location. In contrast, if these paired devices are in a secure location, e.g. As a workplace or at home, exceed this predetermined limit, without triggering such a warning.

The responsiveness can also be improved using the sensor information. For example, even when a platform is in a low power state, the sensors may be capable of being operated at a relatively low frequency. Accordingly, any changes in a location of the platform are determined, e.g. As determined by inertial sensors, a GPS sensor or the like. If no such changes have been registered, a faster connection to a previous wireless hub, such as a Wi-Fi ™ access point or similar wireless enabler, occurs because in this case it is not necessary to scan for available wireless network resources. Thus, a higher level of responsiveness is achieved when switching from a low power state to a standby state.

It is understood that many other applications may be enabled using sensor information obtained via the integrated sensors within a platform described herein, and the above examples are for illustrative purposes only. Using a system as described herein, a perceptual computing system may allow addition of alternative input modalities, including gesture recognition, and allow the system to capture user operations and intentions.

In some embodiments, one or more infrared or other thermal sensing elements or any other elements for detecting the presence or movement of a user may be present. Such sensing elements may include several different elements that work together, operate sequentially, or both. For example, sensing elements include elements that provide initial detection, such as light or sound projection, followed by gesture recognition detection by, for example, an ultrasonic transit time camera or a textured light camera.

Also, in some embodiments, the system includes a light generator to create a line of illumination. In some embodiments, this line provides a visual indication of a virtual boundary, namely an imaginary or virtual location in space, as an action of the user to traverse or break through the virtual boundary or plane as an intent to interact is interpreted with the computing system. In some embodiments, the illumination line may change colors as the computing system transitions to different states with respect to the user. The lighting line may be used to provide a visual indication to the user about a virtual boundary in space and may be used by the system to determine state transitions of the computer to the user, including determining when the user wishes to interact with the computer.

In some embodiments, the computer captures the user position and operates to interpret the movement of a user's hand through the virtual border as a gesture indicating an intention of the user to interact with the computer. In some embodiments, when traversing through the virtual line or plane, the light generated by the light generator may change, giving visual feedback to the user that the user has entered a gestural providing area for input to provide for the computer.

Display screens may display visual indications of state transitions of the computing system to a user. In some embodiments, a first screen is provided in a first state in which the presence of a user is detected by the system, such as by using one or more of the sensing elements.

In some implementations, the system acts to capture a user identity, such as by face recognition. Here, a transition to a second screen may be provided in a second state in which the computing system has recognized the user identity, which second screen provides visual feedback to the user that the user has transitioned to a new state. A transition to a third screen may take place in a third state in which the user has acknowledged the recognition of the user.

In some embodiments, the computing system may use a transition mechanism to determine a location of a virtual boundary for a user, where the location of the virtual boundary may change with user and context. The computing system may generate a light, such as a lighting line, to indicate the virtual boundary for interacting with the system. In some embodiments, the computing system may be in a wait state and the light may be generated in a first color. The computing system may recognize whether the user has crossed the virtual boundary, such as by detecting the presence and movement of the user using sensing elements.

In some embodiments, if it is detected that the user has exceeded the virtual boundary (such as having the user's hands closer to the computing system than to the virtual boundary), the computing system may transition to a state for receiving gesture input from the user, wherein a mechanism for indicating the transition may include the virtual boundary indicating light changing to a second color.

In some embodiments, the computing system may then determine if gesture movement has been detected. If gesture movement is detected, the computing system may proceed with a gesture recognition process that may include using data from a gesture data library that may reside in memory in the computing device or that may otherwise be accessed by the computing device.

If a user's gesture is detected, the computing system may perform a function in response to the input and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not detected, the computing system may transition to an error condition where a fault state indicating mechanism may include the virtual boundary indicating light changing to a third color, the system receiving additional gestures returns when the user is within the virtual boundary to interact with the computing system.

As mentioned above, in other embodiments, the system may be configured as a convertible tablet system that may be used in at least two modes, a tablet mode and a notebook mode. The convertible system can have two fields, a display field and a base field, so that the two fields are stacked in tablet mode in a stack. In Tablet mode, the display panel faces outward and can provide touchscreen functionality, such as it can be found in conventional tablets. In notebook mode, the two fields can be arranged in an open shell configuration.

In various embodiments, the accelerometer may be a 3-axis accelerometer having data rates of at least 50 Hz. A gyroscope may also be included, which may be a 3-axis gyroscope. In addition, an e-compass / magnetometer may be present. Also, one or more proximity sensors may be provided (eg, for "lid open" for sensing when a person is near the system (or not) and adjusting performance to extend battery life). For the sensor fusion capability of some OS, picking up the accelerometer, gyroscope and compass can provide improved features. In addition, wake-up of sensor mechanisms may be implemented via a real-time clock (RTC) sensor hub to receive sensor inputs when a remainder of the system is in a low power state.

In some embodiments, an internal lid / indicator open switch or sensor may be present to indicate when the lid is closed / open and may be used to place the system in a connected standby state or to automatically wake from the connected standby state. Other system sensors may include ACPI sensors for internal processor, memory, and skin temperature monitoring to allow for changes in processor and system operating states based on sensed parameters.

In one embodiment, the OS may be a Microsoft® Windows® 8 OS implementing Connected Standby (also referred to herein as Win8 CS). Windows 8 Connected Standby, or another OS having a similar state, can provide very low ultra-up-time performance through a platform as described herein to allow applications to stay connected at very low power consumption, e.g. With a cloud-based location. The platform can support 3 performance states, namely screen on (normal); Connected Standby (as a default "off" state) and shutdown (zero watts power consumption). Thus, the platform is logically on in the Connected Standby state (at minimum power levels), even when the screen is off. In such a platform, application power management can be made transparent and maintain a constant connection, in part because of offload technology to allow the lowest power component to perform an operation.

Now referring to 12 FIG. 4 illustrates a block diagram of components present in a computer system according to an embodiment of the present invention. FIG. As in 12 shown, the system closes 1200 any combination of components. These components may be implemented as ICs, sections thereof, discrete electronic devices or other modules, logic, hardware, software, firmware, or a combination of computerized systems thereof or as components otherwise integrated within a chassis of the computer system. It should also be noted that the block diagram of 12 it is intended to provide an overview of many components of the computer system. It is understood, however, that some of the components shown may be omitted, additional components may be present, and different arrangements of the components shown may occur in other implementations. As a result, the invention described above may be implemented in any portion of one or more of the interconnections illustrated or described below.

As in 12 Shut down, a processor closes 1210 in one embodiment, a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, the processor acts 1210 as a main processing unit and as a central hub for communication with many of the various components of the system 1200 , As an example, the processor 1200 implemented as a system-on-a-chip (SOC). As a specific illustrative example, the processor concludes 1210 an Intel® Architecture Core ™ based processor, such as an i3, i5, i7 or other such processor available from Intel Corporation, Santa Clara, CA. It is understood, however, that in other embodiments, other low power processors, such as those available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, CA, include a MIPS-based design by MIPS Technologies, Inc. of Sunnyvale. CA, an ARM-based design developed by ARM Holdings, Ltd. or their customers or their licensees or users, such as an Apple A5 / A6 processor, Qualcomm Snapdragon processor or TI OMAP processor. It should be noted that many customer versions of such processors are modified and varied; but they do have one can support or recognize a specific instruction set that executes defined algorithms, as set forth by the processor licensor. Here, the microarchitectural implementation may vary, but the architectural function of the processor is usually consistent. Certain details regarding the architecture and operation of the processor 1210 in one implementation are discussed below to provide an illustrative example.

The processor 1210 communicates with system memory in one embodiment 1215 , An illustrative example that may be implemented across multiple memory devices in one embodiment to provide a predetermined amount of system memory. For example, the memory may be in accordance with a JEDEC low power double data rate (LPDDR) based design, such as the current LPDDR2 standard according to JEDEC JESD 209-2E (published in April 2009), or an LPDDR Next-generation standard called LPDDR3 or LPDDR4, which will provide enhancements to LPDDR2 to increase bandwidth. In various implementations, the individual storage devices may be of different types of packages, such as a single die package (SDP), a dual die package (DDP), or a quad die package (FIG. 67P) , These devices, in some embodiments, are soldered directly to a motherboard to provide a solution with a flatter profile, whereas in other embodiments, the devices are configured as one or more memory modules, which in turn couple to the motherboard through a predetermined connector. And of course, other memory implementations are possible, such as other types of memory modules, e.g. Dual Inline Memory Modules (DIMMs) of various varieties, including but not limited to microDIMMs, MiniDIMMs. In a particular illustrative embodiment, the memory is sized between 2 GB and 16 GB and may be designed as a DDR3LM package or as an LPDDR2 or LPDDR3 memory soldered to a motherboard via a Ball Grid Array (BGA).

To support persistent storage of information such as data, applications, one or more operating systems, and so forth, mass storage may also be used 1220 with the processor 1210 couple. In various embodiments, this mass storage may be implemented by means of an SSD to enable a thinner and lighter system design as well as to improve system responsiveness. However, in other embodiments, the mass storage may be implemented primarily using a hard disk drive (HDD) with a smaller amount of SSD storage to act as an SSD cache to allow non-volatile storage of contextual and other such information during shutdown enable a faster boot on a re-initiation of system activity. Also in 12 shown is a flash device 1222 that with the processor 1210 coupled, for. B. via a serial peripheral interface (Serial Peripheral Interface, SPI). This flash device can support nonvolatile storage of system software, including basic input / output software (BIOS) as well as other firmware of the system.

In various embodiments, the mass storage of the system is implemented by an SSD alone or as a disk, optical or other drive with an SSD cache. In some embodiments, the mass storage is implemented as an SSD or as an HDD along with a Restore (RST) cache module. In various implementations, the HDD supports storage between 320 GB and 4 terabytes (TB) and higher, whereas the RST cache with a SSD capacity of 24 GB 256 GB is implemented. It should be noted that such SSD cache may be designed as a single level cache (SLC) or a multi level cache (MLC) option to provide a suitable level of responsiveness. In a SSD-only option, the module may be located in different locations, such as an mSATA or NGFF slot. For example, an SSD has a capacity of 120 GB up to 1 TB is enough.

Various input / output (I / O) devices may be within the system 1200 to be available. In particular, in the embodiment of 12 an ad 1224 which may be a high definition LCD or LED panel configured within a lid portion of the housing. This display panel can also be a touch screen 1225 provide, for. Externally set up over the display panel so that user input can be supplied to the system through user interaction with this touchscreen to facilitate desired operations, e.g. As regards the display of information, access to information and the like. In one embodiment, the display 1224 with a processor 1210 be coupled via a display circuitry that may be implemented as a high performance graphics interconnect. The touch screen 1225 can have another interconnection with the processor 1210 coupled, which may be an I2C interconnection in one embodiment. As in further 12 in addition to the touch screen 1225 User input can also be shown by touch through a touchpad 1230 which can be configured within the housing and also with the same I2C interconnection as the touch screen 1225 can be coupled.

The display panel can work in several modes. In a first mode, the display panel may be arranged in a transparent state in which the visible light display panel is transparent. In various embodiments, the majority of the display panel may be a display, except for a perimeter around the perimeter. When the system is operating in a notebook mode and the display panel is operating in a transparent state, a user may display information presented on the display panel while also being able to display objects behind the display. In addition, information displayed on the display panel may be displayed by a user located behind the display. Or, the operating state of the display panel may be an opaque condition in which visible light does not pass through the display panel.

In a tablet mode, the system is collapsed so that the display rear surface of the display panel remains in a position that faces outward to a user when the bottom of the base panel rests on a surface or is held by the user. In the tablet mode of operation, the display back surface assumes the role of a display and a user interface, as this surface may have touch screen functionality and perform other known functions of a conventional touch screen device, such as a tablet device. To accomplish this, the display panel may include a transparency matching layer disposed between a touchscreen layer and a display front surface. In some embodiments, the transparency matching layer may be an electrochromic (EC) layer, an LCD layer, or a combination of EC and LCD layers.

In various embodiments, the display may be of different sizes, e.g. A 11.6 "or a 13.3" screen, and may have an aspect ratio of 16: 9 and at least a brightness of 300 nits. Also, the display may be full high definition resolution (HD) (at least 1920 × 1080p), compatible with an embedded display port (eDP), and a low power box with field refresh.

With regard to touchscreen capabilities, the system may provide a display multi-touch panel that is multi-touch capacitive and at least 5-finger capable. And in some embodiments, the display may be 10-finger capable. In one embodiment, the touch screen is housed within a damage and scratch resistant lens and coating (eg, Gorilla Glass ™ or Gorilla Glass 2 ™) for low friction to reduce "finger burn" and avoid "finger skipping." To provide an improved touch experience and responsiveness, in some implementations the touch panel has multi-touch functionality, such as less than 2 frames (30 Hz) per static view during a pinch zoom, and less than 1 cm single-touch functionality per frame (30 Hz) with 200 ms (delay from finger to pointer). In some embodiments, the display supports edge-to-edge glass with a minimum screen border that also terminates flush with the field surface, as well as limited I / O interference when using multi-touch.

For perceptual computing and other purposes, various sensors may be present within the system and may be connected to the processor 1210 be coupled in different ways. Certain inertial and environmental sensors can work with the processor 1210 over a sensor stroke 1240 , z. B. via an I2C interconnection, be coupled. In the in 12 In the embodiment shown, these sensors can be an accelerometer 1241 , an ambient light sensor (ALS) 1242 , a compass 1243 and a gyroscope 1244 lock in. Other environmental sensors may include one or more thermal sensors 1246 in some embodiments, via a system management bus (SMBus) to the processor 1210 couple.

Using the various inertial and environmental sensors present in a platform, many different applications can be realized. These applications allow for advanced computational operations, including perceptual computing, and also allow for performance management / battery life, security, and system responsiveness improvements.

For example, in terms of power management / battery life issues, ambient light conditions, at least in part based on information from an ambient light sensor, are determined at a location of the platform and the intensity of the display is controlled accordingly. Thus, the power consumption during operation of the display is reduced under certain lighting conditions.

Regarding security operations, based on context information obtained from the sensors, such as location information, it may be determined whether a user is allowed to access certain secure documents. For example, a user may be allowed to access such documents at a workstation or at home. However, the user is prevented from accessing such documents when the platform is in a public place. This determination is based in one embodiment on location information, e.g. B. determined by a GPS sensor or camera recognition of landmarks. Other security operations may include providing for pairing devices within short distances of each other, e.g. A portable platform as described herein, and a desktop computer, a cell phone, etc. of a user. Some sharing is realized in some implementations via near field communication when these devices are so paired. However, if the devices exceed a certain distance, such sharing may be disabled. Further, when a platform and a smartphone described herein are paired, a warning may be configured to be triggered when the devices move farther apart than a predetermined distance when in a public location. In contrast, if these paired devices are in a secure location, e.g. As a workplace or at home, exceed this predetermined limit, without triggering such a warning.

The responsiveness can also be improved using the sensor information. For example, even when a platform is in a low power state, the sensors may be capable of being operated at a relatively low frequency. Accordingly, any changes in a location of the platform are determined, e.g. As determined by inertial sensors, a GPS sensor or the like. If no such changes have been registered, a faster connection to a previous wireless hub, such as a Wi-Fi ™ access point or similar wireless enabler, occurs because in this case it is not necessary to scan for available wireless network resources. Thus, a higher level of responsiveness is achieved when switching from a low power state to a standby state.

It is understood that many other applications may be enabled using sensor information obtained via the integrated sensors within a platform described herein, and the above examples are for illustrative purposes only. Using a system as described herein, a perceptual computing system may allow addition of alternative input modalities, including gesture recognition, and allow the system to capture user operations and intentions.

In some embodiments, one or more infrared or other thermal sensing elements or any other elements for detecting the presence or movement of a user may be present. Such sensing elements may include several different elements that work together, operate sequentially, or both. For example, sensing elements include elements that provide initial detection, such as light or sound projection, followed by gesture recognition detection by, for example, an ultrasonic transit time camera or a textured light camera.

Also, in some embodiments, the system includes a light generator to create a line of illumination. In some embodiments, this line provides a visual indication of a virtual boundary, namely an imaginary or virtual location in space, where an action of the user to traverse or break through the virtual boundary or plane is interpreted as an intent to interact with the computing system , In some embodiments, the illumination line may change colors as the computing system transitions to different states with respect to the user. The lighting line may be used to provide a visual indication to the user about a virtual boundary in space and may be used by the system to determine state transitions of the computer to the user, including determining when the user wishes to interact with the computer.

In some embodiments, the computer captures the user position and operates to interpret the movement of a user's hand through the virtual border as a gesture indicating an intention of the user to interact with the computer. In some embodiments, when traversing through the virtual line or plane, the light generated by the light generator may change, giving visual feedback to the user that the user has entered a gestural providing area for input to provide for the computer.

Display screens may display visual indications of state transitions of the computing system to a user. In some embodiments, a first screen is provided in a first state in which the presence of a user is detected by the system, such as by using one or more of the sensing elements.

In some implementations, the system acts to capture a user identity, such as by face recognition. Here, a transition to a second screen may be provided in a second state in which the computing system has recognized the user identity, which second screen provides visual feedback to the user that the user has transitioned to a new state. A transition to a third screen may take place in a third state in which the user has acknowledged the recognition of the user.

In some embodiments, the computing system may use a transition mechanism to determine a location of a virtual boundary for a user, where the location of the virtual boundary may change with user and context. The computing system may generate a light, such as a lighting line, to indicate the virtual boundary for interacting with the system. In some embodiments, the computing system may be in a wait state and the light may be generated in a first color. The computing system may recognize whether the user has crossed the virtual boundary, such as by detecting the presence and movement of the user using sensing elements.

In some embodiments, if it is detected that the user has exceeded the virtual boundary (such as having the user's hands closer to the computing system than to the virtual boundary), the computing system may transition to a state for receiving gesture input from the user, wherein a mechanism for indicating the transition may include the virtual boundary indicating light changing to a second color.

In some embodiments, the computing system may then determine if gesture movement has been detected. If gesture movement is detected, the computing system may proceed with a gesture recognition process that may include using data from a gesture data library that may reside in memory in the computing device or that may otherwise be accessed by the computing device.

If a user's gesture is detected, the computing system may perform a function in response to the input and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not detected, the computing system may transition to an error condition where a fault state indicating mechanism may include the virtual boundary indicating light changing to a third color, the system receiving additional gestures returns when the user is within the virtual boundary to interact with the computing system.

As mentioned above, in other embodiments, the system may be configured as a convertible tablet system that may be used in at least two modes, a tablet mode and a notebook mode. The convertible system can have two fields, a display field and a base field, so that the two fields are stacked in tablet mode in a stack. In tablet mode, the display panel faces outward and can provide touchscreen functionality found in traditional tablets. In notebook mode, the two fields can be arranged in an open shell configuration.

In various embodiments, the accelerometer may be a 3-axis accelerometer having data rates of at least 50 Hz. A gyroscope may also be included, which may be a 3-axis gyroscope. In addition, an e-compass / magnetometer may be present. Also, one or more proximity sensors may be provided (eg, for "lid open" for sensing when a person is near the system (or not) and adjusting performance to extend battery life). For the sensor fusion capability of some OS, picking up the accelerometer, gyroscope and compass can provide improved features. In addition, wake-up of sensor mechanisms may be implemented via a real-time clock (RTC) sensor hub to receive sensor inputs when a remainder of the system is in a low power state.

In some embodiments, an internal lid / indicator open switch or sensor may be present to indicate when the lid is closed / open and may be used to place the system in a connected standby state or to automatically wake from the connected standby state. Other system sensors may include ACPI sensors for internal processor, memory, and skin temperature monitoring to allow for changes in processor and system operating states based on sensed parameters.

In one embodiment, the OS can be a Microsoft ^® Windows ^® 8 OS, the Connected Standby (referred to herein as Win8 CS) implemented. Windows 8 Connected Standby, or another OS having a similar state, can provide very low ultra-up-time performance through a platform as described herein to allow applications to stay connected at very low power consumption, e.g. With a cloud-based location. The platform can support 3 performance states, namely screen on (normal); Connected Standby (as a default "off" state) and shutdown (zero watts power consumption). Thus, the platform is logically on in the Connected Standby state (at minimum power levels), even when the screen is off. In such a platform, application power management can be made transparent and maintain a constant connection, in part because of offload technology to allow the lowest power component to perform an operation.

Also is in 12 recognizable that various peripheral devices via a low pin count (LPC) switching with the processor 1210 couple. In the embodiment shown, various components may be implemented by an embedded controller 1235 be coupled. Such components can be a keyboard 1236 (eg coupled via a PS2 interface), a fan 1237 and a thermal sensor 1239 lock in. In some embodiments, the touchpad 1230 also via a PS2 interface to the EC 1235 couple. In addition, a security processor such as a Trusted Platform Module (TPM) may be used. 1238 according to the Trusted Computing Group (TCG) TPM Specification, Version 1.2 , from 2 Oct. 2003 , via this LPC interconnect with the processor 1210 couple. It should be understood, however, that the scope of the present invention is not limited in this regard, and that secure processing and storage of secure information may reside at another secure location, such as static random access memory (SRAM) in a security coprocessor, or as encrypted data blobs that are decrypted only when protected by a Secure Enclave (SE) processor mode.

In a particular implementation, peripheral ports may include a high-definition media interface (HDMI) connector (which may have various form factors, such as normal-sized, mini, or micro); one or more USB ports, such as normal-sized external ports according to the Universal Serial Bus Revision 3.0 specification (November 2008) with at least one power supply for charging USB devices (such as smartphones) when the system is in the connected standby mode. Condition and plugged into a wall outlet. In addition, one or more Thunderbolt ™ ports may be provided. Other ports may include an externally accessible card reader, such as a standard size SD-XC card reader and / or a WWAN SIM card reader (eg, an 8-pin card reader). For audio, there may be a 3.5mm jack with stereo sound and microphone capability (eg, combination functionality) with support for jack detection (eg, just headset support using the microphone in the lid or headphones with Microphone in the cable). In some embodiments, this jack may be convertible between stereo headphone and stereo microphone input. Also, a power plug may be provided for coupling to an AC support.

The system 1200 can communicate with external devices in a variety of ways, including wirelessly. In the in 12 In the embodiment shown, various wireless modules are present, each of which may correspond to a radio configured for a particular wireless communication protocol. One way for short range wireless communication, such as a near field, may be via a near field communication (NFC) unit 1245 done in one embodiment with the processor 1210 can communicate via an SMBus. It should be noted that about this NFC unit 1245 Devices can communicate in close proximity to each other. For example, a user can make it to the system 1200 enable with another (eg) portable device, such as a user's smartphone, to closely match the two devices and to allow transmission of information such as identification information, payment information, data such as image data, or like to communicate. Wireless power transmission may also be performed using an NFC system.

Using the NFC unit described herein, users can position fixtures side-by-side and side-by-side fixtures for near field coupling functions (such as near field communication and wireless power transfer (WPT)) by utilizing the coupling between coils of one or more of these devices. In particular, embodiments provide devices with strategically shaped and placed ferrite materials to achieve better coupling of the coils. Each coil has an inductance associated therewith that can be selected together with the resistive, capacitive and other features of the system to provide a common resonant frequency for the system.

As in 12 Further, additional wireless units may include other short-range wireless engines, including a WLAN unit 1250 and a bluetooth unit 1252 , Using the WLAN unit 1250 Wi-Fi ™ communications can be realized according to a predetermined 802.11 standard of the Institute of Electrical and Electronics Engineers (IEEE), whereas via the Bluetooth unit 1252 Short range communications can take place via a Bluetooth protocol. These units can work with the processor 1210 For example, communicate via a USB connection or a Universal Asynchronous Receiver Transmitter (UART) connection. Or, these devices can be interconnected using a Peripheral Component Interconnect Express ™ (PCIe ™) protocol, such as PCI. For example, according to the PCI Express ™ Specification Base Specification, Version 3.0 (published January 17, 2007), or other such protocol, such as a Serial Data Input / Output (SDIO) standard, to the processor 1210 couple. Of course, the actual physical connection between these peripheral devices, which may be configured on one or more add-in cards, may be through the NGFF connector mounted on a motherboard.

In addition, wide area wireless communications, e.g. B. according to a cellular or other wireless wide area protocol, via a WWAN unit 1256 which in turn is sent to a Subscriber Identity Module (SIM). 1257 can couple. In addition, also a GPS module 1255 be present to allow reception and use of location information. It should be noted that in the in 12 shown embodiment, the WWAN unit 1256 and an integrated detection unit, such as a camera module 1254 , can communicate over a given USB protocol, such as a 2.0 or 3.0 connection, or a UART or I2C protocol. Again, the actual physical connection of these units can be made by adapting an NGFF mezzanine card to an NGFF connector configured on the motherboard.

In a particular embodiment, wireless functionality may be modular, e.g. For example, with a WiFi ™ 802.11ac solution (for example, an add-in card that is backwards compatible with IEEE 802.11abgn) with support for Windows 8 CS. This card may be configured in an internal slot (for example, via an NGFF adapter). An additional module may provide Bluetooth capability (eg Bluetooth 4.0 with backward compatibility) as well as ^Intel® Wireless Display functionality. Additionally, NFC support may be provided via a separate device or multifunction device, and may be arranged as an example of easy access in a right front portion of the housing. Yet another add-on module may be a WWAN device that can provide support for 3G / 4G / LTE and GPS. This module can be implemented in an internal slot (for example, an NGFF slot). Integrated antenna support can be provided for WiFi ™, Bluetooth, WWAN, NFC and GPS, allowing a seamless transition from WiFi ™ to WWAN radios, wireless Gigabit (WiGig) according to the Wireless Gigabit specification (July 2010) and vice versa.

As described above, an integrated camera can be integrated in the lid. For example, this camera can be a high-resolution camera, the z. B. has a resolution of at least 2.0 megapixels (MP) and can go beyond 6.0 MP.

To provide audio inputs and outputs, an audio processor can use a digital signal processor (DSP) 1260 be implemented with the processor 1210 via a high definition audio (HDA) connection. Similarly, the DSP 1260 with an integrated coder / decoder (CODEC) and amplifier 1262 communicate, in turn, to output speakers 1263 can be implemented within the housing. Similarly, the amplifier and CODEC 1262 be coupled to audio inputs from a microphone 1265 In one embodiment, this may be implemented via dual-array microphones (such as a digital microphone array) to support high-quality audio inputs to enable voice-activated control of various operations within the system. It should be noted that audio outputs from the amplifier / CODEC 1262 to a headphone jack 1264 can be provided. Although in the embodiment of 12 With these particular components shown, it should be understood that the scope of the present invention is not limited thereto.

In a particular embodiment, the digital audio codec and amplifier are capable of driving the stereo headphone jack, the stereo microphone jack, an internal microphone array and stereo speakers. In various implementations, the codec may be integrated into an audio DSP or coupled to a peripheral controller hub (PCH) via an HD audio path. In some implementations, in addition to integrated stereo speakers, one or more subwoofers may be provided and may support the DTS audio speaker solution.

In some embodiments, the processor 1210 by an external voltage regulator (VR) and several internal voltage regulators integrated within the processor die, which are referred to as fully integrated voltage regulators (FIVRs). Using multiple FIVRs in the processor allows components to be grouped into separate power levels so that power is controlled by the FIVR and delivered only to those components in the group. During power management, a given power level may be powered down or off by one FIVR when the processor is placed in a certain low power state while another power level of another FIVR remains active or under full power.

In one embodiment, during some deep sleep states, a power hold level may be used to power up the I / O pins for some I / O signals, such as the interface between the processor and a PCH, the interface with the external VR, and the interface with the EC 1235 , This power hold level also powers an on-die voltage regulator that supports the onboard SRAM or other cache that stores the processor context during sleep. The power hold level is also used to power up the wake-up logic of the processor, which monitors and processes the various wake-up source signals.

During power management, the power hold level remains under power to support the above components while other power levels are shut down or off when the processor enters certain deep sleep states. However, this can lead to unnecessary power consumption or loss if these components are not needed. To accomplish this, embodiments may provide a connected standby sleep state to maintain processor context using a dedicated performance level. In one embodiment, the connected standby sleep state enables processor awakening using resources of a PCH that may itself be present in a package with the processor. In one embodiment, the connected standby sleep state allows the maintenance of processor architecture functions in the PCH until processor awakening, thereby enabling the shutdown of all of the unnecessary processor components that had previously powered up during deep sleep, including turning off all clocks. In one embodiment, the PCH includes a time stamp counter (TSC) and connected standby logic for controlling the system during the connected standby state. The integrated voltage regulator for the power hold level can also be located on the PCH.

In one embodiment, during the connected standby state, an integrated voltage regulator may function as a dedicated power level that remains powered up to support the dedicated cache memory in which the processor context is stored, such as critical state variables, if so Processor enters deep sleep state and connected standby state. This critical state may include state variables associated with the architectural, microarchitectural, debug state, and / or similar state variables associated with the processor.

The wake-up source signals from the EC 1235 may be sent to the PCH during the Connected Standby state, rather than to the processor, so that the PCH can manage wake-up processing instead of the processor. In addition, the TSC is maintained in the PCH to enable maintenance of processor architecture functions. Although in the embodiment of 12 With these particular components shown, it should be understood that the scope of the present invention is not limited thereto.

Power control in the processor can lead to increased power savings. For example, power can be allocated dynamically between cores, individual cores can change the frequency / voltage, and several deep sleep states can be provided to allow very low power consumption. In addition, a dynamic control of the cores or of independent core sections support reduced power consumption by shutting down components when not in use.

Some implementations may provide a specific power management IC (PMIC) to control platform performance. Using this solution, a system can experience very little (e.g., less than 5%) battery degradation for an extended duration (eg, 16 hours) when in a given standby state, as if it were is in a Win8 Connected Standby state. In a Win8 hibernation, a battery life, the z. B. 9 hours, can be realized (eg at 150 nits). With regard to video playback, a long battery life can be realized, e.g. For example, full HD video playback can take place for a minimum of 6 hours. A platform may in one implementation have an energy capacity of e.g. For example, have 35 watt-hours (Wh) for a Win8 CS using an SSD and (eg) 40-44 Wh for Win8 CS using an HDD with an RST cache configuration.

A particular implementation may provide support for a 15W rated thermal design power (TDP) CPU with a configurable CPU TDP up to a TDP design point of approximately 25W thermal features have minimal vents. In addition, the platform is pillow friendly (by not blowing hot air to the user). Different maximum temperature points can be realized depending on the case material. In one implementation of a plastic housing (having at least one plastic lid or base portion), the maximum operating temperature may be 52 degrees Celsius (C). And in one implementation of a metal housing, the maximum operating temperature may be 46 ° C.

In various implementations, a security module, such as a TPM, may be integrated into a processor or may be a discrete device, such as a TPM 2.0 device. With an integrated security module, also known as Platform Trust Technology (PTT), BIOS / firmware can be enabled to provide certain hardware features for certain security features, including more secure commands, secure boot, ^Intel® Anti-Theft Technology, and ^Intel® Identity Protection Technology , Intel ^® Trusted Execution Technology (TXT) and make Intel ^® Manageability Engine Technology along with secure user interfaces, such as a secure keyboard and a secure display available.

Although the present invention has been described with reference to a limited number of embodiments, those skilled in the art will recognize numerous modifications and variations thereof. It is intended by the appended claims to cover all such modifications and variations that are within the true spirit and scope of this present invention.

A design can go through different stages, from design to simulation to manufacture. Data representing a design may represent the design in a number of ways. First, hardware, which is useful in simulations, can be represented using a hardware description language or other functional description language. In addition, at some stages of the design process, a circuit level model with logic and / or transistor gates may be created. In addition, most designs achieve a level of data at one time, representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor manufacturing techniques are used, the data representing the hardware model may be the data that specifies the presence or absence of various features on different mask layers for masks used to fabricate the integrated circuit. In any representation of the design, the data may be stored in any form of machine-readable medium. A memory or magnetic or optical storage, such as a disk, may be the machine-readable medium for storing information transmitted via optical or electrical waves that are modulated or otherwise generated to transmit such information. When an electric carrier wave indicating or carrying the code or design is transmitted insofar as copying, buffering or retransmission of the electrical signal is performed, a new copy is made. Thus, a communications provider or network provider may store, on a tangible, machine-readable medium, at least temporarily, an element, such as information encoded in a carrier wave, implementing techniques of embodiments of the present invention.

A module as used herein refers to any combination of hardware, software and / or firmware. For example, a module includes hardware, such as a microcontroller, associated with a nonvolatile medium to store code designed to be written by the computer Microcontroller to be executed. Reference to a module thus, in one embodiment, refers to the hardware that is specifically configured to recognize and / or execute the code to be held on a nonvolatile medium. Furthermore, the use of a module in another embodiment relates to the nonvolatile medium including the code that is specifically adapted to be executed by the microcontroller to perform predetermined operations. As can be seen, the term module (in this example) may refer to the combination of the microcontroller and the non-volatile medium in yet another embodiment. Module boundaries, shown as separate, typically vary often and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially maintaining independent hardware, software, or firmware. In one embodiment, the use of the term "logic" includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

The use of the term "to" or "designed to" in one embodiment relates to arranging, assembling, manufacturing, offering for selling, importing, and / or designing a device, hardware, logic, or item to perform a designated or specific task , In this example, a device or element thereof that is not operating is still "configured to" perform a designated task when it is designed, coupled, and / or interconnected to perform the designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate that is "configured" to provide a strobe enable signal does not include every potential logic gate that can provide a 1 or a 0. Instead, the logic gate is one that is coupled in a manner in which, during operation, the output 1 or 0 is to enable the clock. It should be noted once again that the use of the term "designed for" does not require operation, but instead focuses on the latent state of a device, hardware, and / or element, with the device's latent state, hardware, and / or of the element is designed to perform a particular task when the device, the hardware and / or the element is in operation.

Further, in one embodiment, the use of the terms "capable of" and / or "operable for" pertains to a device, logic, hardware, and / or element that is configured to support the use of the device, logic, hardware, and / or enable the element in a specified way. It should be noted, as noted above, that in one embodiment the use of "capable of" or "operable for" refers to the latent state of a device, logic, hardware, and / or element, wherein the device, logic, hardware, and / or the element is not in operation, but is designed in such a way as to enable the use of a device in a specified manner.

As used herein, a value includes any known representation of a number, state, logic state, or binary logic state. Often, the use of logic levels, logic values, or logical values is also referred to as ones and zeros, which is simply binary logic states. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a memory cell, such as a transistor or flash cell, may be capable of holding a single logical value or values. However, other representations of values have been used in computer systems. For example, the decimal number ten may also be a binary value of 1010 and a hexadecimal letter A are displayed. Therefore, a value includes any representation of information that can be held in a computer system.

In addition, states can be represented by values or sections of values. For example, a first value, such as a logical one, may represent a default or initial state, whereas a second value, such as a logical zero, may represent a non-standard state. Additionally, in one embodiment, the terms "reset" and "set" refer to a standard or updated value or state, respectively. For example, a default value potentially includes a high logical value, that is, reset, whereas an updated value potentially includes a low logical value, that is, set. It should be noted that any combination of values can be used to represent any number of states.

The embodiments of methods, hardware, software, firmware, or code set forth above may be implemented via instructions stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium executable by a processing element. A non-volatile, machine-accessible / readable medium closes everyone A mechanism that provides information (that is, stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a nonvolatile, machine accessible medium includes random access memory (RAM) such as static RAM (SRAM) or dynamic RAM (DRAM); ROME; a magnetic or optical storage medium; Flash memory devices; electric storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which must be distinguished from the non-volatile media that can receive information therefrom.

Instructions used to program logic to perform embodiments of the invention may be stored within memory in the system, such as a DRAM, cache, flash memory, or other storage. In addition, the commands can be distributed over a network or other computer-readable media. Thus, a machine readable medium may include, among other things, any mechanism for storing or transmitting information in a form that can be read by a machine (e.g., a computer), such as floppy disks, optical disks, compact disc read only memories (CD ROMs), read only memory (ROMs), random access memory (RAM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), magnetic or optical cards, flash memory, or tangible, machine readable storage in the transmission of information over the Internet via electrical, optical, acoustic or other forms of propagated signals (for example, carrier waves, infrared signals, digital signals, etc.). The computer-readable medium thus includes any type of tangible machine-readable medium suitable for storing or transmitting electronic commands and information in a form readable by a machine (e.g., a computer).

Throughout, in this specification, reference to "one embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The occurrences of the term "in one embodiment" in various places throughout the present description therefore do not necessarily all refer to the same embodiment. In addition, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the foregoing specification, a detailed description has been made with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the description and drawings are to be considered in an illustrative sense and not in a limiting sense. Moreover, the prior use of embodiment and other exemplary language does not necessarily contemplate the same embodiment or example, but may involve other and different embodiments as well as potentially the same embodiment.

The systems, methods, and devices may include any of the following examples, or a combination thereof:

Example 1 is a method of configuring a downstream component connected to a host component via a Peripheral Component Interconnect Express (PCle) compliant connection, the method including receiving, from the downstream component, an enhanced capability display; Determining, from the display, one or more configuration parameters for the downstream component; Applying the one or more configuration parameters and performing data signal or control signal transfers over the PCIe compliant connection with the downstream component based at least in part on the one or more applied configuration parameters.

Example 2 may include the subject matter of Example 1, wherein receiving the enhanced capability display includes receiving a Designated Vendor Specific Extended Capability (DVSEC) definition.

Example 3 may include the subject matter of any of Examples 1-2, wherein the enhanced capability display includes an indication of a number of buses that the downstream component uses to perform data signal and control signal transmissions.

Example 4 may include the subject matter of any of Examples 1-3, and may also include associating a number of buses for the downstream component based on the received expanded capability indication.

Example 5 may include the subject matter of any of Examples 1-4, wherein the enhanced capability display includes an indication of a type of port on the connected downstream device connected to the host component.

Example 6 may include the subject matter of any of Examples 1-5, further comprising applying one or more software policies based on the type of port displayed by the enhanced capability display.

Example 7 may include the subject matter of any of Examples 1-6, wherein the enhanced capability indication includes an indication that the downstream component supports a D3Cold power management substate.

Example 8 may include the subject matter of any of Examples 1-7, further comprising applying one or more runtime performance management mechanisms to enable the downstream component to transition to and exit the D3Cold power management sub-state and into one D0 power state when exiting the D3Cold power management substatus.

Example 9 may include the subject matter of any of Examples 1-8, wherein the enhanced capability display includes an indication that the downstream component comprises a host router.

Example 10 may include the subject matter of any of Examples 1-9, further comprising applying one or more security policies to the downstream component based on the indication that the downstream component is a host router.

Example 11 may include the subject matter of any of Examples 1-10, wherein the downstream port is a first downstream port, indicating that the downstream component is a host router indicates that the host router is after the outside facing port, the method further comprising refusing a second indication that a second downstream port, after the first downstream port, is a host router.

Example 12 may include the subject matter of any of Examples 1-11, wherein the enhanced capability display includes an indication that the downstream component uses a "safe ejection" feature.

Example 13 may include the subject matter of any of Examples 1-12, the method further comprising extending a user interface to provide a "safe eject" indication and a description of the downstream component to enable a user to perform a method " Safe ejection "before removing the downstream component.

Example 14 may include the subject matter of any of Examples 1-14, wherein the enhanced capability display includes an indication that the downstream component includes a port extensibility feature to daisy chain connection of further downstream components to enable.

Example 15 is a computer program product tangibly executed on non-transitory computer readable media comprising computer program product instructions that, when executed, conform to logic executed on a root port controller compliant with the Peripheral Component Interconnect Express (PCIe) protocol is to receive, from the downstream component, a display of an enhanced capability; Determining, from the display, one or more configuration parameters for the downstream component; Apply the one or more configuration parameters and perform Causing data signal or control signal transfers over the PCIe compliant connection with the downstream component based at least in part on the one or more applied configuration parameters.

Example 16 may include the subject matter of Example 15, wherein receiving the enhanced capability display includes receiving a Designated Vendor Specific Extended Capability (DVSEC) definition.

Example 17 may include the subject matter of any of Examples 15-16, wherein the enhanced capability display includes an indication of a number of buses that the downstream component uses to perform data signal and control signal transmissions.

Example 18 may include the subject matter of any of Examples 15-17, wherein the instructions are to associate a number of buses for the downstream component based on the received enhanced capability indication.

Example 19 may include the subject matter of any of Examples 15-18, wherein the enhanced capability display includes an indication of a type of port on the connected downstream device connected to the host component.

Example 20 may include the subject matter of any of Examples 15-19, wherein the instructions are to apply one or more software policies based on the type of port displayed by the enhanced capability display.

Example 21 may include the subject matter of any of Examples 15-20, wherein the enhanced capability display includes an indication that the downstream component supports a D3Cold power management substate.

Example 22 may include the subject matter of any of Examples 15-21, wherein the instructions are to use one or more runtime performance management mechanisms to enable the downstream component to go into and out of the D3Cold power management substatus and into one D0 power state when exiting the D3Cold power management substatus.

Example 23 may include the subject matter of any of Examples 15-22, wherein the enhanced capability display includes an indication that the downstream component comprises a host router.

Example 24 may include the subject matter of any of Examples 15-23, wherein the instructions are to apply one or more security policies for the downstream component based on the indication that the downstream component is a host router.

Example 25 may include the subject matter of any of Examples 15-24, wherein the downstream port is a first downstream port, indicating that the downstream component is a host router indicates that the host router is after the outside facing port, the method further comprising refusing a second indication that a second downstream port, after the first downstream port, is a host router.

Example 26 may include the subject matter of any of Examples 15-25, wherein the enhanced capability display includes an indication that the downstream component uses a "safe ejection" feature.

Example 27 may include the subject matter of any of Examples 15-26, which instructions are intended to extend a user interface to provide a "safe eject" indication and a description of the downstream component to enable a user to perform a "secure Eject "before removing the downstream component.

Example 28 may include the subject matter of any of Examples 15-27, wherein the enhanced capability display includes an indication that the downstream component is a port Extensibility feature is included to allow daisy-chain connection of further downstream components.

Example 29 is a system that includes a root port compliant with a Peripheral Component Interconnect Express (PCIe) protocol, where the root port includes a root port controller; and a downstream component connected to the root port via a connection compliant with the PCIe protocol, the root port comprising an upstream port, and at least one downstream hot-pluggable port, wherein the at least one hot-pluggable downstream port is coupled to the component through the connection based on the PCIe protocol, the hot-pluggable downstream port comprising logic implemented at least partially in hardware, wherein the Logic for receiving, from the downstream component, an enhanced capability display; Determining, from the display, one or more configuration parameters for the downstream component; Applying the one or more configuration parameters and performing data signal or control signal transfers over the PCIe-compliant connection with the downstream component based at least in part on the one or more applied configuration parameters.

Example 30 may include the subject matter of example 29, wherein receiving the enhanced capability display includes receiving a Designated Vendor Specific Extended Capability (DVSEC) definition.

Example 31 may include the subject matter of any of Examples 29-30, wherein the enhanced capability display includes an indication of a number of buses that the downstream component uses to perform data signal and control signal transmissions.

Example 32 may include the subject matter of any of Examples 29-31, wherein the logic is to allocate a number of buses for the downstream component based on the received enhanced capability indication.

Example 33 may include the subject matter of any of Examples 29-32, wherein the enhanced capability display includes an indication of a type of port on the connected downstream device connected to the host component.

Example 34 may include the subject matter of any of Examples 29-33, wherein the logic is to apply one or more software policies based on the type of port displayed by the extended capability display.

Example 35 may include the subject matter of any of Examples 29-34, wherein the enhanced capability display includes an indication that the downstream component supports a D3Cold power management substate.

Example 36 may include the subject matter of any of Examples 29-35, where the logic is to apply one or more runtime performance management mechanisms to enable the downstream component to switch to and exit the D3Cold power management sub-state and into a D0 power state when exiting the D3Cold power management substatus.

Example 37 may include the subject matter of any of Examples 29-36, wherein the enhanced capability display includes an indication that the downstream component comprises a host router.

Example 38 may include the subject matter of any of Examples 26-37, wherein the logic is to apply one or more security policies for the downstream component based on the indication that the downstream component is a host router.

Example 39 may include the subject matter of any of Examples 29-38, wherein the downstream port is a first downstream port, indicating that the downstream component is a host router indicates that the host router is after the outside facing port, the method further comprising refusing a second indication that a second downstream port, after the first downstream port, is a host router.

Example 40 may include the subject matter of any of Examples 29-39, wherein the enhanced capability display includes an indication that the downstream component uses a "safe ejection" feature.

Example 41 may include the subject matter of any of Examples 29-40, where the logic is to extend a user interface to provide a "safe eject" indication and a description of the downstream component to enable a user to perform a "secure Eject "before removing the downstream component.

Example 42 may include the subject matter of any of Examples 29-40, wherein the enhanced capability display includes an indication that the downstream component includes a port extensibility feature to daisy-chain connection of further downstream components to enable.

Example 43 is a root device that complies with a Peripheral Component Interconnect Express (PCIe) protocol, where the root port includes a root port controller that provides a means for receiving, from the downstream component, a display an extended ability; means for determining, from the display, one or more configuration parameters for the downstream component; means for applying the one or more configuration parameters and means for performing data signal or control signal transfers over the PCIe compliant connection with the downstream component based at least in part on the one or more applied configuration parameters.

Example 44 may include the subject matter of example 43, wherein receiving the enhanced capability display includes receiving a Designated Vendor Specific Extended Capability (DVSEC) definition.

Example 45 may include the subject matter of any of Examples 43-44, wherein the enhanced capability display includes an indication of a number of buses that the downstream component uses to perform data signal and control signal transmissions.

Example 46 may include the subject matter of any of Examples 43-45, further comprising means for allocating a number of buses for the downstream component based on the received expanded capability indication.

Example 47 may include the subject matter of any of Examples 43-46, wherein the enhanced capability display includes an indication of a type of port on the connected downstream device connected to the host component.

Example 48 may include the subject matter of any of Examples 43-47, further comprising means for applying one or more software policies based on the type of port displayed by the enhanced capability display.

Example 49 may include the subject matter of any of Examples 43-48, wherein the enhanced capability display includes an indication that the downstream component supports a D3Cold power management substate.

Example 50 may include the subject matter of any of Examples 43-49, further comprising means for applying one or more runtime performance management mechanisms to enable the downstream component to switch to and exit the D3Cold power management substatus, and switch to a DO power state upon exiting the D3Cold power management sub-state.

Example 51 may include the subject matter of any of Examples 43-50, wherein the enhanced capability display includes an indication that the downstream component comprises a host router.

Example 52 may include the subject matter of any of Examples 43-51, further comprising means for applying one or more security policies for the downstream component based on the indication that the downstream component is a host router.

Example 53 may include the subject matter of any of Examples 43-52, wherein the downstream port is a first downstream port, indicating that the downstream component is a host router indicates that the host router is after the outside facing port, the method further comprising refusing a second indication that a second downstream port, after the first downstream port, is a host router.

Example 54 may include the subject matter of any of Examples 43-53, wherein the enhanced capability display includes an indication that the downstream component uses a "safe ejection" feature.

Example 55 may include the subject matter of any of Examples 43-54, further comprising means for extending a user interface to provide a "safe eject" indication and a description of the downstream component to enable a user to perform a method " Safe ejection "before removing the downstream component.

Example 56 may include the subject matter of any of Examples 43-55, wherein the enhanced capability display includes an indication that the downstream component includes a port extensibility feature to daisy chain connection of further downstream components to enable.

Example 57 is a device that is compatible with a PCIe-based protocol, where the port may be an upstream component of a PCIe root complex, such as a root port or an upstream switch. The device can support hot plug functions. The device may include one or more downstream ports coupled to an upstream port. The at least one downstream port may be a hot-pluggable downstream port. The hot-pluggable downstream port may be configured to be coupled to a downstream component via a hot-plug connection. The downstream component can provide information about advanced features for the device through the hot-plug downstream port. The enhanced functionality information may be received by the device as an indication of vendor-specific advanced functions that identifies one or more registry settings that correspond to or expose one or more advanced features that the downstream component may use. The device may determine one or more configuration parameters for the downstream connected component based on the display. The device may apply the configuration parameters and perform data signal and / or control signal transfers across the PCIe link, the downstream component using the applied configuration parameters.

Example 58 may include the subject matter of Example 57, wherein receiving the extended capability display includes receiving a definition of Designated Vendor Specific Extended Capability (DVSEC) functionality.

Example 59 may include the subject matter of any of Examples 57 or 58, wherein the component is a first component and the enhanced capability display includes an indication of a number of buses using a second component-connected first component for data signal and control signal transmissions perform; and further comprising allocating a number of buses for the second component based on the received extended capability display.

Example 60 may include the subject matter of any of Examples 57-59, wherein the enhanced capability display includes an indication of a type of port on the connected device connected to the downstream port; and further comprising applying one or more software policies based on the type of port displayed by the enhanced capability display.

Example 61 may include the subject matter of any of Examples 57-60, wherein the extended capability indication includes an indication that the component supports a D3Cold power management substate; and further comprising applying one or more runtime performance management mechanisms to allow the downstream component to change to and exit the D3Cold power management sub-state and exit to a DO power state upon exiting the D3Cold power management sub-state.

Example 62 may include the subject matter of any of Examples 57-61, wherein the enhanced capability display includes an indication that the component includes a host router; and further comprising applying one or more policies to the downstream component based on the indication that the component is a host router.

Example 63 may include the subject matter of any of Examples 57-62, wherein the downstream port is a first downstream port, indicating that the component is a host router indicates that the host router is facing outward Port, the method further comprises refusing a second indication that a second downstream port, after the first downstream port, is a host router.

Example 64 may include the subject matter of any of Examples 57-63, wherein the enhanced capability display includes an indication that the component uses a "safe ejection" feature; and further comprising extending a user interface to provide a "safe eject" indication and a description of the component to enable a user to perform a "safe ejection" method prior to removing the component.

Example 65 may include the subject matter of any of Examples 57-64, wherein the enhanced capability display includes an indication that the component includes a port extensibility feature to facilitate daisy chaining of other components; the port further comprising reserving one or more system resources for other components connected to the component device.

Claims (25)

A method of configuring a downstream component connected to a host component via a Peripheral Component Interconnect Express (PCIe) compliant connection, the method comprising: Receiving, from the downstream component, an enhanced capability indicator; Determining, from the display, one or more configuration parameters for the downstream component; Applying the one or more configuration parameters; and Performing data signal or control signal transfers over the PCIe compliant connection with the downstream component based at least in part on the one or more applied configuration parameters. Method according to Claim 1 wherein receiving the enhanced capability display includes receiving a Designated Vendor Specific Extended Capability (DVSEC) definition. Method according to Claim 1 wherein the enhanced capability display includes an indication of a number of buses that the downstream component uses to perform data signal and control signal transmissions, the method further comprising assigning a number of buses to the downstream component based on the received display of extended ability. Method according to Claim 1 wherein the enhanced capability display includes an indication of a type of port on the connected downstream device connected to the host component, the method further comprising applying one or more software policies based on the type of port that is displayed by the expanded ability display. Method according to Claim 1 wherein the enhanced capability indication includes an indication that the downstream component supports a D3Cold power management substate, the method further comprising applying one or more runtime performance management mechanisms to allow the downstream component to enter the D3Cold substate Change power management and exit to a DO power state when exiting the D3Cold power management substatus. Method according to Claim 1 wherein the enhanced capability display includes an indication that the downstream component comprises a host router, the method further comprising applying one or more security policies to the downstream component based on the indication that the downstream component is a host Router is. Method according to Claim 6 wherein the downstream port is a first downstream port, the indication that the downstream component is a host router indicates that the host router is an outbound port, the method further comprising rejecting a second indication in that a second downstream port, after the first downstream port, is a host router. Method according to Claim 1 wherein the enhanced capability indication includes an indication that the downstream component uses a secure ejection feature, the method further comprising applying one or more security policies to the downstream component based on the indication that the downstream component is a host router. System comprising: a root port compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the root port comprising a root port controller; and a downstream component connected to the root port via a connection compliant with the PCIe protocol, the root port controller comprising logic that is at least partially implemented in hardware, the logic being adapted for : Receiving, from the downstream component, an enhanced capability indicator; Determining, from the display, one or more configuration parameters for the downstream component; Applying the one or more configuration parameters; and Performing data signal or control signal transfers over the PCIe compliant connection with the downstream component based at least in part on the one or more applied configuration parameters. System after Claim 9 wherein receiving the enhanced capability display includes receiving a Designated Vendor Specific Extended Capability (DVSEC) definition. System after Claim 9 wherein the enhanced capability indication includes an indication of a number of buses that the downstream component uses to perform data signal and control signal transmissions, wherein the logic allocates a number of buses for the downstream component based on the received enhanced capability indication should. System after Claim 9 wherein the enhanced capability display includes an indication of a type of port on the connected downstream device that is connected to the host component, the logic having one or more software policies based on the type of port represented by the display of the extended ability is displayed, should apply. System after Claim 9 wherein the enhanced capability indication includes an indication that the downstream component supports a D3Cold power management substate, the logic to apply one or more runtime performance management mechanisms to allow the downstream component to enter the substate of D3Cold power management switch to and exit to a DO power state upon exiting the D3Cold power management sub-state. System after Claim 9 wherein the enhanced capability indication includes an indication that the downstream component comprises a host router, the logic having one or more security policies for the downstream component based on the indication that the downstream component is a host router; should apply. System after Claim 14 wherein the downstream port is a first downstream port, the indication that the downstream component is a host router indicates that the host router is an outbound port, the method further comprising rejecting a second indication in that a second downstream port, after the first downstream port, is a host router. System after Claim 9 wherein the enhanced capability display includes an indication that the downstream component is using a "safe ejection" feature, wherein the logic is to extend a user interface to provide a "safe eject" indication and a description of the downstream component to it to allow a user to perform a "safe ejection" method prior to removing the downstream component, System after Claim 9 wherein the enhanced capability indication includes an indication that the downstream component comprises a port extensibility feature to facilitate daisy chaining of further downstream components. A root port device compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the root port comprising a root port controller, comprising: a downstream port for receiving, from a downstream component, an enhanced capability display; means for determining, from the display, one or more configuration parameters for the downstream component; means for applying the one or more configuration parameters; and means for performing data signal or control signal transfers over the PCIe compliant connection with the downstream component based at least in part on the one or more applied configuration parameters. Root port setup after Claim 18 wherein receiving the enhanced capability display includes receiving a Designated Vendor Specific Extended Capability (DVSEC) definition. Root port setup after Claim 18 wherein the enhanced capability display includes an indication of a number of buses that the downstream component uses to perform data signal and control signal transmissions, the root port device further comprising means for allocating a number of buses for the downstream component based on the received enhanced capability display. Root port setup after Claim 18 wherein the enhanced capability display comprises an indication of a type of port on the connected downstream device connected to the host component, the root port device further comprising means for applying one or more software policies based on the type of port indicated by the expanded capability display. Root port setup after Claim 18 wherein the enhanced capability indication includes an indication that the downstream component supports a D3Cold power management substate, the root port device further comprising means for applying one or more runtime performance management mechanisms to enable the downstream component switch to and leave the D3Cold Power Management sub-state and go into a DO power state when exiting the D3Cold Power Management sub-state. Root port setup after Claim 18 wherein the enhanced capability display includes an indication that the downstream component comprises a host router, the root port device further comprising means for applying one or more security policies to the downstream component based on the indication that the downstream component is a host router. Root port setup after Claim 23 wherein the downstream port is a first downstream port, the indication that the downstream component is a host router indicates that the host router is an outbound port, the method further comprising rejecting a second indication in that a second downstream port, after the first downstream port, is a host router. Root port setup after Claim 18 wherein the extended capability indication includes an indication that the downstream component uses a secure ejection feature, the root port device further comprises user interface augmentation means for displaying a secure ejection indication and a description of the To provide a downstream component to allow a user to perform a "safe eject" procedure prior to removing the downstream component.

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