CN116095023B - Self-adapting method for interconnecting bus resources of rapid peripheral components of data processing unit - Google Patents

Self-adapting method for interconnecting bus resources of rapid peripheral components of data processing unit Download PDF

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CN116095023B
CN116095023B CN202310362379.XA CN202310362379A CN116095023B CN 116095023 B CN116095023 B CN 116095023B CN 202310362379 A CN202310362379 A CN 202310362379A CN 116095023 B CN116095023 B CN 116095023B
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peripheral component
component interconnect
bus
data processing
processing unit
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CN116095023A (en
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陈森法
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Zhuhai Xingyun Zhilian Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/65—Re-configuration of fast packet switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application provides a self-adapting method of a rapid peripheral component interconnection bus resource of a data processing unit. The method comprises the following steps: determining bus resources of a root port corresponding to a data processing unit deployed to the root port to implement a switch that supports a function table associated with a peripheral component interconnect express protocol including a first extended function item; scanning downstream devices relative to the root port and identifying devices supporting the first extended function item during the scanning, at least after deploying the data processing unit, and performing a configuration write operation on the first extended function item according to the bus resources to obtain a configured first extended function item; and responding to the configuration writing operation through the data processing unit, and adjusting the topological structure of the switch according to the configured first expansion function item so that the bus resources of the interconnection of the quick peripheral components occupied by the switch do not exceed the bus resources. Thus saving resources and improving efficiency.

Description

Self-adapting method for interconnecting bus resources of rapid peripheral components of data processing unit
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method for adapting a bus resource of a peripheral component interconnect express of a data processing unit.
Background
With the development of technologies such as cloud computing and data centers, input and output resources often need to be customized in digital infrastructure construction, for example, dynamic release and recovery of devices are achieved through data processing units (Data Processing Unit, DPUs), so that the input and output resources can be customized. However, the servers produced by different server vendors may define different device trees, and the resources of the server slots may also be different, so that the DPU vendor may be required to adapt to the customization requirements of different server vendors, server slots, and users. In the prior art, the bus resources of the root port to be deployed of the DPU are determined, for example, the maximum available bus number is determined by checking the equipment tree of the server, the matched DPU firmware is found according to the available bus resources, the proper DPU firmware is programmed through the additional server, and finally the deployment of the DPU can be completed after the server is powered down and powered up. In the prior art, the DPU hardware deployment process requires multiple powering-on and powering-off of the server, and also requires opening a chassis, inserting a DPU card and programming DPU firmware, so that the deployment time is long, and the programming of new DPU firmware is possibly required for changing the server or adjusting the slot configuration each time, which is unfavorable for saving resources and improving efficiency.
Therefore, the application provides a self-adaptive method of the interconnection bus resources of the peripheral components of the data processing unit, which is used for solving the technical problems in the prior art.
Disclosure of Invention
In a first aspect, the present application provides a method for adapting a peripheral component interconnect express bus resource of a data processing unit. The adaptive method comprises the following steps: determining a first bus resource of a first root port corresponding to a data processing unit, wherein the data processing unit is deployed to the first root port to implement a peripheral component interconnect express switch, a topology of the peripheral component interconnect express switch including an upstream port and at least one downstream port for connecting at least one peripheral component interconnect express endpoint, the peripheral component interconnect express switch supporting a first peripheral component interconnect function table associated with a first peripheral component interconnect protocol, the first peripheral component interconnect function table including a first extended function item; scanning downstream peripheral component interconnect devices with respect to the first root port and identifying one or more peripheral component interconnect devices of the downstream peripheral component interconnect devices supporting the first extended function item during scanning at least after deploying the data processing unit to the first root port to implement the peripheral component interconnect express switch, and performing a configuration write operation on the first extended function item in accordance with the first bus resource to obtain a configured first extended function item; and responding to the detection of the configuration writing operation through the data processing unit, and adjusting the topology structure of the PCI express switch according to the configured first expansion function item so that the PCI express bus resources occupied by the PCI express switch do not exceed the first bus resources.
According to the first aspect of the application, when the data processing unit is deployed, different firmware is not required to be selected according to different server models, different firmware is not required to be issued for different servers and slots, a user does not need to install an operating system of a target server in advance and analyze bus resources in a root port of a device tree, operations of programming the firmware, powering on and off the server, opening a case and the like are saved, and resource saving and efficiency improvement are facilitated.
In a possible implementation manner of the first aspect of the present application, the adaptive method is applied in a system start-up phase of a server, where the first bus resource is determined by a basic input output system of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource.
In a possible implementation manner of the first aspect of the present application, the adaptive method is applied to an application stage of a server, where the first bus resource is determined by an operating system kernel of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource.
In a possible implementation manner of the first aspect of the present application, when the adaptive method is applied to a system start-up phase of a server, the first bus resource is determined by a basic input output system of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource, and when the adaptive method is applied to an application phase of the server, the first bus resource is determined by an operating system kernel of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource.
In a possible implementation manner of the first aspect of the present application, the server supports a single root input output virtualization function, and the adaptive method is applied to a system start-up phase of the server and then to an application phase of the server so as to implement the single root input output virtualization function.
In a possible implementation manner of the first aspect of the present application, the first bus resource includes a minimum bus value and a maximum bus value, the first extended function includes a first field and a second field, and performing, according to the first bus resource, the configuration write operation on the first extended function includes: writing the minimum bus value to the first field and writing the maximum bus value to the second field.
In a possible implementation manner of the first aspect of the present application, the first extended function item further includes a third field for indicating a version number of the first peripheral component interconnect express protocol.
In a possible implementation manner of the first aspect of the present application, according to the configured first extended function item, adjusting a topology structure of the peripheral component interconnect express switch so that a peripheral component interconnect express bus resource occupied by the peripheral component interconnect express switch does not exceed the first bus resource, including: and determining a bus value interval corresponding to the PCI express bus resources occupied by the PCI express switch according to the second field included in the configured first extended function item and the initial bus value of the data processing unit.
In one possible implementation manner of the first aspect of the present application, the minimum bus value is Min, the maximum bus value is Max, the initial bus value is P, and the bus value interval is a difference that is not less than P and not greater than Max minus 1.
In a possible implementation manner of the first aspect of the present application, the pci express bus resources occupied by the pci express switch are used for a dynamic device issuing function of the pci express switch.
In a possible implementation manner of the first aspect of the present application, the maximum number of dynamically-issuing peripheral component interconnect physical function devices supported by the dynamic device issuing function of the peripheral component interconnect express switch is based on the first bus resource.
In a possible implementation manner of the first aspect of the present application, the maximum number of dynamically-issuing peripheral component interconnect physical function devices supported by the dynamic device issuing function of the peripheral component interconnect express switch is based on the number of the at least one peripheral component interconnect express endpoints to which the downstream ports included in the topology of the peripheral component interconnect express switch are connected.
In a possible implementation manner of the first aspect of the present application, the upstream port of the topology structure of the peripheral component interconnect express switch is used to support the first extended function item, and the one or more peripheral component interconnect devices are identified by identifying, during the scanning, that the upstream port has support for the first extended function item.
In a possible implementation manner of the first aspect of the present application, the one or more peripheral component interconnect devices correspond to the at least one peripheral component interconnect express endpoint to which a downstream port included in a topology structure of the peripheral component interconnect express switch is connected.
In a possible implementation manner of the first aspect of the present application, the data processing unit is disposed in a first slot of the server by parsing a device tree of the server to determine the first bus resource, where the first slot corresponds to the first root port.
In a possible implementation manner of the first aspect of the present application, the peripheral component interconnect express switch is a primary switch or a secondary switch.
In a second aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects when the computer program is executed.
In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a topology structure of a fast peripheral component interconnect switch based on a data processing unit according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for adapting PCI express bus resources of a data processing unit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a system start-up phase and an application phase of a server according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.
Fig. 1 is a schematic diagram of a topology structure of a peripheral component interconnect express switch based on a data processing unit according to an embodiment of the present application. As shown in fig. 1, the data processing unit 114 is deployed at the root port 112 of the host 110. The data processing unit 114 may be a data processing unit (Data Processing Unit, DPU), also called a data processor, implemented using any suitable technology or architecture for providing a high performance network interface and data processing acceleration. Here, the peripheral component interconnect express switch 120 is implemented based on the data processing unit 114, and the peripheral component interconnect express switch 120 may correspond to any suitable peripheral component interconnect express (Peripheral Component Interconnect express, PCIe) standard. The topology of the data processing unit 114 based PCI express switch 120 shown in FIG. 1 includes an upstream port 122 and three downstream ports, downstream port A130, downstream port B132 and downstream port C134, respectively. Three peripheral component interconnect express (PCIe) endpoints are also implemented based on data processing unit 114, namely peripheral component interconnect express a 140, peripheral component interconnect express B142, and peripheral component interconnect express C144. The topology of the peripheral component interconnect express switch 120 includes three downstream ports that are in one-to-one correspondence with the three peripheral component interconnect express endpoints, wherein downstream port a 130 corresponds to peripheral component interconnect express endpoint a 140, downstream port B132 corresponds to peripheral component interconnect express endpoint B142, and downstream port C134 corresponds to peripheral component interconnect express endpoint C144. The PCI express switch 120 implemented based on the data processing unit 114 provides dynamic provisioning and reclamation capabilities of the device through the connection of at least one downstream port included therein to the PCI express endpoint, which can be used to customize input and output resources. Specifically, the number of PCIe devices that the peripheral component interconnect express switch 120 can dynamically issue, such as the number of PCIe physical function (Physical Function, PF) devices, is based on the number of downstream ports of the peripheral component interconnect express switch 120 (three downstream ports are schematically shown in fig. 1), that is, the peripheral component interconnect express endpoint is connected through the downstream ports of the peripheral component interconnect express switch 120, so as to implement point-to-point data transmission of the PCIe model. For example, there may be a multi-function device (PF), i.e., there are multiple PFs, or there may be a single function device, i.e., a single PF. Thus, the dynamic transmitting capabilities of the devices (e.g., the number of PCIe PF devices that can be dynamically issued) that the peripheral component interconnect express switch 120 has are based on the number of downstream ports of the peripheral component interconnect express switch 120. In general, an uplink port in the topology structure of the peripheral component interconnect express switch 120 occupies a bus, a downlink port occupies a port as a whole, and then a bus is reserved for the peripheral component interconnect endpoint hung under each downlink port, which means that the number of the downlink ports is two plus the number of buses that the peripheral component interconnect express switch 120 needs to occupy. That is, to implement the PCI express switch 120, the number of buses that the data processing unit 114 needs to occupy is the number of downstream ports that the PCI express switch 120 includes plus two. Considering that the number of downstream ports included in the peripheral component interconnect express switch 120 is equal to the number of downstream channels, the number of downstream channels is used to determine the number of PCIe devices, such as PCIe PF devices, that the peripheral component interconnect express switch 120 can dynamically issue, and thus determine the dynamic issuing and recycling capabilities of the devices of the peripheral component interconnect express switch 120. The dynamic issuance and reclamation capabilities of devices, such as the maximum number of PCIe PF devices that can be dynamically issued, implemented by the data processing unit 114 deployed at the root port 112 of the host 110, which is the data processing unit's peripheral component interconnect express switch 120, are limited by the bus resources that the root port 112 can provide, i.e., the maximum number of buses that can be used. In other words, the bus resources of the root port 112 determine the maximum number of downstream channels of the PCI express switch 120 and also determine the maximum number of PCIe PF devices that the PCI express switch 120 can dynamically issue. The number of buses occupied by the data processing unit 114 cannot exceed the bus resources of the root port 112, otherwise a system start-up failure or an application failure may result.
With continued reference to fig. 1, the topology of the peripheral component interconnect express switch 120 shown in fig. 1 is a primary switch, and as described above, the peripheral component interconnect express switch 120 includes a number of downstream ports equal to the number of downstream channels used to determine the number of PCIe devices, such as PCIe PF devices, that the peripheral component interconnect express switch 120 can dynamically issue. In some embodiments, a topology of secondary switches or other more complex switches may be employed. This may provide a greater number of PCIe PF devices with limited bus resources. For switches employing secondary switches or other topologies, there remains a need for a data processing unit 114 deployed at the root port 112 of the host 110 that implements the capability of dynamically issuing and reclaiming devices of the PCI express switch 120, such as the maximum number of PCIe PF devices that can be dynamically issued, limited by the bus resources that the root port 112 can provide, i.e., the maximum number of buses that can be used. Thus, in some embodiments, the PCI express switch 120 may employ any suitable switch topology, such as a secondary switch, and the bus resources of the root port 112 determine the maximum number of downstream channels of the PCI express switch 120 and the maximum number of PCIe PF devices that the PCI express switch 120 may dynamically issue. The number of buses occupied by the data processing unit 114 cannot exceed the bus resources of the root port 112, otherwise a system start-up failure or an application failure may result.
With continued reference to fig. 1, the topology of the pci express switch 120 shown in fig. 1 and based on the data processing unit 114 may be a primary switch as shown in fig. 1 or any other suitable topology such as a secondary switch, and the topology of the pci express switch 120 may include an upstream port and any number of downstream ports for connecting corresponding pci express endpoints. The dynamic issuing and recycling capabilities of the peripheral component interconnect express switch 120 devices, such as the maximum number of PCIe PF devices that can be dynamically issued, are limited by the maximum number of buses that can be used by the root port 112 to which the data processing unit 114 belongs, and the number of buses occupied by the data processing unit 114 cannot exceed the number of buses of the root port 112, which may cause a system start failure or an application to operate normally. The hosts 110 may represent servers deployed by the data processing unit 114, and servers produced by different server vendors may define different device trees, and server slots may also have different resources. In general, a server defines bus resources, such as a range of bus numbers, that each Root Port (Root Port) may occupy through a device tree, such as a peripheral component interconnect (Peripheral Component Interconnect, PCI) tree in the device tree. The root port generally corresponds to a slot, and the data processing unit acquires the bus resource of the root port corresponding to the slot by inserting a certain slot. Different server manufacturers there is own customization. It is necessary to adapt the design of different server vendors, server slots, and data processing units in order to fully utilize the dynamic sending capabilities of the PCIe devices of the data processing units, in view of the fact that if the bus resources occupied by the data processing units exceed the bus resources of the root port, this may cause the server to start up failure during the system startup phase due to insufficient bus resources. Various improvements in the present application are described in detail below in conjunction with other embodiments of the present application, which provide a method for adapting a bus resource for interconnecting peripheral components of a data processing unit.
Fig. 2 is a flow chart of a method for adapting a bus resource of a peripheral component interconnect express (pci) of a data processing unit according to an embodiment of the present application. As shown in fig. 2, the adaptation method includes the following steps.
Step S210: determining a first bus resource of a first root port corresponding to a data processing unit, wherein the data processing unit is deployed to the first root port to implement a peripheral component interconnect express switch, a topology of the peripheral component interconnect express switch includes an upstream port and at least one downstream port for connecting at least one peripheral component interconnect express endpoint, the peripheral component interconnect express switch supports a first peripheral component interconnect function table associated with a first peripheral component interconnect protocol, the first peripheral component interconnect function table including a first extended function item.
Step S220: at least after deploying the data processing unit to the first root port to implement the peripheral component interconnect express switch, scanning downstream peripheral component interconnect devices with respect to the first root port and identifying one or more peripheral component interconnect devices supporting the first extended function item in the downstream peripheral component interconnect devices during the scanning, and performing a configuration write operation on the first extended function item according to the first bus resource to obtain a configured first extended function item.
Step S230: and responding to the detection of the configuration writing operation through the data processing unit, and adjusting the topology structure of the PCI express switch according to the configured first expansion function item so that the PCI express bus resources occupied by the PCI express switch do not exceed the first bus resources.
Referring to the above steps, in step S210, the first bus resource of the first root port corresponding to the data processing unit is determined, and the first bus resource of the first root port may be determined by parsing a device tree of the server, for example, a peripheral component interconnect (Peripheral Component Interconnect, PCI) tree in the device tree, where the first bus resource represents a range of bus resources such as a bus number (including a maximum bus number and a minimum bus number) that the first root port may occupy. The data processing unit is deployed to the first root port to implement the peripheral component interconnect express switch, which means that the peripheral component interconnect express switch is implemented based on the bus resources that the data processing unit and the deployed first root port can provide. The topology of the peripheral component interconnect switch may refer to the topology of the peripheral component interconnect switch 120 shown in fig. 1 based on the data processing unit 114, or any other suitable topology such as a secondary switch. The topology structure of the PCI express switch includes an upstream port and at least one downstream port for connecting with at least one PCI express endpoint. In some embodiments, the topology of the peripheral component interconnect express switch may refer to the topology of the peripheral component interconnect express switch 120 based on the data processing unit 114 shown in fig. 1, for example, the topology may include an upstream port 122 and three downstream ports, namely, a downstream port a 130, a downstream port B132, and a downstream port C134. The PCI express switch supports a first PCI express function table associated with a first PCI express protocol, the first PCI express function table including a first extended function item. Here, the first peripheral component interconnect express protocol may correspond to any suitable peripheral component interconnect express (Peripheral Component Interconnect express, PCIe) standard, or a communication protocol standard through which the PCI organization passes. The first peripheral component interconnect function table represents a function linked list structure associated with the first peripheral component interconnect express protocol for managing functions and features. The configuration space of the peripheral component interconnect express represents the space for information interaction between the software and the device, and is based on a specific peripheral component interconnect express protocol such as a first peripheral component interconnect express protocol. The configuration space for the PCI express may be a set of registers including, for example, endpoint and bridge configurations, and a first PCI express function table. The first peripheral component interconnect function table is generally expanded on the basis of a basic configuration space, and a unidirectional link list structure is formed by storing a head pointer on a pointer register in the basic configuration space, pointing to a next function structure and a corresponding function register through the head pointer, and storing another pointer in each function register for pointing to the next function structure and the corresponding function register. The function structure and the set of function registers on the one-way linked list structure may serve as the first peripheral component interconnect function list, i.e., represent a linked list associated with the first peripheral component interconnect express protocol for managing functions and features. The first peripheral component interconnect feature table, such as an identification number, head pointer, etc. of the feature structure therein, may indicate the features supported by the device that can be used for interaction between the device and the software. Here, the first peripheral component interconnect function table includes a first extended function item. The first expansion function item represents expansion capability or expansion characteristics, and can be expanded on the basis of an original unidirectional linked list structure by adding a new function structure and a corresponding function register, so that the effect that the PCIe expansion characteristics are added to the first peripheral component interconnect function table on the basis of a PCIe point-to-point interaction model defined by the first peripheral component interconnect protocol is achieved. In other words, the first extended function is to add a new function (capability) to the peripheral component interconnect function table (PCI Capabilities List) associated with the first peripheral component interconnect express protocol (e.g., a particular version of the PCIe protocol such as PCIe 4.0 or PCIe 5.0) also called PCI function table to provide an extended capability. The first peripheral component interconnect function table thus obtained includes a first extended function item. Thus, a device supporting the first extended functionality also means having corresponding extension capabilities and having corresponding extension characteristics. In this way, the existing PCIe protocol and PCIe model may be utilized, and by utilizing a function linked list structure for managing characteristics in the PCIe configuration space, that is, the first peripheral component interconnect function table, by adding an expansion capability, that is, making the first peripheral component interconnect function table include the first expansion function item, the subsequent adaptive adjustment may be facilitated.
Continuing with the steps described above, at least after deploying the data processing unit to the first root port to implement the peripheral component interconnect express switch, scanning downstream peripheral component interconnect devices with respect to the first root port and identifying one or more peripheral component interconnect devices supporting the first extended function item in the downstream peripheral component interconnect devices during the scanning, and performing a configuration write operation on the first extended function item according to the first bus resource to obtain a configured first extended function item in step S220. This means that both the scanning device and the performing of the configuration write operation take place after the deployment of the data processing unit to the first root port and the implementation of the PCI express switch. That is, the first bus resources of the first root port need not be adjusted by resource allocation prior to deployment of the data processing unit, but rather are adapted by dynamic adaptation of the data processing unit after deployment of the data processing unit. Specifically, after the data processing unit has been deployed and the peripheral component interconnect express switch has been implemented, in order to ensure that bus resources occupied by the data processing unit (e.g., dynamic issuing and recycling capabilities of devices of the peripheral component interconnect express switch) do not exceed first bus resources of a first root port, thereby avoiding a system start failure or abnormal application situation, scanning a downstream peripheral component interconnect device relative to the first root port, such as a PCI device that is hooked down to the first root port, and during the scanning, using interactions with devices defined by a PCIe protocol, one or more peripheral component interconnect devices supporting the first extended function item in the downstream peripheral component interconnect device may be identified. This exploits the interaction between the software defined by the PCIe protocol and the device and the PCIe configuration space. If one or more peripheral component interconnect devices supporting the first extended function item among the downstream peripheral component interconnect devices are identified, this means that the one or more peripheral component interconnect devices have corresponding extended capabilities and have corresponding extended characteristics. Thus, a configuration write operation is performed on the first extended function item according to the first bus resource to obtain a configured first extended function item. This means that by utilizing the interaction between the software defined by the PCIe protocol and the device and the PCIe configuration space, the configured first extended function item is obtained by performing a configuration write operation on the first extended function item, so that the data processing unit is informed of the critical information of the first bus resource of the first root port. It should be appreciated that after the data processing unit is deployed to the first root port to implement the PCI express switch, if the data processing unit is notified by way of firmware over-write, this means that power down and power up operations of the server are performed, which increases latency and loss. In addition, after the data processing unit is deployed to the first root port so as to implement the pci express switch, if the resource allocation is performed to adjust the first bus resource of the first root port, the power-down operation and the power-up operation of the server are also involved, which also increases delay and brings loss. Therefore, the self-adaptive method for the PCI express bus resources of the data processing unit provided by the embodiment of the invention utilizes interaction between software defined by a PCIe protocol and equipment and PCIe configuration space, and realizes that the key information of the first bus resources of the first root port is notified to the data processing unit after the data processing unit is deployed to the first root port so as to realize the interconnection switch of the PCI express components. Next, in step S230, in response to detecting the configuration write operation, the data processing unit adjusts, according to the configured first extended function item, a topology structure of the peripheral component interconnect express switch so that peripheral component interconnect express bus resources occupied by the peripheral component interconnect express switch do not exceed the first bus resources. This means that the data processing unit is adapted in response to the detected configuration write operation. This means that the adaptation of the data processing unit is driven by the execution of the configuration write operation, whereas it is mentioned above that after deploying the data processing unit to the first root port to implement the fast peripheral component interconnect switch, the device is scanned, one or more peripheral component interconnect devices supporting the first extended function item are identified, and the configuration write operation is performed on the first extended function item. Considering that different server manufacturers, different server slots and different data processing unit manufacturers may have different time consuming processes in deploying the data processing units, scanning the devices and identifying the devices supporting the first extended function item until the configuration write operation is performed, the above-mentioned adaptive adjustment method of the data processing units driven by the execution of the configuration write operation may be well adapted to different server manufacturers, different server slots and different data processing unit manufacturers. Further, the data processing unit performs adaptive adjustment in response to the detection of the configuration write operation, that is, adjusts the topology structure of the peripheral component interconnect express switch according to the configured first extended function item, so that the peripheral component interconnect express bus resources occupied by the peripheral component interconnect express switch do not exceed the first bus resources. Therefore, the system starting failure or the abnormal operation of the application caused by the fact that the bus resources occupied by the data processing unit exceed the bus resources of the root port is effectively avoided, and the dynamic transmitting capacity of PCIe equipment of the data processing unit is fully utilized.
The self-adaptive method of the PCI express bus resource of the data processing unit shown in fig. 2, so that when the data processing unit is deployed, different firmware is not required to be selected according to different server models, but after the data processing unit is deployed to the first root port to realize the PCI express switch, interaction between software defined by PCIe protocol and equipment is utilized, PCIe configuration space is utilized (by scanning equipment, identifying equipment supporting the first extended function item and performing configuration write operation on the first extended function item to obtain the configured first extended function item), so that the data processing unit is informed of the critical information of the first bus resource of the first root port, and further, the data processing unit is enabled to perform self-adaptive adjustment in response to detecting the configuration write operation, that is, the topology structure of the PCI express switch is adjusted according to the configured first extended function item, so that the bus resource of the PCI express module occupied by the PCI express switch does not exceed the first bus resource. Therefore, when the data processing unit is deployed, different firmware is not required to be selected according to different server models, different firmware is not required to be issued for different servers and slots, a user does not need to install an operating system of a target server in advance and analyze bus resources in a root port of a device tree, operations of writing the firmware, powering on and off the server, opening a case and the like are saved, and resource saving and efficiency improvement are facilitated. In addition, the self-adaptive adjustment of the data processing unit can ensure that the bus resources occupied by the data processing unit do not exceed the bus resources of the root port, so that the system start failure or the application failure due to insufficient bus resources is effectively avoided.
In one possible implementation, the adaptive method is applied to a system start-up phase of a server, determining, by a basic input output system (Basic Input Output System, BIOS) of the server, the first bus resource, scanning the downstream peripheral component interconnect device with respect to the first root port, and performing the configuration write operation on the first extended function item according to the first bus resource. In this way, the BIOS determines the first bus resource in the system start-up phase, scans the downstream peripheral component interconnection device corresponding to the first root port, and executes the configuration write operation on the first extended function item according to the first bus resource, so as to implement adaptive adjustment of the data processing unit to adapt to the first bus resource, and after the data processing unit is deployed to the first root port so as to implement the fast peripheral component interconnection switch, the configuration write operation is performed through the BIOS scanning device, which means that resource allocation and firmware selection do not need to be performed in advance, thereby saving resources and improving efficiency at the same time as ensuring that the system start-up phase is smooth.
In a possible implementation manner, the adaptive method is applied to an application stage of a server, the first bus resource is determined by an operating system kernel of the server, the downstream peripheral component interconnect device corresponding to the first root port is scanned, and the configuration writing operation is performed on the first extended function item according to the first bus resource. In this way, by determining the first bus resource in the application phase by the operating system kernel, scanning the downstream peripheral component interconnect device with respect to the first root port, and executing the configuration write operation on the first extended function item according to the first bus resource, the data processing unit is adaptively adjusted to adapt to the first bus resource, and the configuration write operation is performed by the operating system kernel scan device after the data processing unit is deployed to the first root port to implement the peripheral component interconnect switch, which means that resource allocation and firmware selection do not need to be performed in advance, thereby saving resources and improving efficiency while ensuring smooth application phase. Furthermore, in the application stage of the server, the self-adaptive adjustment of the data processor can be performed without powering on and powering off the server, and the system efficiency is effectively improved.
In one possible implementation, when the adaptive method is applied to a system start-up phase of a server, the first bus resource is determined by a basic input output system of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource, and when the adaptive method is applied to an application phase of the server, the first bus resource is determined by an operating system kernel of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource. In some embodiments, the server supports a single root input output virtualization function, and the adaptive method is applied to a system start-up phase of the server and then to an application phase of the server to implement the single root input output virtualization function. Thus, the available bus resources are fully utilized by the adaptive adjustment of the data processing unit without changing the bus resources of the existing root port. Thus, unlike the manner in which bus resources are allocated according to the needs of PCIe devices, adaptive adjustment of a data processing unit means having the data processing unit adapt to the available bus resources. Specifically, if PCIe devices want to normally access to a bus and utilize bus resources, the PCIe devices need to ensure that bus numbers occupied by PCIe devices are within a bus number range of a deployed root port through guidance and configuration of a BIOS in a system start stage, otherwise, system start is unsuccessful; in addition, it is also necessary to ensure that the bus number of the PCIe device is also within the bus number range of the deployed root port during the application phase by the kernel of the operating system. Therefore, in the system start-up phase or the BIOS phase, it is ensured that the bus resources occupied by the data processing unit do not exceed the bus resources of the root port, otherwise, the start-up failure is caused; in addition, in an application stage or a kernel stage after the system is started, bus resources occupied by the data processing unit are ensured not to exceed buses of the Root port, otherwise, certain capabilities of the device such as Single Root I/O Virtualization (SRIOV) function cannot normally operate. Moreover, considering that SRIOV is generally not resolved in the BIOS phase, but in the kernel phase of the operating system, that is, in the application phase, the adaptive method is required to be applied to the system start-up phase of the server and then to the application phase of the server, so as to implement the single root input/output virtualization function.
In one possible implementation, the first bus resource includes a minimum bus value and a maximum bus value, the first extended function includes a first field and a second field, and performing the configuration write operation on the first extended function according to the first bus resource includes: writing the minimum bus value to the first field and writing the maximum bus value to the second field. The specific field names, field definitions, and names of the first extended function items may be defined in terms of PCI organization passing definitions. Here, the first field corresponds to a minimum bus value and the second field corresponds to a maximum bus value. The first and second fields enable the transfer of critical information of the first bus resource to the data processing unit via the first extended function item. In some embodiments, the first extended function item further includes a third field for indicating a version number of the first peripheral component interconnect express protocol. In some embodiments, according to the configured first extended function item, adjusting a topology of the peripheral component interconnect express switch so that a peripheral component interconnect express bus resource occupied by the peripheral component interconnect express switch does not exceed the first bus resource, including: and determining a bus value interval corresponding to the PCI express bus resources occupied by the PCI express switch according to the second field included in the configured first extended function item and the initial bus value of the data processing unit. In some embodiments, the minimum bus value is Min, the maximum bus value is Max, the initial bus value is P, and the bus value interval is a difference that is not less than P and not greater than Max minus 1. In general, in order to ensure that the pci bus resources occupied by the pci switch do not exceed the first bus resources, 1 is subtracted from the maximum bus value, that is, max, so that the bus value interval is not greater than the difference of Max minus 1.
In one possible implementation manner, the PCI express bus resources occupied by the PCI express switch are used for the dynamic device issuing function of the PCI express switch. In some embodiments, a maximum number of dynamically issuable peripheral component interconnect physical function devices supported by a dynamic device issuing function of the peripheral component interconnect express switch is based on the first bus resource. In some embodiments, the maximum number of dynamically-issuable peripheral component interconnect physical function devices supported by the dynamic device issuing function of the peripheral component interconnect switch is based on the number of the at least one peripheral component interconnect endpoint to which the downstream port included in the topology of the peripheral component interconnect switch is connected. In some embodiments, the peripheral component interconnect express physical function device may be a multi-function device (PF), i.e., a plurality of PFs, or may be a single function device, i.e., a single PF. Therefore, the maximum number of dynamically issued peripheral component interconnect physical function devices supported by the dynamic device issuing function of the peripheral component interconnect express switch, that is, the dynamic issuing capability of the devices possessed by the peripheral component interconnect express switch is based on the number of the at least one peripheral component interconnect express endpoints connected by the downstream ports included in the topology of the peripheral component interconnect express switch. In this way, the first bus resource of the deployed first root port is fully utilized to provide the dynamic device issuing function through the adaptive adjustment of the data processing unit.
In a possible implementation manner, an uplink port of a topology structure of the peripheral component interconnect express switch is used to support the first extended function item, and the one or more peripheral component interconnect devices are identified by identifying that the uplink port has support for the first extended function item during a scanning process. In some embodiments, the one or more peripheral component interconnect devices correspond to the at least one peripheral component interconnect endpoint to which a downstream port included in a topology of the peripheral component interconnect express switch is connected. Here, the support for the first extended function item is provided by an upstream port of a topology of the peripheral component interconnect express switch implemented by a data processing unit. The performing of the configuration write operation is also a write operation for the configuration of the upstream port, so that the data processing unit can be informed by performing the configuration write operation after the upstream port of the data processing unit is found to have an expansion capability or an expansion characteristic, by utilizing the expansion function in the configuration space.
In one possible implementation, the data processing unit is deployed at a first slot of the server by parsing a device tree of the server to determine the first bus resource, the first slot corresponding to the first root port. Thus, the first bus resource of the first port corresponding to the first slot is fully utilized.
In one possible implementation, the peripheral component interconnect express switch is a primary switch or a secondary switch. It should be appreciated that the topology of the peripheral component interconnect express switch may be a primary switch as shown in fig. 1 or any other suitable topology such as a secondary switch, and that the topology of the peripheral component interconnect express switch may include an upstream port and any number of downstream ports for connecting corresponding peripheral component interconnect express endpoints.
Fig. 3 is a schematic diagram of a system startup phase and an application phase of a server according to an embodiment of the present application. As shown in fig. 3, during a system start-up phase 310, via a basic input output system 312, the following are performed: analyzing the device tree of the server, determining the bus resources of the root port, scanning PCI devices, identifying PCI devices supporting the expansion function items, and executing configuration writing operation, and finally, the basic input output system 312 and the Data Processing Unit (DPU) are coordinated together, so that the DPU adaptively adjusts the topology structure of the interconnection switch of the peripheral components. The system startup phase and the application phase of the server according to the embodiment of the present application shown in fig. 3 may refer to the foregoing adaptive method for the interconnection bus resources of the peripheral components of the data processing unit shown in fig. 2. The DPU of fig. 3 refers to the adaptation method of fig. 2 to achieve an adaptation of the topology of the peripheral component interconnect express switch. This means that by the bios 312 determining bus resources at the system start-up stage 310, scanning the PCI devices, which are downstream peripheral component interconnect devices with respect to the root port, and performing configuration write operations on the first extended function item according to the bus resources, an adaptive adjustment of the data processing unit is achieved to adapt the bus resources, and the bios 312 scanning devices and performing configuration write operations after deploying the data processing unit to the root port to implement the rapid peripheral component interconnect switch, this means that there is no need to perform resource allocation, select firmware in advance, while saving resources and improving efficiency while ensuring that the system start-up stage is smooth.
With continued reference to fig. 3, after the system startup phase 310 is completed, i.e., the DPU is coordinated with the bios 312 to adaptively adjust the topology of the pci express switch, control is transferred to the boot loader 302 and the device tree of the server may be transferred together. The operating system kernel 322 is then booted by the boot loader 302 and the device tree is passed. In the application phase 320, by the operating system kernel 322, the following are performed: analyzing the device tree of the server, determining the bus resources of the root port, scanning PCI devices, identifying PCI devices supporting the expansion function items and executing configuration writing operation, and finally, the operating system kernel 322 and the DPU are used for realizing the self-adaptive adjustment of the topology structure of the interconnection switch of the rapid peripheral components by the DPU. This means that data processing unit adaptation is implemented at the application stage 320 to adapt bus resources by the operating system kernel 322. Further, in the application stage 320 of the server, the adaptive adjustment of the data processor can be performed without powering on or powering off the server, so that the system efficiency is effectively improved. The system startup phase and the application phase of the server shown in fig. 3 may be suitable for a service scenario in which the DPU needs to be adaptively adjusted in the system startup phase 310 and the application phase 320, respectively, to implement the topology of the fast peripheral component interconnect switch. It should be appreciated that in the system start-up stage 310, the topology of the peripheral component interconnect express switch may be adaptively adjusted by the DPU to ensure that the server starts up normally, while in the application stage 320, it is generally necessary to parse the device tree again to determine bus resources, for example, in order to use a Single Root I/O Virtualization (SRIOV) function of the device, parsing is required in the application stage 320, so that the adaptive method is required to be applied to the system start-up stage 310 of the server first and then to the application stage 320 of the server to implement the Single Root I/O Virtualization function. By the self-adaptive method of the interconnection bus resources of the rapid peripheral component of the data processing unit shown in fig. 2 and the system starting stage and the application stage of the server shown in fig. 3, the self-adaptive adjustment of the data processor can be utilized to fully utilize the available bus resources on the premise of not needing the operations of powering on and powering off the server and opening the case, thereby realizing the functions such as SRIOV and the like, being beneficial to saving resources and improving efficiency.
Fig. 4 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 400 includes: one or more processors 410, a communication interface 420, and a memory 430. The processor 410, communication interface 420, and memory 430 are interconnected by a bus 440. Optionally, the computing device 400 may further include an input/output interface 450, where the input/output interface 450 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 410 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 400 performing various operations may refer to specific details in the above-described embodiments, such as the processor 410 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the present embodiment, the computing device 400 may be configured to implement some or all of the functions of one or more components of the apparatus embodiments described above, and the communication interface 420 may be configured to implement communication functions and the like necessary for the functions of the apparatuses, components, and the processor 410 may be configured to implement processing functions and the like necessary for the functions of the apparatuses, components.
It should be appreciated that the computing device 400 of fig. 4 may include one or more processors 410, and that the processors 410 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the processors 410 may constitute a processor sequence or processor array, or that the processors 410 may be separated into primary and secondary processors, or that the processors 410 may have different architectures such as heterogeneous computing architectures. In addition, the computing device 400 shown in FIG. 4, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 400 may include more or fewer components than shown in fig. 4, or combine certain components, or split certain components, or have a different arrangement of components.
The processor 410 may have various specific implementations, for example, the processor 410 may include one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), which are not limited in this embodiment. Processor 410 may also be a single-core processor or a multi-core processor. Processor 410 may be comprised of a combination of a CPU and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 410 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 420 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.
The memory 430 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 430 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 430 may also be used to store program code and data such that processor 410 invokes the program code stored in memory 430 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 400 may contain more or fewer components than shown in FIG. 4, or may have a different configuration of components.
The bus 440 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. The bus 440 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 4 for clarity of illustration, but does not represent only one bus or one type of bus.
The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated. Embodiments of the present application also provide a system that includes a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.
Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.

Claims (18)

1. An adaptive method for interconnecting bus resources of peripheral components of a data processing unit, the adaptive method comprising:
determining a first bus resource of a first root port corresponding to a data processing unit, wherein the data processing unit is deployed to the first root port to implement a peripheral component interconnect express switch, a topology of the peripheral component interconnect express switch including an upstream port and at least one downstream port for connecting at least one peripheral component interconnect express endpoint, the peripheral component interconnect express switch supporting a first peripheral component interconnect function table associated with a first peripheral component interconnect protocol, the first peripheral component interconnect function table including a first extended function item;
Scanning downstream peripheral component interconnect devices with respect to the first root port and identifying one or more peripheral component interconnect devices of the downstream peripheral component interconnect devices supporting the first extended function item during scanning at least after deploying the data processing unit to the first root port to implement the peripheral component interconnect express switch, and performing a configuration write operation on the first extended function item in accordance with the first bus resource to obtain a configured first extended function item;
and responding to the detection of the configuration writing operation through the data processing unit, and adjusting the topology structure of the PCI express switch according to the configured first expansion function item so that the PCI express bus resources occupied by the PCI express switch do not exceed the first bus resources.
2. The adaptation method according to claim 1, wherein the adaptation method is applied to a system start-up phase of a server, determining the first bus resource by a basic input output system of the server, scanning the downstream peripheral component interconnect device with respect to the first root port, and performing the configuration write operation on the first extended function item according to the first bus resource.
3. The adaptation method according to claim 1, wherein the adaptation method is applied to an application phase of a server, determining the first bus resource by an operating system kernel of the server, scanning the downstream peripheral component interconnect device with respect to the first root port, and performing the configuration write operation on the first extended function item according to the first bus resource.
4. The adaptation method according to claim 1, wherein when the adaptation method is applied to a system start-up phase of a server, the first bus resource is determined by a basic input output system of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource, and when the adaptation method is applied to an application phase of the server, the first bus resource is determined by an operating system kernel of the server, the downstream peripheral component interconnect device with respect to the first root port is scanned, and the configuration write operation is performed on the first extended function item according to the first bus resource.
5. The adaptation method according to claim 4, wherein the server supports a single root input output virtualization function, the adaptation method being applied to a system start-up phase of the server and then to an application phase of the server to implement the single root input output virtualization function.
6. The adaptation method of claim 1, wherein the first bus resource comprises a minimum bus value and a maximum bus value, wherein the first extended function comprises a first field and a second field, and wherein performing the configuration write operation on the first extended function according to the first bus resource comprises: writing the minimum bus value to the first field and writing the maximum bus value to the second field.
7. The adaptation method of claim 6, wherein the first extended function item further comprises a third field for indicating a version number of the first peripheral component interconnect express protocol.
8. The adaptive method of claim 7, wherein adjusting the topology of the peripheral component interconnect express switch according to the configured first extended function such that peripheral component interconnect express bus resources occupied by the peripheral component interconnect express switch do not exceed the first bus resources comprises:
And determining a bus value interval corresponding to the PCI express bus resources occupied by the PCI express switch according to the second field included in the configured first extended function item and the initial bus value of the data processing unit.
9. The adaptive method according to claim 8, wherein the minimum bus value is Min, the maximum bus value is Max, the initial bus value is P, and the bus value interval is a difference of not less than P and not more than Max minus 1.
10. The adaptive method of claim 1, wherein the PCI express bus resources occupied by the PCI express switch are used for dynamic device issuance functions of the PCI express switch.
11. The adaptive method of claim 10, wherein a maximum number of dynamically issuable peripheral component interconnect physical function devices supported by a dynamic device issuing function of the peripheral component interconnect express switch is based on the first bus resource.
12. The adaptive method of claim 11, wherein the maximum number of dynamically-issuable peripheral component interconnect physical function devices supported by the dynamic device issuing function of the peripheral component interconnect switch is based on the number of the at least one peripheral component interconnect endpoint to which the downstream port included in the topology of the peripheral component interconnect switch is connected.
13. The adaptation method according to claim 1, wherein an upstream port of a topology of the peripheral component interconnect express switch is used to support the first extended function item, and wherein the one or more peripheral component interconnect devices are identified by identifying that the upstream port has support for the first extended function item during scanning.
14. The adaptation method according to claim 13, wherein the one or more peripheral component interconnect devices correspond to the at least one peripheral component interconnect endpoint to which a downstream port included in a topology of the peripheral component interconnect express switch is connected.
15. The adaptation method according to claim 1, wherein the data processing unit is deployed at a first slot of the server by parsing a device tree of the server to determine the first bus resource, the first slot corresponding to the first root port.
16. The adaptation method according to claim 1, wherein the peripheral component interconnect express switch is a primary switch or a secondary switch.
17. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 16 when executing the computer program.
18. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 16.
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动态可重构总线数据传输管理方法设计与实现;邓哲 等;计算机工程(第01期);全文 *

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