CN104598354B

CN104598354B - High-end fault-tolerant computer FPGA Special debugging method and device thereof based on soft or hard framework

Info

Publication number: CN104598354B
Application number: CN201510080649.3A
Authority: CN
Inventors: 刘同强; 刘刚; 童圆满; 李仁刚
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2015-02-15
Filing date: 2015-02-15
Publication date: 2016-05-25
Anticipated expiration: 2035-02-15
Also published as: WO2016127953A1; CN104598354A

Abstract

The invention provides a kind of high-end fault-tolerant computer FPGA Special debugging method and device thereof based on soft or hard framework, relate to high-end computer design field. Obtain the Debugging message needing by the debug logic of Host Computer Software Platform control FPGA, and logic function is configurable, crawl information can dynamically show in software. The debug logic of the FPGA signal that configuration captures needs according to upper computer software is organized into specific format, stores in FPGA internal RAM, and the interface section of debug logic packs the data to the packet that communications protocol specifies, sends to USB interface. The packet that upper computer software receives debug logic transmission unpacks, and stores in MySQL database, is dynamically shown to the interface of software simultaneously. Software and hardware communication is carried out communication according to special communications protocol. Obtain than the better analytical effect of logic analyser, and greatly improve the availability of system, reduce debugging risk.

Description

High-end fault-tolerant computer FPGA Special debugging method and device thereof based on soft or hard framework

Technical field

The present invention relates to high-end computer design field, be specifically related to a kind of high-end fault-tolerant computer FPGA Special debugging method and device thereof based on soft or hard framework.

Background technology

Along with the develop rapidly of computer technology, in order to meet the needs of socio-economic development, high performance computer system becomes one of bottleneck of restriction social development key area. The key areas such as finance, telecommunications are high to the performance requirement of computer system, therefore need to build huge multichannel computer system, to better adapt to the application demand in current each field, but high-end computer system stability and a system debug difficult problem are also absorbed on the other hand, high-end computer system need to be used a large amount of fpga chips, and the stability of the internal logic of chip and robustness are most important to stablizing of whole high-end computer system. Therefore, better the internal logic of FPGA Debugging seems even more important more easily, is build and safeguard one of effective ways of highly reliable computer system.

Summary of the invention

In order to address this problem, the invention provides a kind of high-end fault-tolerant computer FPGA Special debugging method based on soft or hard framework, the fpga chip debugging feature using for high-end fault-tolerant computer, adopts soft or hard framework to carry out dynamic configurable debugging. Adopt this framework can obtain than the better analytical effect of logic analyser, and save substantial contribution. More economical in the maintenance of debug system, convenient, and greatly improve the availability of system, reduce debugging risk. Software and hardware architecture refers to, and obtain the Debugging message of needs, and logic function is configurable by the debug logic of Host Computer Software Platform control FPGA, and crawl information can dynamically show in software. The debug logic of the FPGA signal that configuration captures needs according to upper computer software is organized into specific format, stores in FPGA internal RAM, and the interface section of debug logic packs the data to the packet that communications protocol specifies, sends to USB interface. The packet that upper computer software receives debug logic transmission unpacks, and stores in MySQL database, is dynamically shown to the interface of software simultaneously. Software and hardware communication is carried out communication according to special communications protocol.

The present invention also provides a kind of high-end fault-tolerant computer FPGA Special debugging device based on soft or hard framework, comprising:

1) software platform, based on VC6.0+MySQL platform development, friendly interface, can be according to host-host protocol, extracts different messages and dynamically shows. Historical information stores local data base into, can review by the data of database the ruuning situation of system under line.

2), hardware logic, logical gate and fpga logic are simultaneously comprehensive, in fpga chip, move, and carry out transfer of data by USB interface and software platform. The information that hardware logic extracts needs stores local RAM into according to agreement form, and canned data is transferred to software platform according to communications protocol.

3), communications protocol, software and hardware carries out communication by USB interface, adopts self-designed communications protocol in application layer, agreement comprises control message, data message two classes. Control message and be mainly used to carry out the definition of data format, the definition of valid data etc.; Data message is mainly used to transmit Debugging message. Message is by packet header, data, checking data, bag tail composition.

The present invention is directed to the debugging feature of high-end fault-tolerant computer FPGA, utilize software and hardware framework to substitute logic analyser, the fund of having saved has improved again the debugging efficiency of FPGA, and the extracted amount of information is several times as much as again logic analyser simultaneously. It is many that the feature of high-end fault-tolerant computer fpga chip is that logical resource takies, and the utilization rate of IO is higher, and the resource of leaving debugging for is little. Meanwhile, due to code logic complexity, system is in operation and inevitably occurs BUG, can find rapidly in time problem place, has become the difficult point of high-end fault-tolerant computer fpga chip debugging. The present invention utilizes software and hardware architecture platform, has well solved the problems referred to above.

Brief description of the drawings

Fig. 1 is system construction drawing.

Fig. 2 is software system structure figure.

Fig. 3 is software interface figure.

Fig. 4 is hardware logic structure figure.

Fig. 5 is hardware logic control section structure chart.

Fig. 6 is hardware logic hop structure chart.

Fig. 7 is host-host protocol structure chart.

Detailed description of the invention

With reference to the accompanying drawings, design content of the present invention is described.

As described in summary of the invention, in the present invention, mainly comprise: software platform (1), hardware logic (2), communications protocol (3).

According to the feature of high-end fault-tolerant computer FPGA application system, adopt soft or hard framework to debug. The features such as this framework has configurable, uses flexibly, and use cost is low.

Debug system is used, and first needs upper computer software system to be configured the operation of hardware logic, sends configuration message by usb bus, and hardware logic carries out the renewal of corresponding information, the configuration of the pattern of finishing the work according to configuration information. The operation of whole system shop, detect logic and carry out the crawl of Debugging message, and according to configuration mode, Debugging message is packaged, store in RAM according to the form of packet, the interface section of hardware logic, read RAM message, send datagram and process to host computer according to communications protocol regulation.

Upper computer software, receives the data message that hardware platform sends, and separates package operation, and data are stored and shown in interface according to pre-configured pattern. Commissioning staff can real-time detecting system ruuning situation. Historical data in can reading database under line is carried out the analysis of problem.

Claims

1. the high-end fault-tolerant computer FPGA Special debugging method based on soft or hard framework, is characterized in that,

Adopt soft or hard framework to carry out dynamic configurable debugging; Software and hardware architecture refers to by the debug logic of Host Computer Software Platform control FPGA and obtains the Debugging message needing, and logic function is configurable, and crawl information can dynamically show in software; The debug logic of the FPGA signal that configuration captures needs according to upper computer software is organized into specific format, stores in FPGA internal RAM, and the interface section of debug logic packs the data to the packet that communications protocol specifies, sends to USB interface; The packet that upper computer software receives debug logic transmission unpacks, and stores in MySQL database, is dynamically shown to the interface of software simultaneously; Software and hardware communication is carried out communication according to communications protocol.

2. the high-end fault-tolerant computer FPGA Special debugging device based on soft or hard framework, is characterized in that, comprising:

1) software platform, based on VC6.0+MySQL platform development, can be according to host-host protocol, extract different messages and dynamically show; Historical information stores local data base into, can review by the data of database the ruuning situation of system under line;

2), hardware logic, logical gate and fpga logic are simultaneously comprehensive, in fpga chip, move, and carry out transfer of data by USB interface and software platform; The information that hardware logic extracts needs stores local RAM into according to agreement form, and canned data is transferred to software platform according to communications protocol;

3), communications protocol, software and hardware carries out communication by USB interface, application layer adopt communications protocol, agreement comprises control message, data message two classes; Control message and be mainly used to carry out the definition of data format, the definition of valid data; Data message is mainly used to transmit Debugging message.

3. device according to claim 2, is characterized in that, message is by packet header, data, checking data, bag tail composition.