WO2018209673A1 - Field programmable gate circuit and online testing method therefor - Google Patents

Abstract

An online testing method for a field programmable gate circuit, and the field programmable gate circuit. The method comprises: receiving configuration information of a host computer by means of a hardware interface on the field programmable gate circuit (S102); selecting, according to the configuration information, a corresponding signal source from the field programmable gate circuit and configuring sampling parameters (S104); sampling the signal source according to the sampling parameters to obtain sampling data (S106); writing the sampling data into a memory in the field programmable gate circuit (S108); and transmitting the sample data in the memory to the host computer by means of the hardware interface (S110). According to the configuration information, the problem positioning is simple and accurate to implement without requiring a specific JTAP cable. The method is simple and practical, and at the same time, debugging is convenient, especially on-site debugging. There is no need to set up a special hardware environment, and developers do not need to test instruments.

Description

Field programmable gate circuit and online testing method thereof

[Technical Field]

The invention relates to the technical field of circuit testing, in particular to a field programmable gate circuit and an online testing method thereof.

 【Background technique】

FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) is a user-programmable logic device that differs from traditional MCUs (Microcontroller) Unit, Micro Control Unit), which is implemented by hardware, is a hardware circuit that is executed in parallel. Therefore, it is not possible to perform breakpoint debugging and simulation just like developing an MCU.

At present, the mainstream mode of debugging and simulation of field programmable gate circuits is analyzed by using an embedded logic analyzer and an external logic analyzer.

When debugging with the embedded logic analyzer, the designer needs to select the key signals according to the phenomenon, and then recompile and download. This is repeated, which reduces the development efficiency. Especially after the equipment leaves the factory, the on-site debugging environment is even worse, and the traditional methods are more inadequate. obvious. Moreover, it occupies more field programmable gate circuit resources, and when there are many key signals involved, the designer has to make trade-offs, which brings difficulties in problem location.

When debugging with an external logic analyzer, only the signals of the field programmable gate pins can be tested. The internal signals cannot be tested. It is necessary to set up a specific development environment with a specific JTAG (Joint). Test Action Group, Joint Test Working Group) Cables are commissioned and signal acquisition via hardware connections is required, which also creates obstacles to development. And in many cases, developers don't have test instruments at hand.

It can be seen that the debugging mode of the field programmable gate circuit is complicated and the development efficiency is low. Some methods also need to set up a specific development environment, and the accuracy of problem location is not high.

 [Summary of the Invention]

The object of the present invention is to provide a field programmable gate circuit and an online test method thereof for the complicated debugging mode of the field programmable gate circuit in the prior art, the development efficiency is low, and the accuracy of the problem location is not high.

The technical solution adopted by the present invention to solve the above technical problem is to provide an on-line test method for a field programmable gate circuit, comprising: receiving configuration information of a host computer through a hardware interface on the field programmable gate circuit; Determining configuration information from the field programmable gate circuit to select a corresponding signal source and configuring sampling parameters; sampling the signal source according to the sampling parameter to obtain sampling data; writing the sampling data to a field programmable gate a memory internal to the circuit; and transmitting the sampled data in the memory to the host computer through the hardware interface to analyze the sampled data.

Another technical solution adopted by the present invention to solve the above technical problem is to provide a field programmable gate circuit, comprising: a hardware interface, a configuration circuit, a sampling circuit and a memory, wherein the hardware interface is connected to a host computer, and the hardware interface And the sampling circuit is further connected to the sampling circuit, the sampling circuit is further connected to the memory, the memory is further connected to the hardware interface; the hardware interface receives configuration information of the upper computer; the configuration circuit Selecting a corresponding signal source from the field programmable gate circuit according to the configuration information and configuring a sampling parameter; the sampling circuit samples the signal source according to the sampling parameter to obtain sampling data, and samples the sampling Data is written into the memory, and the sample data in the memory is sent to the host computer through the hardware interface to analyze the sampled data.

The invention has the beneficial effects that the hardware interface receives the configuration information of the upper computer, and then samples the signal source in the circuit according to the configuration information, completes the problem location, makes the problem location simple and accurate, and the memory sends the sample data through the hardware interface. Up to the upper computer, no need to cooperate with a specific JTAP cable, simple and practical, at the same time, easy to debug, especially on-site debugging, no need to set up a special hardware environment, developers do not need to test instruments at hand.

 [Description of the Drawings]

The present invention will be further described below in conjunction with the accompanying drawings and embodiments, in which:

1 is a flow chart of an embodiment of an in-circuit test method for a field programmable gate circuit of the present invention;

2 is a schematic structural diagram of an embodiment of an in-circuit test device of a field programmable gate circuit of the present invention;

3 is a schematic diagram of a sampling process of an in-circuit test device of a field programmable gate circuit of the present invention;

4 is a schematic block diagram of an embodiment of a field programmable gate circuit of the present invention.

【detailed description】

The technical solutions of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

FIG. 1 is a flowchart of an embodiment of an online test method for a field programmable gate circuit of the present invention, the method comprising:

S102. Receive configuration information of the host computer through a hardware interface on the field programmable gate circuit.

In this step, the hardware interface is a serial interface.

S104. Select a corresponding signal source from the field programmable gate circuit according to the configuration information, and configure sampling parameters.

In this step, the signal source comes from a functional module internal to the field programmable gate.

S106. Sample the signal source according to sampling parameters to obtain sampling data.

Specifically, in this embodiment, step S106 includes: first, receiving a sampling instruction of the upper computer through the hardware interface, and then sampling the signal source according to the sampling parameter in response to the sampling instruction to obtain sampling data. It can be seen that the sampling source of the host computer can be sampled through the hardware interface, and the signal source can be sampled, and the field operation is convenient. The sampling parameter includes at least one of a sampling frequency, an overall sampling quantity, a trigger signal, and a maximum number of pre-trigger samples. Further, when the sampling parameter includes the sampling frequency, step S106 includes sampling the signal source according to the sampling frequency.

S108. Write sampling data into a memory inside the field programmable gate circuit;

In this step, the memory is a register.

S110: Send sampling data in the memory to the host computer through a hardware interface, to analyze the sampled data.

In this step, the analysis of the sampled data by the host computer depends on the actual use of the host computer, and will not be described in detail within the understanding of those skilled in the art.

In this embodiment, the configuration information of the host computer is received through the hardware interface, and then the signal source in the circuit is sampled according to the configuration information to complete the problem location, so that the problem location is simple and accurate, and the memory sends the sample data through the hardware interface. Up to the upper computer, no need to cooperate with a specific JTAP cable, simple and practical, at the same time, easy to debug, especially on-site debugging, no need to set up a special hardware environment, developers do not need to test instruments at hand.

Specifically, in this embodiment, when the sampling parameter includes the trigger signal in step S106, step S106 includes triggering the signal source by using the trigger signal during the sampling process, and dividing the sampling process by triggering the signal source. For pre-trigger sampling and post-trigger sampling, further, since the sampling process is divided into pre-trigger sampling and post-trigger sampling, step S108 includes dividing the sampling data written into the memory into pre-trigger sampling data and post-trigger sampling data according to the trigger signal. By sampling the signal source to perform sampling, the accuracy of the sampled data is improved, and the positioning of the problem is conveniently completed. The sampled data is divided into pre-trigger sampled data and post-trigger sampled data, which is beneficial to analyzing the sampled data to facilitate on-site The internal functional modules in the programmable gate circuit are tested to improve the accuracy of the test.

Further, specifically, in this embodiment, since the number of sampled data that has been written in the pre-trigger sampling satisfies the maximum number of samples before the triggering configured by the configuration information, the sampled data to be written into the memory according to the trigger signal Distinguishing between pre-trigger sample data and post-trigger sample data includes: when the trigger signal is triggered to the signal source, if the number of sample data that has been written into the memory is less than the maximum number of samples before the trigger, the sample data that has been written into the memory is recorded. The quantity, in turn, uses the number of records to distinguish between the pre-trigger sample data and the post-trigger sample data.

It can be seen that when the signal source is triggered, the pre-trigger sample data and the post-trigger sample data are distinguished by the quantity value of the written sample data, so as to ensure that the sampled data before the trigger reaches a certain number, thereby improving the sampling precision and thereby improving. The accuracy of the test.

Further, in other embodiments of the present invention, the sampling data written in the memory is divided into the pre-trigger sampling data and the post-trigger sampling data according to the trigger signal, including: before the trigger signal is triggered to the signal source, if the memory is written The number of sampled data is equal to the maximum number of samples before the trigger, and the sampled data written to the memory is replaced by the sampled data of the subsequent sampling until the trigger signal triggers the signal source, and after the trigger signal triggers the signal source, the subsequent sampling is performed. The sampled data is written to the remaining space of the memory. Specifically, in this embodiment, replacing the sampled data that has been written into the memory with the sampled data that is subsequently sampled until the trigger signal triggers the signal source includes reading and writing the memory in a shift storage manner, so that the sampled data in the memory The sampled data of the most recent sample for the maximum number of samples before the trigger.

It can be seen that before the signal source is triggered, the number of sampled data that has been written into the memory is equal to the maximum number of samples before the trigger, and the sampled data obtained by the subsequent sampling replaces the sampled data that has been written into the memory to ensure that the sample sampled before the trigger is sampled. The number of sampled data is not greater than the maximum number of samples before the triggering, so that the sampled data after the triggering and written to the memory reaches a certain number, thereby improving the sampling precision, thereby improving the accuracy of the test.

Further, in this embodiment, step S106 includes determining whether the number of sampled data stored in the memory is equal to the total number of samples, and if equal to the total number of samples, stopping sampling. When the number of sampled data written in the memory reaches the total number of samples configured according to the configuration information, the sampling is completed, and this step is real-time, that is, when one sampled data is written into the memory, the number of sampled data in the memory is determined. Whether it is equal to the total number of samples, if not equal, continue sampling, get a sample data, and write the sample data to the memory.

Further, in the embodiment, before the step S108, the data in the memory is cleared to provide a storage space for the sampled data. Before the sampling data sampled in step S106 is written into the memory, the memory is emptied, preparation is made for sampling, and the accuracy of the sampled data is improved.

2 is a schematic structural diagram of an embodiment of an in-circuit test device of a field programmable gate circuit of the present invention. The online test device tests an internal functional module in a field programmable gate circuit by the method in the above embodiment. The hardware interface 210 includes a hardware interface 210, a sampling circuit 230, and a memory 240. The hardware interface 210 is connected to the upper computer. The hardware interface 210 is also connected to the sampling circuit 230 via the configuration circuit 220. The sampling circuit 230 is also connected to the memory 240. Connected to the hardware interface 210. The configuration circuit 220, the sampling circuit 230, and the memory 240 can be implemented by a whole integrated circuit, such as an MCU. In this case, the memory 240 can be a register in the MCU.

The hardware interface 210 is configured to receive configuration information of the upper computer; wherein the hardware interface 210 is a serial interface.

The configuration circuit 220 is configured to select a corresponding signal source from the field programmable gate circuit according to the configuration information and configure the sampling parameter; wherein the selected signal source is from an internal functional module in the field programmable gate circuit, and can be connected through a signal interface The sampling circuit 230 is connected.

The sampling circuit 230 is configured to sample the signal source according to the sampling parameters to obtain sampling data, and write the sampling data into the memory 240. Further, when the host computer reads the sample data in the memory 240, the sample data in the memory 240 is sent to the host computer through the hardware interface 210 to analyze the sample data.

In this embodiment, the configuration information of the host computer is received through the hardware interface, and then the signal source in the circuit is sampled according to the configuration information to complete the problem location, so that the problem location is simple and accurate, and the memory sends the sample data through the hardware interface. Up to the upper computer, no need to cooperate with a specific JTAP cable, simple and practical, at the same time, easy to debug, especially on-site debugging, no need to set up a special hardware environment, developers do not need to test instruments at hand.

In this embodiment, the sampling parameter includes at least one of a sampling frequency, an overall sampling number, a trigger signal, and a maximum number of pre-trigger samples.

Further, in this embodiment, the sampling circuit 230 triggers the signal source by using a trigger signal during the sampling process, and further divides the sampling process into pre-trigger sampling and post-trigger sampling, thereby improving the accuracy of the sampling data and facilitating the completion of the problem. Positioning. Thus, the sampled data is divided into pre-trigger sample data and post-trigger sample data.

The sampling process and working state of the sampling module will be described in detail below with reference to FIG.

When the sampling circuit 230 is in the sampling waiting state, the configuration circuit 220 has selected the signal source according to the configuration information, and configures the sampling parameter. At this time, the hardware interface 210 waits to receive the sampling instruction of the upper computer, and clears the memory 240 inside the field programmable gate circuit. I thought I would prepare for the sampling below. Then, when the hardware interface 210 receives the sampling instruction of the upper computer, the sampling circuit 230 responds to the sampling instruction, and then samples the signal source according to the sampling parameter, and at this time, enters the pre-trigger sampling state.

When the sampling circuit 230 is in the pre-trigger sampling state, the signal source is sampled according to the sampling frequency, and the sampling data is written into the memory 240. Thereafter, the trigger signal triggers the signal source, and the number of sampled data written into the memory 240 is less than the configuration. The maximum number of pre-trigger samples configured by the information, the number of sampled data that has been written into the memory 240 is recorded, and the recorded quantity value indicates the number of sampled data before the trigger, and then the sampling circuit 230 enters the post-trigger sampling state.

When the sampling circuit 230 is in the pre-trigger sampling state, the signal source is sampled according to the sampling frequency, and the sampling data is written into the memory 240. At this time, the trigger signal does not trigger the signal source, that is, before the trigger signal triggers the signal source. The number of sampled data that has been written into the memory 240 is equal to the maximum number of pre-trigger samples configured by the configuration information, and the sampling circuit 230 enters the trigger sampling state, and replaces the sampled data that has been written into the memory 240 by using the sampled data of the subsequent sampling, that is, the subsequent sampling is The memory 240 is synchronously read and written until the trigger signal triggers the signal source. At this time, the sampling circuit 230 enters the post-trigger sampling state.

When the sampling circuit 230 is in the post-trigger sampling state, the signal source continues to be sampled. At this time, the sampling data is the post-trigger sampling data, and the post-trigger sampling data is written into the remaining space of the memory 240, that is, after the trigger signal is triggered to the signal source. , is in the sampling state after the trigger. Subsequently, the sampling circuit 230 enters a sampling end state.

When the sampling circuit 230 is in the sampling end state, at this time, the number of sampling data in the memory 240 is equal to the total sampling number configured by the configuration information.

It should be noted that, during the sampling process in which the sampling circuit 230 samples the signal source, when the hardware interface receives the new sampling instruction of the upper computer, the sampling circuit 230 restarts sampling, that is, shifts to the sampling waiting state, and starts sampling again. .

Further, in the online testing device, the sampling circuit 230 is further connected to the hardware interface 210, and the working state of the sampling circuit 230 is sent to the upper computer through the hardware interface, so that the upper computer can connect the sampling progress at any time.

4 is a schematic structural diagram of a field programmable circuit embodiment of the present invention. The field programmable circuit 400 includes a hardware interface 410, a configuration circuit 420, a sampling circuit 430, a memory 440, and a function circuit 450. The hardware interface 410 and The upper computer is connected, the hardware interface 410 is also connected to the sampling circuit 430 via the configuration circuit 420, the sampling circuit 430 is also connected to the memory 440, the memory 440 is also connected to the hardware interface 410, and the sampling circuit 430 is also connected to the functional circuit 450 through a signal interface. It should be noted that there is more than one function circuit 450 inside the field programmable circuit, and only one function circuit is shown in the figure for illustration.

The hardware interface 410 is configured to receive configuration information of the upper computer; wherein the hardware interface 410 is a serial interface.

The configuration circuit 420 is configured to select a corresponding signal source from the field programmable gate circuit according to the configuration information and configure the sampling parameter; wherein the selected signal source is from the function circuit 450 inside the field programmable gate circuit.

The sampling circuit 430 is configured to sample the signal source according to the sampling parameters to obtain sampling data, and write the sampling data to the memory 440. Further, when the host computer reads the sample data in the memory 440, the sample data in the memory 440 is sent to the host computer through the hardware interface 410 to analyze the sampled data. The sampling circuit 430 samples the signal source according to the sampling parameters. For details, refer to the description in the foregoing embodiment, and details are not described herein again.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformation made by the specification and the drawings of the present invention may be directly or indirectly applied to other related technical fields. The same is included in the scope of patent protection of the present invention.

Claims (19)

1. An online test method for a field programmable gate circuit, comprising:

   Receiving configuration information sent by the host computer through a hardware interface on the field programmable gate circuit;

   Selecting a corresponding signal source from the field programmable gate circuit according to the configuration information and configuring sampling parameters;

   Sampling the signal source according to the sampling parameter to obtain sampling data;

   Writing the sampled data to a memory inside the field programmable gate circuit;

   And sending the sampled data in the memory to the upper computer through the hardware interface to analyze the sampled data.
2. The method of claim 1 wherein said step of sampling said signal source based on said sampling parameters to obtain sampled data comprises:

   Receiving, by the hardware interface, a sampling instruction of the upper computer;

   The signal source is sampled according to the sampling parameter in response to the sampling instruction to obtain the sampled data.
3. The method of claim 1 wherein the sampling parameter comprises at least one of a sampling frequency, an overall number of samples, a trigger signal, and a maximum number of pre-trigger samples.
4. The method of claim 3 wherein said step of sampling said signal source based on said sampling parameters to obtain sampled data comprises:

   Sampling the signal source according to the sampling frequency;
5. The method of claim 3 wherein said step of sampling said signal source based on said sampling parameters to obtain sampled data comprises:

   The signal source is triggered by the trigger signal during sampling.
6. The method of claim 5 wherein said step of writing said sampled data to a memory internal to the field programmable gate circuit comprises:

   The sample data written in the memory is divided into pre-trigger sample data and post-trigger sample data according to the trigger signal.
7. The method according to claim 6, wherein the distinguishing the sample data written in the memory into pre-trigger sample data and post-trigger sample data according to the trigger signal comprises:

   When the trigger signal is triggered to the signal source, if the number of the sampled data that has been written into the memory is less than the maximum number of pre-trigger samples, the recording of the written memory is recorded The number of sampled data, and then the number of records is used to distinguish between the pre-trigger sample data and the post-trigger sample data.
8. The method according to claim 6, wherein the distinguishing the sample data written in the memory into pre-trigger sample data and post-trigger sample data according to the trigger signal comprises:

   Before the trigger signal is triggered to the signal source, if the number of the sampled data that has been written into the memory is equal to the maximum number of samples before the trigger, the sampled data of the subsequent sample is used instead of the written The sampling data of the memory is triggered by the trigger signal to the signal source, and after the trigger signal is triggered by the signal source, the sampled data of the subsequent sampling is written into the memory remaining space.
9. The method according to claim 8, wherein said step of replacing said sampled data that has been written into said memory with said sampled data that has been subsequently sampled until said trigger signal triggers said signal source comprises:

   The memory is read and written in a shift storage manner such that the sample data in the memory is the latest sampled sample data of the maximum number of pre-trigger samples.
10. The method of claim 6 wherein said step of sampling said signal source based on said sampling parameters to obtain sampled data comprises:

    It is determined whether the quantity of the sampled data stored in the memory is equal to the total number of samples, and if it is equal to the total number of samples, sampling is stopped.
11. The method of claim 1 further comprising: before said step of writing said sampled data to a memory internal to the field programmable gate circuit, further comprising:

    The data in the memory is emptied to provide storage space for the sampled data.
12. A field programmable gate circuit, comprising:

    a hardware interface, a configuration circuit, a sampling circuit, and a memory, the hardware interface is connected to the upper computer, the hardware interface is further connected to the sampling circuit via the configuration circuit, and the sampling circuit is further connected to the memory, The memory is also interfaced with the hardware;

    The hardware interface receives configuration information of the upper computer; the configuration circuit selects a corresponding signal source from the field programmable gate circuit according to the configuration information, and configures sampling parameters; the sampling circuit is based on the sampling parameter The signal source is sampled to obtain sample data, and the sample data is written into the memory, and the sample data in the memory is sent to the host computer through the hardware interface to Data is analyzed.
13. The circuit of claim 12, wherein the sampling parameter comprises at least one of a sampling frequency, an overall number of samples, a trigger signal, and a maximum number of pre-trigger samples.
14. The circuit of claim 13 wherein said sampling circuit further samples said signal source based on said sampling frequency.
15. The circuit of claim 13 wherein said sampling circuit further triggers said signal source with said trigger signal during sampling.
16. The circuit according to claim 15, wherein said sampling circuit distinguishes said sample data written in said memory into pre-trigger sample data and post-trigger sample data in accordance with said trigger signal.
17. The circuit according to claim 16, wherein said distinguishing said sample data written in said memory into pre-trigger sample data and post-trigger sample data according to said trigger signal comprises:

    When the trigger signal is triggered to the signal source, if the number of the sampled data that has been written into the memory is less than the maximum number of pre-trigger samples, the recording of the written memory is recorded The number of sampled data, and then the number of records is used to distinguish between the pre-trigger sample data and the post-trigger sample data.
18. The circuit according to claim 16, wherein said distinguishing said sample data written in said memory into pre-trigger sample data and post-trigger sample data according to said trigger signal comprises:

    Before the trigger signal is triggered to the signal source, if the number of the sampled data that has been written into the memory is equal to the maximum number of samples before the trigger, the sampled data of the subsequent sample is used instead of the written The sampling data of the memory is triggered by the trigger signal to the signal source, and after the trigger signal is triggered by the signal source, the sampled data of the subsequent sampling is written into the memory remaining space.
19. The circuit according to claim 16, wherein said sampling module further determines whether the number of said sampled data stored in said memory is equal to said total number of samples, and if equal to said total number of samples, stopping sampling.