CN109298839A - Storage controller, storage device, system and method based on PIS - Google Patents
Storage controller, storage device, system and method based on PIS Download PDFInfo
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- CN109298839A CN109298839A CN201811261719.5A CN201811261719A CN109298839A CN 109298839 A CN109298839 A CN 109298839A CN 201811261719 A CN201811261719 A CN 201811261719A CN 109298839 A CN109298839 A CN 109298839A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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Abstract
The present invention relates to a kind of storage controllers based on PIS, storage device, system and method, including processor, for controlling the operation of storage device, and can send the first pre-processing instruction to data processing unit according to the operational order that host side is sent；Host-side interface connects the storage controller and the host side by the host-side interface；Flash controller carries out data transmission for the storage controller with flash array；Data processing unit, the first pre-processing instruction for being sent according to processor, pre-processes the data stored in flash array, and pretreated data are sent to host side by host-side interface；Above-mentioned host-side interface, flash controller, data processing unit are connect with processor, and the data processing unit is connect with the host-side interface and the flash controller respectively.Inventive memory device can storing data and data calculate, data bus resource occupancy is effectively reduced.
Description
Technical field
The present invention relates to a kind of storage controllers based on PIS, storage device, system and method.
Background technique
As shown in Figure 1, the CPU and memory of traditional Feng's Neumann computer are independently arranged, led to by bus
Letter.As shown in Fig. 2, traditional memory (such as SSD) includes controller and multiple flash, controller includes processor, flash
Instruction is transmitted to processor by interface by controller, internal bus, buffer and interface etc., host, and processor passes through internal total
Instruction is distributed to flash controller and buffer by line, and instruction is transmitted to flash by internal bus by flash controller,
Flash is received and is read and write data from flash particle after instruction, then by internal bus data is transmitted to buffer, by buffer
Host is transferred data to by interface, or interface is directly transferred data to by Flash controller, then passes through interface
Transfer data to host.Traditional memory further includes ECC, and the data for reading and writing flash controller carry out error correction, so
After be then forwarded to flash controller.
The CPU and memory of traditional computer are independent two disparate modules, and computer is responsible for calculating, and memory is responsible for
Storage, when carrying out big data analysis, mass data first will be again and again from the memory that memory is transmitted to CPU, then carries out
Data Analysis Services.The fast development of growth and artificial intelligence recently as big data business, data volume is increasing, needle
To the data-intensive applications of these data, the amount of analysis of CPU is also increasing, if according to traditional memory and CPU
The mode being independently arranged with memory, it is necessary to which the bus of more high bandwidth is just able to achieve increasing data volume from memory
Be transmitted to CPU, but the bus of traditional computer is STD bus, bandwidth be it is fixed, therefore, in Data-intensive computing
In artificial intelligence application, the bandwidth of standard does not catch up with data volume and amount of analysis, it is impossible to meet demand.In addition, due to data
Measure it is increasing, if data are transmitted by traditional STD bus, by the energy of drain bus significantly.Moreover, because data
It measures increasing, the big quantity space of CPU will be occupied, influence the speed of service of CPU.
Summary of the invention
Goal of the invention of the invention is to provide a kind of storage controller based on PIS, storage device, system and side
Method, storage device not only can store data, but also can carry out data calculating, and the resources occupation rate of data/address bus is effectively reduced, into
And improve the overall performance of computing system.
Based on the same inventive concept, there are four independent technical solutions for present invention tool:
1, a kind of storage controller based on PIS, comprising:
Processor, for controlling the operation of storage device, and can be according to the operational order that host side is sent to data processing
Unit sends the first pre-processing instruction；
Host-side interface connects the storage controller and the host side by the host-side interface；
Flash controller carries out data transmission for the storage controller with flash array；
Data processing unit, the first pre-processing instruction for being sent according to processor, to the number stored in flash array
According to being pre-processed, pretreated data are sent to host side by host-side interface；
Above-mentioned host-side interface, flash controller, data processing unit are connect with processor, the data processing unit
It is connect respectively with the host-side interface and the flash controller.
Further, the processor can be sent according to the operational order that the host side is sent to the flash controller
Storing data to be pre-treated is sent to by the second pre-processing instruction, the flash controller according to second pre-processing instruction
The data processing unit.
Further, the flash controller includes Data Management Unit, and the Data Management Unit will be for that will store number
According to being encoded and carry out transfer management；The flash controller is according to the second pre-processing instruction, by storage number to be pre-treated
According to after Data Management Unit coding and transfer management, it is sent to the data processing unit.
Further, the host-side interface, flash controller, data processing unit are connected by AXI bus and processor
It connects, the data processing unit is connected respectively at the host-side interface with the flash controller by AXI bus.
2, a kind of storage device, including the above-mentioned storage controller based on PIS.
3, a kind of storage system, host side connect one or more storage devices, described storage device packet by data/address bus
Include the above-mentioned storage controller based on PIS.
4, a kind of data preprocessing method of storage device, the operational order that storage device receiving host end is sent, judgement
Whether operational order includes pre-processing instruction, if it is, after storage device pre-processes storing data, then will pretreatment
Storing data afterwards is sent to host side；If it is not, then storing data is directly sent to host side by storage device.
The invention has the benefit that
Inventive memory device controller (DPU) not only can control the operation of storage device, but also can carry out to the data of storage
Calculation processing, that is, storage device not only can store data, but also can carry out data calculating, existing architectural framework be breached, in number
According to computing capability is introduced in storage processor, realize PIS (Processing in Storage).Processor combination number of the present invention
Firmware is handled according to processing unit or processor integrated data, so that completing in the nearest place of range data to storing data
Pretreatment, and treated data are sent into host, greatly reduce the load and energy consumption of the buses such as PCIe, while releasable
CPU frees the CPU of host side from heavy repeated labor, improves the CPU speed of service, improves big data processing
With analysis ability, and the resources occupation rate of I/O bus is reduced, greatlys improve the overall performance of computing system, can sufficiently meet
Magnanimity, heterogeneous, non-structured big data, cloud storage requirement.
As shown in fig. 6,2.1GB data input keyword " Chinese " search that will be downloaded from wiki (wikipedia)
In operation test, 9.2s is needed using the computer processing time of normal memory, and occupy CPU up to 55%；And pass through this hair
Bright DPU (Nidal ADA Technology), the processing time only needs 6s, and only takes up CPU 5% or so.As shown in fig. 7, passing through
Data volume after the computer disposal of DPU of the present invention is only that treated the 3% of data volume for common computer, is greatly reduced
It is transferred to the data volume of host, therefore, greatly reduces CPU occupation proportion, while greatly reducing bus load and power consumption.
Detailed description of the invention
Fig. 1 is the data communication schematic diagram of existing host side and memory；
Fig. 2 is the structure principle chart of existing memory；
Fig. 3 is the structure principle chart of inventive memory device；
Fig. 4 is the system architecture diagram of storage system of the present invention；
Fig. 5 is the data preprocessing method flow chart of inventive memory device；
Fig. 6 is the host side CPU accounting comparison signal of inventive memory device controller and existing storage controller
Figure；
Fig. 7 is the host side CPU processing data volume pair of inventive memory device controller and existing storage controller
Compare schematic diagram.
Specific embodiment
The present invention is described in detail for each embodiment shown in reference to the accompanying drawing, but it should be stated that, these
Embodiment is not limitation of the present invention, those of ordinary skill in the art according to these embodiments made by function, method,
Or equivalent transformation or substitution in structure, all belong to the scope of protection of the present invention within.
Embodiment one:
Storage controller based on PIS:
As shown in figure 3, the storage controller (DPU) based on PIS includes:
Processor, for controlling the operation of storage device, and can be according to the operational order that host side is sent to data processing
Unit sends the first pre-processing instruction；
Host-side interface connects storage controller and host side by host-side interface；The interface of DPU uses PCIe
Interface or NVMe interface etc..
Flash controller (falsh controller) carries out data biography for storage controller and flash array (flash)
It is defeated；
Data processing unit (ADA), the first pre-processing instruction for being sent according to processor, to being stored in flash array
Data pre-processed, pretreated data are sent to host side by host-side interface；
Above-mentioned host-side interface, flash controller, data processing unit are connect with processor, data processing unit difference
It is connect with host-side interface and flash controller.
When it is implemented, processor is connect by internal bus with flash controller, ADA and host-side interface, flash
Controller also passes through internal bus and connect with flash, and ADA also passes through internal bus and connect with interface.The internal bus of DPU uses
AXI (Advanced eXtensible Interface) bus, has the characteristics that high-performance, high bandwidth, low latency, can meet
Performance needed for DPU internal transmission.
Processor can be central processing unit (Central Processing Unit, CPU), network processing unit
(network processor, NP), general processor, digital signal processor (Digital Signal Processor,
DSP), specific integrated circuit (Application-Specific Integrated Circuit, ASIC), field programmable gate
Array (Field Programmable Gate Array, FPGA) or other programmable logic device, transistor logic device
Part, hardware component or any combination thereof.In the case where processor is a CPU, which can be monokaryon CPU, can also be with
It is multi-core CPU.
Data processing unit includes text search unit and/or Data Format Transform unit, and text search unit is for real
When full-text search is carried out to data stream, Data Format Transform unit is for be converted into storing data can computational format.Text is searched
Rope (GREP), Data Format Transform (SCANF), classification (Sorting), compression, decompression etc..GREP and SCANF is big data
Using widest two kinds of Data-intensive computings in the middle.Since storage calculates the scalability of PIS framework in fusion chip, after
It is continuous to realize computing function in other disks according to different industries to the specific requirements of calculating.Data Format Transform (SCANF)
Be one by storing data by certain readable format (such as ASCII, Unicode) be converted to can computational format (such as binary system) mistake
Journey.Steps are as follows for traditional data calculating: (1) initial data being read into host memory from storage device；(2) host CPU
Initial data in memory is formatted, and is saved in another position of memory；(3) after application program is to conversion
Data are operated.Clearly as CPU and caching participate in a large amount of simple and duplicate data exchanges and calculating, it is above-mentioned
The efficiency of data usage mode is very low, and the load of rambus and I/O bus is very heavy.Many numerical value are calculated and are appointed
For business, the work of above-mentioned Data Format Transform is necessary and occupies for up to 60% execution time.
Flash controller includes Data Management Unit (ADM), and Data Management Unit is for being encoded simultaneously storing data
Carry out transfer management；Flash controller is according to third pre-processing instruction, by storing data to be pre-treated through Data Management Unit
After coding and transfer management, it is sent to data processing unit.
When the data that host needs to transfer flash are analyzed, processor is sent an instruction to by host-side interface,
After processor receives operational order, judge in received operational order whether to include pre-processing instruction, such as include, processor is by the
One pre-processing instruction is sent to ADA and the second pre-processing instruction is sent to flash controller, and flash controller receives second
Data are read and write from flash particle after pre-processing instruction, then required data are pre-processed by ADA, after pretreatment, will be handled
Data afterwards are sent to interface by internal bus, send the data to host by host interface, so that host is further located
Reason.When flash controller includes Data Management Unit (ADM), from flash after flash controller the second pre-processing instruction of reception
Particle reads and writes data, then by ADM data are encoded and carried out with the transfer management of data, then again by ADA to required
Data are pre-processed, and after pretreatment, treated data by internal bus are sent to interface, are sent out data by interface
Host is given, so that host is further processed.
Further, operational order has identification code, and identification code includes pre-processing instruction, passes through identification code and storage device
In pre-stored identification code be compared, compare successfully, then start pretreatment, compare failure, then do not start pretreatment, directly
Send the data to host.
Embodiment two:
Storage controller based on PIS:
Embodiment two and the difference of embodiment one essentially consist in, in embodiment two, ADA and processor as integral structure,
That is ADA is poured into a software form in the firmware of processor, is further reduced the setting of DPU internal bus pin.That is, processor packet
Data processing firmware is included, data processing firmware is for pre-processing storing data.Remaining working principle of embodiment two is same
Embodiment one.
Embodiment three:
Storage device:
Described storage device includes the storage controller (DPU) based on PIS of embodiment one or embodiment two.
Example IV:
Storage system:
As shown in figure 4, host side connects multiple storage devices by data/address bus, described storage device include embodiment one or
The storage controller (DPU) based on PIS of embodiment two.Storage device (memory) is set on the slot of host, is led to
It crosses and multiple storage devices is set, mass data can be handled.
Embodiment five:
The data preprocessing method of storage device:
As shown in figure 5, whether the operational order (data command) that storage device receiving host end is sent, judge operational order
Comprising pre-processing instruction, if it is, after storage device pre-processes storing data, then by pretreated storing data
It is sent to host side；If it is not, then storing data is directly sent to host side by storage device.
Pretreatment include in real time to data stream carry out full-text search, by storing data be converted into can computational format, classification
(Sorting), compress, decompress etc..
Judge that operational order whether include the method for pre-processing instruction includes: that host sends and refers to the operation of identification code
It enabling, identification code includes pre-processing instruction, it is compared by identification code with pre-stored identification code in storage storage device, than
To success, then start pretreatment, compares failure, then do not start pretreatment, directly send the data to host.
It should be appreciated that device and method disclosed in the above embodiment provided herein, can also pass through it
Its mode realizes that the apparatus embodiments described above are merely exemplary.The foregoing is merely specific realities of the invention
Mode is applied, but scope of protection of the present invention is not limited thereto, anyone skilled in the art takes off in the present invention
It in the technical scope of dew, can easily think of the change or the replacement, should be covered by the protection scope of the present invention.Therefore, this hair
Bright protection scope should be subject to the protection scope in claims.
Claims (7)
1. a kind of storage controller based on PIS characterized by comprising
Processor, for controlling the operation of storage device, and can be according to the operational order that host side is sent to data processing unit
Send the first pre-processing instruction；
Host-side interface connects the storage controller and the host side by the host-side interface；
Flash controller carries out data transmission for the storage controller with flash array；
Data processing unit, the first pre-processing instruction for being sent according to processor, to the data stored in flash array into
Pretreated data are sent to host side by host-side interface by row pretreatment；
Above-mentioned host-side interface, flash controller, data processing unit are connect with processor, the data processing unit difference
It is connect with the host-side interface and the flash controller.
2. the storage controller according to claim 1 based on PIS, it is characterised in that: the processor can basis
The operational order that the host side is sent sends the second pre-processing instruction to the flash controller, the flash controller according to
Storing data to be pre-treated is sent to the data processing unit by second pre-processing instruction.
3. the storage controller according to claim 2 based on PIS, it is characterised in that: the flash controller packet
Data Management Unit is included, the Data Management Unit by storing data for being encoded and carrying out transfer management；The flash memory
Controller is according to the second pre-processing instruction, by storing data to be pre-treated after Data Management Unit coding and transfer management,
It is sent to the data processing unit.
4. the storage controller according to claim 1 based on PIS, it is characterised in that: the host-side interface, sudden strain of a muscle
Memory controller, data processing unit are connect by AXI bus with processor, and the data processing unit is distinguished by AXI bus
It is connected in the host-side interface with the flash controller.
5. a kind of storage device, it is characterised in that: including described in Claims 1-4 any one based on the storage device of PIS
Controller.
6. a kind of storage system, it is characterised in that: host side connects one or more storage devices, the storage by data/address bus
Device includes the storage controller described in Claims 1-4 any one based on PIS.
7. a kind of data preprocessing method of storage device, it is characterised in that: the operation that storage device receiving host end is sent refers to
It enables, judges whether operational order includes pre-processing instruction, if it is, after storage device pre-processes storing data, then
Pretreated storing data is sent to host side；If it is not, then storing data is directly sent to host side by storage device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811261719.5A CN109298839A (en) | 2018-10-26 | 2018-10-26 | Storage controller, storage device, system and method based on PIS |
| PCT/CN2019/095197 WO2020082813A1 (en) | 2018-10-26 | 2019-07-09 | Pis-based memory device controller, memory device, system, and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811261719.5A CN109298839A (en) | 2018-10-26 | 2018-10-26 | Storage controller, storage device, system and method based on PIS |
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| CN109298839A true CN109298839A (en) | 2019-02-01 |
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| CN201811261719.5A Pending CN109298839A (en) | 2018-10-26 | 2018-10-26 | Storage controller, storage device, system and method based on PIS |
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| WO (1) | WO2020082813A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020082813A1 (en) * | 2018-10-26 | 2020-04-30 | 深圳大普微电子科技有限公司 | Pis-based memory device controller, memory device, system, and method |
| CN111949211A (en) * | 2020-07-10 | 2020-11-17 | 深圳宏芯宇电子股份有限公司 | Storage device and storage control method |
| CN112181293A (en) * | 2020-09-17 | 2021-01-05 | 深圳大普微电子科技有限公司 | Solid state disk controller, solid state disk, storage system and data processing method |
| WO2023060891A1 (en) * | 2021-10-14 | 2023-04-20 | 华为技术有限公司 | Data processing method, apparatus and system, and device, storage medium and program product |
| WO2023072048A1 (en) * | 2021-10-27 | 2023-05-04 | 华为技术有限公司 | Network storage method, storage system, data processing unit, and computer system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760045B (en) * | 2011-04-29 | 2015-07-08 | 无锡江南计算技术研究所 | Intelligent storage device and data processing method thereof |
| JP5853899B2 (en) * | 2012-03-23 | 2016-02-09 | ソニー株式会社 | Storage control device, storage device, information processing system, and processing method therefor |
| CN104834484B (en) * | 2015-05-11 | 2018-10-23 | 上海新储集成电路有限公司 | Data processing system based on embedded programmable logic array and processing method |
| CN107870878A (en) * | 2017-10-31 | 2018-04-03 | 深圳清华大学研究院 | Storage system, terminal and computer installation |
| CN209044575U (en) * | 2018-10-26 | 2019-06-28 | 深圳大普微电子科技有限公司 | Storage controller, storage device and system based on PIS |
| CN109298839A (en) * | 2018-10-26 | 2019-02-01 | 深圳大普微电子科技有限公司 | Storage controller, storage device, system and method based on PIS |
-
2018
- 2018-10-26 CN CN201811261719.5A patent/CN109298839A/en active Pending
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2019
- 2019-07-09 WO PCT/CN2019/095197 patent/WO2020082813A1/en active Application Filing
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020082813A1 (en) * | 2018-10-26 | 2020-04-30 | 深圳大普微电子科技有限公司 | Pis-based memory device controller, memory device, system, and method |
| CN111949211A (en) * | 2020-07-10 | 2020-11-17 | 深圳宏芯宇电子股份有限公司 | Storage device and storage control method |
| US11609713B2 (en) | 2020-07-10 | 2023-03-21 | Hosin Global Electronics Co., Ltd | Storage device and storage control method |
| CN112181293A (en) * | 2020-09-17 | 2021-01-05 | 深圳大普微电子科技有限公司 | Solid state disk controller, solid state disk, storage system and data processing method |
| CN112181293B (en) * | 2020-09-17 | 2023-08-22 | 深圳大普微电子科技有限公司 | Solid state disk controller, solid state disk, storage system and data processing method |
| WO2023060891A1 (en) * | 2021-10-14 | 2023-04-20 | 华为技术有限公司 | Data processing method, apparatus and system, and device, storage medium and program product |
| WO2023072048A1 (en) * | 2021-10-27 | 2023-05-04 | 华为技术有限公司 | Network storage method, storage system, data processing unit, and computer system |
Also Published As
| Publication number | Publication date |
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| WO2020082813A1 (en) | 2020-04-30 |
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