CN105320630A - Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache - Google Patents

Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache Download PDF

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Publication number
CN105320630A
CN105320630A CN201410375271.5A CN201410375271A CN105320630A CN 105320630 A CN105320630 A CN 105320630A CN 201410375271 A CN201410375271 A CN 201410375271A CN 105320630 A CN105320630 A CN 105320630A
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gpu
processing unit
cpu
system architecture
intelligent flash
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张军
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Abstract

The invention discloses a heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on an intelligent flash cache. The architecture is characterized in that the architecture is provided with a parallel CPU and a parallel GPU which are independent and are provided with respective storage subsystems and storage devices capable of accessing others; the GPU is connected to a chipset through an I/O (Input/Output) bus, and then is connected with the CPU through an I/O bridge; the CPU consists of an ALU (Arithmetic Logical Unit), a register file, the intelligent flash cache and a bus interface.

Description

A kind of multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory
Technical field
The present invention relates to a kind of multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory
Background technology
CPU and central processing unit are one piece of ultra-large integrated circuit, are arithmetic core and the control core of a computing machine.Mainly comprise arithmetical unit (ALU) and the large parts of controller (CU) two.In addition, the bus of the data also comprising several registers and cache memory and realize contacting between them, control and state.It and internal storage and input-output apparatus are collectively referred to as the large core component of robot calculator three.GPU and graphic process unit are a kind of specially at the microprocessor of personal computer, workstation, game machine and some mobile device epigraph operation.
Heterogeneous Computing mainly refers to the account form of the computing unit composition system using dissimilar instruction set and architectural framework.Common computing unit classification comprises the processors such as CPU, GPU.Heterogeneous Computing obtains more concerns in recent years, mainly because the traditional approach being improved computing power by lifting cpu clock frequency and number of cores encounters heat radiation and energy consumption bottleneck.And although the dedicated computing unit frequency of operation such as GPU are lower, have more interior check figure and computation capability, ratio and the performance/power dissipation ratio of overall performance/chip area are all very high, are far from being fully used.
The design of CPU allows it compare and is good at process irregular data structure and uncertain access mode, and recursive algorithm, the intensive code of branch and single-threading program.This kind of program task has the steps such as complicated instruction scheduling, circulation, branch, Logic judgment and execution.And GPU is good at processing rule data structure and measurable access mode.The strong point of both set, reaches the optimization of overall performance by Heterogeneous Computing.
Intelligent flash buffer memory is a read-only buffer memory.When unmodified data block because the pressure in space is eliminated out buffer area high-speed cache, these data blocks are just moved in flash cache; If need again these data, database will be retracted these data blocks again from flash cache.Flash cache utilizes the I/O speed of flash memory device, more much higher than the memory property based on disk; There is enough CPU, can flash cache be used.
The invention provides a kind of multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory.The feature of framework, for having independently parallel C PU and parallel GPU, has respective storage subsystem, all may have access to the storer of the other side; GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge; CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.
Summary of the invention
The object of the present invention is to provide a kind of multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory.The present invention includes following characteristics:
Invention technical scheme
1. based on a multinuclear isomery CPU-GPU system architecture for intelligent flash buffer memory, the feature of framework:
1) there is independently parallel C PU and parallel GPU, have respective storage subsystem, all may have access to the storer of the other side;
2) GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge;
3) CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.
Accompanying drawing explanation
Accompanying drawing 1 is the multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory.
Embodiment
1. based on a multinuclear isomery CPU-GPU system architecture for intelligent flash buffer memory, the feature of framework:
1) there is independently parallel C PU and parallel GPU, have respective storage subsystem, all may have access to the storer of the other side;
2) GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge;
3) CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.

Claims (1)

1. based on a multinuclear isomery CPU-GPU system architecture for intelligent flash buffer memory, the feature of framework:
1) there is independently parallel C PU and parallel GPU, have respective storage subsystem, all may have access to the storer of the other side;
2) GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge;
3) CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.
CN201410375271.5A 2014-08-01 2014-08-01 Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache Pending CN105320630A (en)

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CN105320630A true CN105320630A (en) 2016-02-10

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106502956A (en) * 2016-10-28 2017-03-15 张军 A kind of operating system prototype of multinuclear isomery CPU GPU system frameworks
CN106708777A (en) * 2017-01-23 2017-05-24 张军 Multi-core heterogeneous CPU - CPU - FPGA architecture
CN106843045A (en) * 2017-01-23 2017-06-13 张军 A kind of embedded OS prototype based on multinuclear isomery CPU GPU FPGA system frameworks
US10614541B2 (en) 2017-06-29 2020-04-07 Nvidia Corporation Hybrid, scalable CPU/GPU rigid body pipeline

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105892931A (en) * 2014-05-16 2016-08-24 上海京知信息科技有限公司 heterogeneous CPU-GPU system configuration based on intelligent flash cache

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105892931A (en) * 2014-05-16 2016-08-24 上海京知信息科技有限公司 heterogeneous CPU-GPU system configuration based on intelligent flash cache

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106502956A (en) * 2016-10-28 2017-03-15 张军 A kind of operating system prototype of multinuclear isomery CPU GPU system frameworks
CN106708777A (en) * 2017-01-23 2017-05-24 张军 Multi-core heterogeneous CPU - CPU - FPGA architecture
CN106843045A (en) * 2017-01-23 2017-06-13 张军 A kind of embedded OS prototype based on multinuclear isomery CPU GPU FPGA system frameworks
US10614541B2 (en) 2017-06-29 2020-04-07 Nvidia Corporation Hybrid, scalable CPU/GPU rigid body pipeline

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Application publication date: 20160210