CN105320630A - Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache - Google Patents
Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache Download PDFInfo
- Publication number
- CN105320630A CN105320630A CN201410375271.5A CN201410375271A CN105320630A CN 105320630 A CN105320630 A CN 105320630A CN 201410375271 A CN201410375271 A CN 201410375271A CN 105320630 A CN105320630 A CN 105320630A
- Authority
- CN
- China
- Prior art keywords
- gpu
- processing unit
- cpu
- system architecture
- intelligent flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on an intelligent flash cache. The architecture is characterized in that the architecture is provided with a parallel CPU and a parallel GPU which are independent and are provided with respective storage subsystems and storage devices capable of accessing others; the GPU is connected to a chipset through an I/O (Input/Output) bus, and then is connected with the CPU through an I/O bridge; the CPU consists of an ALU (Arithmetic Logical Unit), a register file, the intelligent flash cache and a bus interface.
Description
Technical field
The present invention relates to a kind of multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory
Background technology
CPU and central processing unit are one piece of ultra-large integrated circuit, are arithmetic core and the control core of a computing machine.Mainly comprise arithmetical unit (ALU) and the large parts of controller (CU) two.In addition, the bus of the data also comprising several registers and cache memory and realize contacting between them, control and state.It and internal storage and input-output apparatus are collectively referred to as the large core component of robot calculator three.GPU and graphic process unit are a kind of specially at the microprocessor of personal computer, workstation, game machine and some mobile device epigraph operation.
Heterogeneous Computing mainly refers to the account form of the computing unit composition system using dissimilar instruction set and architectural framework.Common computing unit classification comprises the processors such as CPU, GPU.Heterogeneous Computing obtains more concerns in recent years, mainly because the traditional approach being improved computing power by lifting cpu clock frequency and number of cores encounters heat radiation and energy consumption bottleneck.And although the dedicated computing unit frequency of operation such as GPU are lower, have more interior check figure and computation capability, ratio and the performance/power dissipation ratio of overall performance/chip area are all very high, are far from being fully used.
The design of CPU allows it compare and is good at process irregular data structure and uncertain access mode, and recursive algorithm, the intensive code of branch and single-threading program.This kind of program task has the steps such as complicated instruction scheduling, circulation, branch, Logic judgment and execution.And GPU is good at processing rule data structure and measurable access mode.The strong point of both set, reaches the optimization of overall performance by Heterogeneous Computing.
Intelligent flash buffer memory is a read-only buffer memory.When unmodified data block because the pressure in space is eliminated out buffer area high-speed cache, these data blocks are just moved in flash cache; If need again these data, database will be retracted these data blocks again from flash cache.Flash cache utilizes the I/O speed of flash memory device, more much higher than the memory property based on disk; There is enough CPU, can flash cache be used.
The invention provides a kind of multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory.The feature of framework, for having independently parallel C PU and parallel GPU, has respective storage subsystem, all may have access to the storer of the other side; GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge; CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.
Summary of the invention
The object of the present invention is to provide a kind of multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory.The present invention includes following characteristics:
Invention technical scheme
1. based on a multinuclear isomery CPU-GPU system architecture for intelligent flash buffer memory, the feature of framework:
1) there is independently parallel C PU and parallel GPU, have respective storage subsystem, all may have access to the storer of the other side;
2) GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge;
3) CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.
Accompanying drawing explanation
Accompanying drawing 1 is the multinuclear isomery CPU-GPU system architecture based on intelligent flash buffer memory.
Embodiment
1. based on a multinuclear isomery CPU-GPU system architecture for intelligent flash buffer memory, the feature of framework:
1) there is independently parallel C PU and parallel GPU, have respective storage subsystem, all may have access to the storer of the other side;
2) GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge;
3) CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.
Claims (1)
1. based on a multinuclear isomery CPU-GPU system architecture for intelligent flash buffer memory, the feature of framework:
1) there is independently parallel C PU and parallel GPU, have respective storage subsystem, all may have access to the storer of the other side;
2) GPU is connected to chipset by I/O bus, and then is connected with CPU by I/O bridge;
3) CPU is made up of ALU, register file and intelligent flash buffer memory and bus interface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410375271.5A CN105320630A (en) | 2014-08-01 | 2014-08-01 | Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410375271.5A CN105320630A (en) | 2014-08-01 | 2014-08-01 | Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105320630A true CN105320630A (en) | 2016-02-10 |
Family
ID=55248038
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410375271.5A Pending CN105320630A (en) | 2014-08-01 | 2014-08-01 | Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105320630A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106502956A (en) * | 2016-10-28 | 2017-03-15 | 张军 | A kind of operating system prototype of multinuclear isomery CPU GPU system frameworks |
CN106708777A (en) * | 2017-01-23 | 2017-05-24 | 张军 | Multi-core heterogeneous CPU - CPU - FPGA architecture |
CN106843045A (en) * | 2017-01-23 | 2017-06-13 | 张军 | A kind of embedded OS prototype based on multinuclear isomery CPU GPU FPGA system frameworks |
US10614541B2 (en) | 2017-06-29 | 2020-04-07 | Nvidia Corporation | Hybrid, scalable CPU/GPU rigid body pipeline |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105892931A (en) * | 2014-05-16 | 2016-08-24 | 上海京知信息科技有限公司 | heterogeneous CPU-GPU system configuration based on intelligent flash cache |
-
2014
- 2014-08-01 CN CN201410375271.5A patent/CN105320630A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105892931A (en) * | 2014-05-16 | 2016-08-24 | 上海京知信息科技有限公司 | heterogeneous CPU-GPU system configuration based on intelligent flash cache |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106502956A (en) * | 2016-10-28 | 2017-03-15 | 张军 | A kind of operating system prototype of multinuclear isomery CPU GPU system frameworks |
CN106708777A (en) * | 2017-01-23 | 2017-05-24 | 张军 | Multi-core heterogeneous CPU - CPU - FPGA architecture |
CN106843045A (en) * | 2017-01-23 | 2017-06-13 | 张军 | A kind of embedded OS prototype based on multinuclear isomery CPU GPU FPGA system frameworks |
US10614541B2 (en) | 2017-06-29 | 2020-04-07 | Nvidia Corporation | Hybrid, scalable CPU/GPU rigid body pipeline |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Jouppi et al. | Motivation for and evaluation of the first tensor processing unit | |
US11562213B2 (en) | Methods and arrangements to manage memory in cascaded neural networks | |
TWI470418B (en) | An asymmetric performance multicore architecture with same instruction set architecture (isa) | |
CN103218338B (en) | The real-time many DSP debug system of a kind of signal processor system | |
CN101526934A (en) | Construction method of GPU and CPU combined processor | |
CN205959137U (en) | Big data service ware mainboard based on explain 1610 majestic treaters | |
CN105320630A (en) | Heterogeneous multi-core CPU-GPU (Central Processing Unit-Graphics Processing Unit) system architecture based on intelligent flash cache | |
Martin | Multicore processors: challenges, opportunities, emerging trends | |
US20140025930A1 (en) | Multi-core processor sharing li cache and method of operating same | |
CN111209247A (en) | Integrated circuit computing device and computing processing system | |
Pugsley et al. | Fixed-function hardware sorting accelerators for near data mapreduce execution | |
Ouyang et al. | Active SSD design for energy-efficiency improvement of web-scale data analysis | |
Greengard | GPUs reshape computing | |
CN105892931A (en) | heterogeneous CPU-GPU system configuration based on intelligent flash cache | |
Kim et al. | The implementation of a power efficient bcnn-based object detection acceleration on a xilinx FPGA-SOC | |
Power et al. | Implications of emerging 3D GPU architecture on the scan primitive | |
US20140189667A1 (en) | Speculative memory disambiguation analysis and optimization with hardware support | |
US20160055005A1 (en) | System and Method for Page-Conscious GPU Instruction | |
Waidyasooriya et al. | FPGA-accelerator for DNA sequence alignment based on an efficient data-dependent memory access scheme | |
CN104636089A (en) | Method for accelerating performance of servers of domestic central processing units on basis of NVME (nonvolatile memory express) technology | |
Waidyasooriya et al. | Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment | |
Rjabov et al. | Interactions of Zynq-7000 devices with general purpose computers through PCI-express: A case study | |
CN105988945A (en) | Heterogeneous multiprocessor system and driving control method thereof | |
CN209044575U (en) | Storage controller, storage device and system based on PIS | |
Lim et al. | Triple Engine Processor (TEP) A Heterogeneous Near-Memory Processor for Diverse Kernel Operations |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160210 |