CN105988945A - Heterogeneous multiprocessor system and driving control method thereof - Google Patents
Heterogeneous multiprocessor system and driving control method thereof Download PDFInfo
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- CN105988945A CN105988945A CN201510062427.9A CN201510062427A CN105988945A CN 105988945 A CN105988945 A CN 105988945A CN 201510062427 A CN201510062427 A CN 201510062427A CN 105988945 A CN105988945 A CN 105988945A
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Abstract
The invention discloses a heterogeneous multiprocessor system and a driving control method thereof. The heterogeneous multiprocessor system comprises the following steps that in system initialization, a first processor has a control right to external equipment, an interrupt request of the external equipment can be only accepted by the first processer at the moment, and a second processor shields the interrupt request of the external equipment; the firs processor operates a driving program of the external equipment and detects the state of the external equipment; when the external equipment is in a first state, the first processor processes a control instruction and data transmission of the external equipment, and writes the state and the control information of the external equipment; when detecting that the external equipment is turned into a second state from the first state, the first processor transfers the control right of the external equipment to the second processor, and the second processor operates the driving program of the external equipment, and reads the state and the control information of the external equipment from a memory to process. Due to adoption of an interruption technique, dynamic adjustment of equipment driving can be achieved.
Description
Technical field
The present invention relates to heterogeneous multi-processor technology, particularly relate to a kind of heterogeneous multiprocessor system and
Drive control method.
Background technology
Along with the development of integrated circuit technique, the increasing function that processes is desirably integrated into a system
In integrated chip (System on a Chip is called for short SoC).A lot of electronic equipments have only to a SoC again
It is aided with some resistance and electric capacity.Processor in SoC, symmetric multiprocessor the most common.Isomery mould
The big.little processor architecture such as ARM of formula also gets more and more.At control field, such as Freescale
Vybrid series processors such as VF6xx, use two kernels, a Cortex A5, another
Cortex M4。
The heterogeneous schemas multiprocessor of prior art there is problems of, although each processor can be controlled
System drives external equipment, but they may not access external equipment simultaneously.To same external equipment,
If multiple isomery kernels to access this equipment, it may be necessary to different drivers, because each kernel
The operating system (OS) of upper operation may be all different.
Summary of the invention
It is an object of the invention to solve heterogeneous schemas multiprocessor in prior art and controlling driving outside
The problems referred to above existed during equipment, it is provided that a kind of heterogeneous multiprocessor system and driving control method thereof.
To achieve these goals, on the one hand, the invention provides a kind of heterogeneous multi-processor and drive control
Method, the method is applied to be made up of first processor, the second processor, memorizer and external equipment
In heterogeneous multiprocessor system, the method comprises the following steps:
When system initialization, first processor has control to external equipment, at the most only first
Reason device accepts the interrupt requests of external equipment, and the second processor shields the interrupt requests of external equipment；
First processor runs the driver of external equipment, the state of detection external equipment；
When external equipment is in the first state, first processor is to the control command of external equipment and data
Transmission processes, by the state of external equipment and control information write-in memory；When external equipment is by
When one state is changed into the second state, the control that external equipment is had by first processor hands to second
Processor, the second processor runs the driver of external equipment, reads external equipment from memorizer
State and control information process.
Preferably, when the external equipment of detection is changed into the first state by the second state, the second processor
The control having external equipment gives back first processor, and first processor runs driving of external equipment
Dynamic program, the state and the control information that read external equipment from memorizer process.
Preferably, first processor and the second processor control external equipment by dma controller and deposit
Carry out data transmission between reservoir.
Preferably, first processor accepts the interrupt requests of external equipment, and the second processor shielding is outside
The interrupt requests step of equipment is to be realized by DMA interrupt control unit.
On the other hand, the invention provides a kind of heterogeneous multiprocessor system, this system includes: first
Processor, the second processor, memorizer and external equipment；First processor and the second processor connect
Memorizer, accesses external equipment by device bus；The interrupt signal of external equipment is coupled with first
Interrupt control unit and the second interrupt control unit, the first interrupt control unit is connected with first processor, and second
Interrupt control unit and the second processor connect；
When system initialization, first processor has control to external equipment, at the most only first
Reason device accepts the interrupt requests of external equipment, and the second processor shields the interrupt requests of external equipment；The
One processor runs the driver of external equipment, the state of detection external equipment；When external equipment is in
During the first state, control command and the data transmission of external equipment are processed by first processor, will outward
The state of portion's equipment and control information write-in memory；When external equipment is changed into the second shape by the first state
During state, the control that external equipment is had by first processor hands to the second processor, the second processor
Running the driver of external equipment, the state and the control information that read external equipment from memorizer are carried out
Process.
Preferably, heterogeneous multiprocessor system system also includes dma controller, first processor and
Two processors control to carry out data transmission between external equipment and memorizer by dma controller.
Preferably, first processor and the second processor specifically for, from memorizer, read external equipment
State and control information external equipment is initialized, and enter driven flow process.
The present invention passes through interrupt techniques and suitable control, it is achieved that at heterogeneous multiprocessor system everywhere
The reason enterprising Mobile state of device adjusts device drives, by control right transfer to another kernel from a kernel.
On the one hand this can adjust the load on each kernel, on the other hand power consumption can also be carried out finer control
System.Such as, when certain peripheral hardware does not work, can only operation monitoring journey on the kernel that power consumption is smaller
Sequence；After detecting that this peripheral hardware needs to enter duty, it is transferred on the kernel that computing capability is higher.
Accompanying drawing explanation
A kind of heterogeneous multiprocessor system structure chart that Fig. 1 provides for the embodiment of the present invention；
A kind of heterogeneous multi-processor that Fig. 2 provides for the embodiment of the present invention drives control method flow chart.
Detailed description of the invention
Below by drawings and Examples, technical scheme is described in further detail.
A kind of heterogeneous multiprocessor system structure chart that Fig. 1 provides for the embodiment of the present invention.As it is shown in figure 1,
This system includes: in first processor the 11, second processor the 12, first interrupt control unit 21, second
Disconnected controller 22, memorizer 30, dma controller 40 and external equipment 50.
Wherein, first processor 11 and the second processor 12 connect, at first processor 11 and second
Reason device 12 connects memorizer 30 and dma controller 40 respectively, and accesses outside setting by device bus
Standby 50.First processor 11 and the second processor 12 control external equipment by dma controller 40
Carry out data transmission between 50 and memorizer 30.
The interrupt signal of external equipment 50 is coupled with the first interrupt control unit 21 and the second interrupt control unit
22, the first interrupt control unit 21 is connected with first processor 11, the second interrupt control unit 22 and second
Processor 12 connects.Each interruption is arranged by the first interrupt control unit 21 or the second interrupt control unit 22
There is an interrupt mask bit, be used for enabling/shielding the interruption of correspondence.Interrupt mask bit can be in isomery multiprocessing
It is configured during device system reset.
In the heterogeneous multiprocessor system that the embodiment of the present invention provides, at first processor 11 and second
Reason device 12 runs different operating system.Such as, first processor 11 runs a small operation system
System, controls in real time, and the second processor 12 runs a large operation system, to provide abundant
Application.
Correspondingly, the application pin provides the control driving method of a kind of heterogeneous multiprocessor system, such as figure
Shown in 2.
A kind of heterogeneous multi-processor that Fig. 2 provides for the embodiment of the present invention drives control method flow chart.Should
Method comprises the following steps: heterogeneous multiprocessor system, when carrying out system initialization, is first processed by first
Device 11 has control to external equipment 50, and the most only first processor 11 can accept outside and sets
The interrupt requests of standby 50, and the second processor 12 needs to shield the interrupt requests of external equipment 50；?
Run the scaled-down version driver of an external equipment 50 on first processor 11, be used for detecting outside and set
The state of standby 50.
When the external equipment 50 of detection is in the first state, by first processor 11 to external equipment 50
Control command and data transmission process, and by the state of external equipment 50 and control information write
Memorizer 30；When the external equipment 50 of detection is changed into the second state by the first state, first processes
The control that external equipment 50 has is handed to the second processor 12 by device 11, and the second processor 12 is transported
The driver of row external equipment 50, and from shared memorizer 30, read the shape of external equipment 50
State and control information initialize, and enter driven flow process.
It should be noted that the heterogeneous multiprocessor system that provides of the embodiment of the present invention is to carry out system initial
During change, it is also possible to the first control that external equipment 50 had by the second processor 12, and first processor
11 interrupt requests needing to shield external equipment 50.This technical scheme also belongs to present invention protection
Scope.
In an application scenarios: the most on the mobile apparatus, it is often necessary to power consumption control.External equipment
Not it is always at work or high load condition.When heterogeneous multiprocessor system detects at external equipment
When idle condition (the such as first state), by the processor core (such as first processor) of low energy consumption
Process；When detecting that external equipment is in high load condition (the such as second state), then by Gao Gong
The processor core (the such as second processor) of consumption processes.
The embodiment of the present invention passes through interrupt techniques and suitable control, it is achieved that at heterogeneous multiprocessor system
The enterprising Mobile state of each processor adjust device drives, by control right transfer to another from a kernel
Kernel.On the one hand this can adjust the load on each kernel, on the other hand can also carry out more smart to power consumption
Thin control.Such as, when certain peripheral hardware does not work, can only run on the kernel that power consumption is smaller
Monitoring programme；After detecting that this peripheral hardware needs to enter duty, it is transferred to computing capability higher
On kernel.
It is clear that on the premise of without departing from true spirit and scope of the present invention, described here
Invention can have many changes.Therefore, all changes that it will be apparent to those skilled in the art that,
It is intended to be included within the scope of the claims contained.Scope of the present invention only by
Described claims are defined.
Claims (8)
1. heterogeneous multi-processor drive a control method, be applied to by first processor (11), second
In the heterogeneous multiprocessor system that processor (12), memorizer (30) and external equipment (50) are constituted,
It is characterized in that:
When system initialization, described first processor (11) has control to described external equipment (50)
System power, the most described first processor (11) accepts the interrupt requests of described external equipment (50),
And described second processor (12) shields the interrupt requests of described external equipment (50)；
Described first processor (11) runs the driver of described external equipment (50), and detection is described
The state of external equipment (50)；
When described external equipment (50) is in the first state, described first processor (11) is to described
The control command of external equipment (50) and data transmission process, by described external equipment (50)
State and control information write-in memory (30)；When the described external equipment (50) of detection is by the first shape
When state is changed into the second state, described external equipment (50) is had by described first processor (11)
Control hands to described second processor (12), and described second processor (12) runs described outside
The driver of equipment (50), reads described external equipment (50) from described memorizer (30)
State and control information process.
Method the most according to claim 1, it is characterised in that when the described external equipment of detection
(50), when being changed into the first state by the second state, described outside is set by described second processor (12)
The control that standby (50) have gives back described first processor (11), described first processor (11)
Run the driver of described external equipment (50), from described memorizer (30), read described outside
State and the control information of equipment (50) process.
Method the most according to claim 1, it is characterised in that described first processor (11)
Described external equipment (50) is controlled by dma controller (40) with described second processor (12)
And carry out data transmission between described memorizer (30).
Method the most according to claim 1, it is characterised in that described first processor (11)
Accept the interrupt requests of described external equipment (50), and described second processor (12) shield described outside
The interrupt requests step of portion's equipment (50) is realized by interrupt control unit.
5. according to the method described in any claim in claim 1 to 5, it is characterised in that institute
State first processor (11) or described second processor (12) runs driving of described external equipment (50)
Dynamic program, reads state and the information of control of described external equipment (50) from described memorizer (30)
Carry out processing step to include:
The state and the control information that read described external equipment (50) from described memorizer (30) are carried out
Initialize, and enter driven flow process.
6. a heterogeneous multiprocessor system, it is characterised in that including: first processor (11),
Second processor (12), memorizer (30) and external equipment (50)；
Described first processor (11) and described second processor (12) connect memorizer (30), logical
Cross device bus and access described external equipment (50)；
The interrupt signal of described external equipment (50) is coupled with the first interrupt control unit (21) and second
Interrupt control unit (22), described first interrupt control unit (21) is with described first processor (11) even
Connecing, described second interrupt control unit (22) is connected with described second processor (12)；
When system initialization, described first processor (11) has control to described external equipment (50)
System power, the most described first processor (11) accepts the interrupt requests of described external equipment (50),
And described second processor (12) shields the interrupt requests of described external equipment (50)；At described first
Reason device (11) runs the driver of described external equipment (50), detects described external equipment (50)
State；When described external equipment (50) is in the first state, described first processor (11) is right
The control command of described external equipment (50) and data transmission process, by described external equipment (50)
State and control information write-in memory (30)；When the described external equipment (50) of detection is by first
When state is changed into the second state, described external equipment (50) is had by described first processor (11)
Control hand to described second processor (12), described second processor (12) run described outside
The driver of portion's equipment (50), reads described external equipment (50) from described memorizer (30)
State and control information process.
System the most according to claim 1, it is characterised in that also include dma controller (40),
Described first processor (11) and described second processor (12) are by described dma controller (40)
Control to carry out data transmission between described external equipment (50) and described memorizer (30).
System the most according to claim 1, it is characterised in that described first processor (11)
With described second processor (12) specifically for,
From described memorizer (30), the state of the described external equipment of reading (50) and the information of control are to institute
State external equipment (50) to initialize, and enter driven flow process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510062427.9A CN105988945A (en) | 2015-02-06 | 2015-02-06 | Heterogeneous multiprocessor system and driving control method thereof |
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| CN201510062427.9A CN105988945A (en) | 2015-02-06 | 2015-02-06 | Heterogeneous multiprocessor system and driving control method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302562A (en) * | 2017-05-23 | 2017-10-27 | 中国科学院计算技术研究所 | The adaptive command processing system and method for a kind of internet-of-things terminal equipment |
| CN111694532A (en) * | 2020-06-11 | 2020-09-22 | 翱捷科技(上海)有限公司 | Display control method of single-chip heterogeneous system and wearable device |
| CN112347015A (en) * | 2021-01-08 | 2021-02-09 | 南京芯驰半导体科技有限公司 | Communication device and method between heterogeneous multiprocessors of system on chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171564A (en) * | 2005-05-11 | 2008-04-30 | 英特尔公司 | Seamless transition of operating environments in mobile systems for power optimization |
| CN101661321A (en) * | 2008-08-25 | 2010-03-03 | 联想(北京)有限公司 | Computer and method for controlling operation thereof |
| CN102385562A (en) * | 2010-08-31 | 2012-03-21 | 联想(北京)有限公司 | Method for interaction between computer and data |
| CN103092317A (en) * | 2011-10-31 | 2013-05-08 | 联想(北京)有限公司 | Electronic device and operation method thereof |
-
2015
- 2015-02-06 CN CN201510062427.9A patent/CN105988945A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171564A (en) * | 2005-05-11 | 2008-04-30 | 英特尔公司 | Seamless transition of operating environments in mobile systems for power optimization |
| CN101661321A (en) * | 2008-08-25 | 2010-03-03 | 联想(北京)有限公司 | Computer and method for controlling operation thereof |
| CN102385562A (en) * | 2010-08-31 | 2012-03-21 | 联想(北京)有限公司 | Method for interaction between computer and data |
| CN103092317A (en) * | 2011-10-31 | 2013-05-08 | 联想(北京)有限公司 | Electronic device and operation method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302562A (en) * | 2017-05-23 | 2017-10-27 | 中国科学院计算技术研究所 | The adaptive command processing system and method for a kind of internet-of-things terminal equipment |
| CN107302562B (en) * | 2017-05-23 | 2019-12-03 | 中国科学院计算技术研究所 | A kind of the adaptive command processing system and method for internet-of-things terminal equipment |
| CN111694532A (en) * | 2020-06-11 | 2020-09-22 | 翱捷科技(上海)有限公司 | Display control method of single-chip heterogeneous system and wearable device |
| CN111694532B (en) * | 2020-06-11 | 2021-06-04 | 翱捷科技股份有限公司 | Display control method of single-chip heterogeneous system and wearable device |
| CN112347015A (en) * | 2021-01-08 | 2021-02-09 | 南京芯驰半导体科技有限公司 | Communication device and method between heterogeneous multiprocessors of system on chip |
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