CN101097559A - System and method for realizing interconnect between main processor and coprocessor interface - Google Patents
System and method for realizing interconnect between main processor and coprocessor interface Download PDFInfo
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- CN101097559A CN101097559A CNA2006100894531A CN200610089453A CN101097559A CN 101097559 A CN101097559 A CN 101097559A CN A2006100894531 A CNA2006100894531 A CN A2006100894531A CN 200610089453 A CN200610089453 A CN 200610089453A CN 101097559 A CN101097559 A CN 101097559A
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Abstract
The invention discloses a kind of system to realize connection between main processor and coprocessor, which includes main processor, at least one coprocessor, dual-port data memory, data bus of main processor, data bus of coprocessor, at least one instruction register, and at least one state register. The invention also discloses a kind of method to realize connection between main processor and coprocessor, and it includes: A. the main processor writes the data which will be transmitted to coprocessor in the indicated storage region of dual-port data memory, and sends starting command to coprocessor; B. the coprocessor receives the starting instruction and returns the state character of receiving instruction, and accesses the indicated storage section to get the data written by main processor, and runs the operation defined in starting instruction; C. when the coprocessor finishes the operation, it returns the status character of finishing command to main processor, and the main processor gets the result of coprocessor.
Description
Technical field
The present invention relates to Computer Architecture and VLSI (very large scale integrated circuit) designs technical field, relate in particular to a kind of system and method for realizing primary processor and coprocessor interface and interconnection.
Background technology
Coprocessor is at different application scenarios and demand, to primary processor expansion, assist primary processor to finish the processor that special applications is handled.Floating-point operation coprocessor for example, multimedia coprocessor etc.
Coprocessor is programmable.Coprocessor has the coprocessor command set that expands on primary processor instruction set basis, coprocessor contains the functional unit towards application-specific, can be used to quicken the processing of application-specific.
The traditional primary processor and the interface of coprocessor adopt comparatively complicated closely-coupled mode.For example, (Advanced RISC Machines's senior compacting instruction set processor ARM) interconnects and communication with the coprocessor interface of its coprocessor interface by special use.The interface of coprocessor comprises following four class signals: clock signal, clock control signal, streamline are followed signal and handshake.The coprocessor of ARM and arm processor use same clock signal.The streamline that oneself is arranged in the coprocessor.Coprocessor uses a pipeline follower by the coprocessor interface that is connected with arm processor, the instruction of carrying out in the ARM kernel streamline is followed the tracks of, and kept acting in agreement of two streamlines.
But the interface of existing primary processor and coprocessor and interconnection structure have some latent defects that can't avoid.For example, compatibility is not strong, can only support specific primary processor and coprocessor; It is thinner that coprocessor carries out the granularity of data processing, can only effectively carry out the processing of individual data word, can not support the data processing that granularity is thicker; The shared one section streamline of coprocessor and primary processor, both parallel runnings simultaneously; Do not support coprocessor command set design flexibly etc.
Summary of the invention
(1) technical matters that will solve
Deficiency at above-mentioned prior art existence, a fundamental purpose of the present invention is to provide a kind of system that realizes primary processor and coprocessor interface and interconnection, to improve the compatibility between primary processor and the coprocessor, make coprocessor can support the data processing of various granularities, and make coprocessor and the processor can parallel running, support coprocessor command set design flexibly.
Another fundamental purpose of the present invention is to provide a kind of method that realizes primary processor and coprocessor interface and interconnection, to improve the compatibility between primary processor and the coprocessor, make coprocessor can support the data processing of various granularities, and make coprocessor and the processor can parallel running, support coprocessor command set design flexibly.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of system that realizes primary processor and coprocessor interface and interconnection comprises a primary processor and at least one coprocessor, and this system also comprises:
Dual port data memory is used to realize the data communication between described primary processor and at least one coprocessor;
The primary processor data bus is used to connect described primary processor and dual port data memory;
The coprocessor data bus is used to connect dual port data memory and described at least one coprocessor;
At least one command word register, the instruction that is used for being received from described primary processor sends to the coprocessor that is connected with self;
At least one status word register, the status information that is used for being received from coprocessor sends to described primary processor.
Described dual port data memory comprises: the data access port that is connected with primary processor by described primary processor data bus; The data access port that is connected with at least one coprocessor by described coprocessor data bus; With with described two data access port corresponding address decoding logic circuits.
Two data access ports of described dual port data memory comprise respectively at least: clock signal, control signal, address signal and data-signal.
The data access port of described primary processor by being connected with self, and the data access port of coprocessor by being connected with self are carried out read operation or write operation to the different storage zone of dual port data memory simultaneously.
Described primary processor is the primary processor of Harvard structure; Described primary processor data bus is the data bus of Harvard structure primary processor, is used to connect the primary processor of described Harvard structure and a data access port of dual port data memory; Described coprocessor data bus is used to connect another data access port of described at least one coprocessor and dual port data memory.
Described command word register is corresponding one by one with coprocessor; Described primary processor conducts interviews to the complete order word register by carrying out write operation, and described coprocessor conducts interviews by carrying out the read operation pair command word register corresponding with self.
Described status word register is corresponding one by one with coprocessor; Described primary processor conducts interviews to whole status word registers by carrying out read operation, and described coprocessor conducts interviews by carrying out the write operation pair status word register corresponding with self.
A kind of method that realizes primary processor and coprocessor interface and interconnection, this method comprises:
The data that A, primary processor pass to coprocessor with need write the designated storage area in the dual port data memory, and send the coprocessor enabled instruction to coprocessor;
B, coprocessor receive after the enabled instruction to primary processor return command accepting state word, and the designated storage area in the visit dual port data memory is obtained the data that primary processor writes, and carries out the operation that defines in the enabled instruction;
C, coprocessor are finished after the operation that defines in the instruction to primary processor return command completion status word, and primary processor obtains the execution result of coprocessor.
The data that primary processor described in the steps A passes to coprocessor with need write the designated storage area in the dual port data memory, are to realize by the designated storage area in the data access port visit dual port data memory of primary processor data bus and dual port data memory.
Primary processor described in the steps A sends the coprocessor enabled instruction to coprocessor and comprises: primary processor sends to coprocessor by command word register and carries the coprocessor enabled instruction of carrying out defining operation and visit designated storage area domain information at least.
Coprocessor described in the step B returns by status word register to primary processor return command accepting state word.
Coprocessor described in the step B further comprises behind primary processor return command accepting state word: primary processor is carried out normal program flow according to the order accepting state word that receives.
Coprocessor described in the step C further is carried at execution result in the order completion status word after finishing the operation that defines in the instruction, coprocessor described in the step C is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:
C1, coprocessor send the order completion status word that carries execution result by status word register to primary processor;
C2, primary processor receive the order completion status word that coprocessor sends, and obtain the execution result that coprocessor returns from order completion status word.
Coprocessor described in the step C is finished the designated storage area that further the execution result data is write after the operation that defines in the instruction in the dual port data memory, coprocessor described in the step C is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:
C1 ', coprocessor send order completion status word by status word register to primary processor;
C2 ', primary processor receive order completion status word, and the designated storage area in the visit dual port data memory is obtained the execution result data that coprocessor writes.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the present invention, because primary processor and coprocessor utilize separately data bus and streamline respectively, so primary processor can interconnect and collaborative work with various types of coprocessors, has improved the compatibility between primary processor and the coprocessor greatly.
2, utilize the present invention, handle, can carry out the coarseness data processing of a plurality of data words again, so coprocessor can be supported the data processing of various granularities because coprocessor when carrying out data processing, can either carry out the fine-grained data of individual data word.
3, utilize the present invention, because primary processor and coprocessor adopt the mechanism of timesharing visit to the specific region of dual port data memory, coprocessor can not influence primary processor to the accessing operation of data storer and the process of executable operations to the accessing operation of data storer and the process of executable operations, the sequential of the two accesses data memory can not interact yet, also normal executive routine stream of primary processor in the coprocessor executable operations is so primary processor and coprocessor can parallel runnings.
4, utilize the present invention, primary processor and coprocessor also can obtain very high data access bandwidth by dual port data memory, and coprocessor can also be supported coprocessor command set design flexibly.
5, utilize the present invention, primary processor only sends a coprocessor instruction at every turn, promptly have only a coprocessor to operate also and might visit the coprocessor data bus, also have only a coprocessor that the coprocessor data bus is conducted interviews at any time, the problem of coprocessor data bus access conflict therefore can not occur.
6, utilize the present invention, finish at coprocessor before the specific operation and return state of coprocessor instruction definition, primary processor can not start other coprocessor.Like this, at a time have only primary processor and a coprocessor to work simultaneously, the situation that a plurality of coprocessors are worked simultaneously can not occur, the problem of operating collision between the coprocessor therefore can not occur.
Description of drawings
Fig. 1 is the synoptic diagram of the system of realization primary processor provided by the invention and N coprocessor interface and interconnection;
Fig. 2 is the synoptic diagram of the system of realization primary processor provided by the invention and coprocessor interface and interconnection;
Fig. 3 is the realization flow figure of realization primary processor provided by the invention and coprocessor interface and interconnection overall technological scheme;
Fig. 4 is a method flow diagram of realizing primary processor and coprocessor interface and interconnection according to first embodiment of the invention;
Fig. 5 is a method flow diagram of realizing primary processor and coprocessor interface and interconnection according to second embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the synoptic diagram of the system of realization primary processor provided by the invention and N coprocessor interface and interconnection, and this system comprises a primary processor and at least one coprocessor, and this system also comprises:
Dual port data memory is used to realize the data communication between described primary processor and at least one coprocessor;
The primary processor data bus is used to connect described primary processor and dual port data memory;
The coprocessor data bus is used to connect dual port data memory and described at least one coprocessor;
At least one command word register, the instruction that is used for being received from described primary processor sends to the coprocessor that is connected with self;
At least one status word register, the status information that is used for being received from coprocessor sends to described primary processor.
Above-mentioned primary processor is the primary processor of Harvard structure, has independently data-carrier store and program storage, is connected with program bus with data bus respectively, gets to refer to and carry out parallelly independently carry out.
Wherein, the data bus of primary processor is identified as the primary processor data bus in order to distinguish mutually with the data bus of coprocessor, and the data bus of coprocessor is identified as the coprocessor data bus.
Dual port data memory is expanded by the original one-port memory of primary processor, and primary processor and coprocessor carry out data communication by dual port data memory.Described dual port data memory comprises: the data access port that is connected with primary processor by described primary processor data bus, i.e. data access port A; The data access port that is connected with at least one coprocessor by described coprocessor data bus, i.e. data access port B; With with described two data access port corresponding address decoding logic circuits.
Dual port data memory has fully independently two sets of data access ports and corresponding address decoding logic circuit.Data access port A that the data-carrier store of dual-port has and data access port B are separate.Data access port A and data access port B comprise respectively at least: clock signal, control signal, address signal and data-signal etc.
The primary processor data bus links to each other with the data access port A of dual port data memory, and primary processor is by primary processor data bus and data access port A visit dual port data memory.The data access port A maintenance of dual port data memory and being connected of primary processor data bus.
The coprocessor data bus links to each other with the data access port B of dual port data memory, and coprocessor is by coprocessor data bus and data access port B visit dual port data memory.The data access port B of dual port data memory is connected with the coprocessor data bus, and by coprocessor data bus a plurality of coprocessors in parallel.
Because primary processor only sends a coprocessor instruction at every turn, promptly have only a coprocessor to operate also and might visit the coprocessor data bus, so have only a coprocessor that the coprocessor data bus is conducted interviews at any time at most, the access conflict of coprocessor data bus therefore can not occur.
Because primary processor can only start a coprocessor at most at every turn, a plurality of coprocessors on the coprocessor data bus, can not occur and work simultaneously, the situation of competition bus resource, and coprocessor all carries the logic of address decoding.
Two sets of data access ports of dual port data memory can work independently in different clock frequencies, and can conduct interviews to dual port data memory simultaneously.But,, then might visit failure if simultaneously read-write operation is carried out in a certain specific memory zone of dual port data memory.In order to guarantee the effectively correct of data communication, primary processor and coprocessor carry out the visit timesharing of dual-ported memory in the present invention.
Primary processor is by data access port A, and coprocessor carries out read operation or write operation to the different storage zone of dual port data memory simultaneously by data access port B.But primary processor is by data access port A, and coprocessor can not read while write the same storage unit of dual port data memory by data access port B.
When primary processor sends the work of coprocessor instruction startup coprocessor, the memory area of in coprocessor instruction, having specified coprocessor to visit.When coprocessor conducted interviews to this memory area, the operation of coprocessor did not influence the normal executive routine stream of primary processor, but primary processor can only be visited other memory area except that specifying the coprocessor access region.When coprocessor has been finished after the visit in designated memory zone and executing corresponding operating, will be to primary processor return command completion status word.Primary processor receives after the order completion status word, just can the memory area of specifying the coprocessor visit be conducted interviews.
When carrying out the data communication of primary processor and coprocessor, the data that primary processor at first is delivered to need coprocessor write the particular area of memory of dual port data memory, and start primary processor.After primary processor sends coprocessor instruction and starts coprocessor work, coprocessor can be by the port B of coprocessor data bus and dual-ported memory, the particular area of memory of visit dual port data memory is read in service data, and operation writes data after finishing.This moment, primary processor can not conduct interviews to this memory area, have only when coprocessor and finish visit and return command completion status word the data storer, and primary processor receives after the order completion status word, and primary processor just can conduct interviews to the particular area of memory of dual port data memory.Primary processor obtains the data that coprocessor writes by the particular area of memory of visit dual port data memory, finishes the data communication between primary processor and coprocessor.
Described command word register is corresponding one by one with coprocessor, and primary processor conducts interviews to the complete order word register by carrying out write operation, and coprocessor conducts interviews by carrying out the read operation pair command word register corresponding with self.
Described status word register is corresponding one by one with coprocessor, and primary processor conducts interviews to whole status word registers by carrying out read operation, and coprocessor conducts interviews by carrying out the write operation pair status word register corresponding with self.
Primary processor transmits coprocessor instruction by command word register to coprocessor, coprocessor by status word register and in conjunction with interrupt request singal to the primary processor return state.Command word register will pass to coprocessor from the coprocessor instruction that primary processor sends, and status word register then will be given primary processor from the state transfer that coprocessor returns.Simultaneously, to return be that external interrupt with primary processor combines to the state of coprocessor.
N among a Fig. 1 command word register and N status word register all are the visits of primary processor addressable.Coprocessor then can only addressing have access to its an affiliated command word register and status word register.For example coprocessor N can only visit order word register N and status word register N.
Simultaneously, primary processor can only carry out read operation to status word register, and coprocessor can only carry out write operation to status word register; Primary processor can only carry out write operation to command word register, and coprocessor can only carry out read operation to command word register.
Interrupt request singal and interrupt response signal also are one to one.The corresponding interrupt response signal of the interruption application signal N among Fig. 1 N for example.Interrupt request singal and interrupt response signal belong to primary processor, respectively a corresponding N external interrupt, for example the external interrupt N of interruption application signal N and the corresponding primary processor of interrupt response signal N.Each coprocessor is assigned with an external interrupt resource, and connects an interrupt request singal and an interrupt response signal respectively.For example coprocessor N is connected to interrupt request singal N and interrupt response signal N.Coprocessor N is connected the external interrupt N that also can apply for primary processor by interrupting application signal N with interrupt response signal N with primary processor, when coprocessor sent the external interrupt request, primary processor entered the interrupt service routine of external interrupt N correspondence and carries out.
Primary processor to the process that coprocessor sends order is: primary processor starts coprocessor N as need and carries out certain specific operation, then with command word R write command word register in the process of carrying out normal program flow.Wherein command word R has defined the action type of coprocessor and the memory area that can visit of primary processor appointment.The N that is connected with a primary processor coprocessor when not receiving order, all is in the order query State, constantly the querying command word register.The value that inquires among the command word register N as certain the coprocessor N in the coprocessor is its coprocessor instruction R that can discern and carry out, then can return command accepting state word, and begin corresponding co processor operation.Finish at coprocessor N before the specific operation and return state of coprocessor instruction R definition, primary processor can not start other coprocessor.Like this, at a time have only processor and a coprocessor to work simultaneously at most, the situation that a plurality of coprocessors are worked simultaneously can not occur, the problem of operating collision between the coprocessor therefore can not occur.
Coprocessor to the process of primary processor return state is: when coprocessor N initiates when the state of primary processor returns, coprocessor N is changed to interrupt request singal N effectively so that processor N can summary responses and handled after with status word S write state word register N.Wherein defined the state that coprocessor N returns to primary processor among the status word S.
Whether primary processor receives this interruption by interruptable controller according to condition judgment such as interrupt mask bit and interrupt priority levels after receiving interruption application N.As receiving interrupt request N, primary processor can be changed to interrupt response signal N effectively.Be in the coprocessor N that interrupts the application waiting status detect the interrupt response n-signal effectively after, cancel and interrupt application signal N.
Realize that based on the present invention shown in Figure 1 the synoptic diagram of the system of primary processor and N coprocessor interface and interconnection, Fig. 2 show the synoptic diagram of the system of realization primary processor provided by the invention and coprocessor interface and interconnection.
Primary processor and a coprocessor interface and interconnected structure are the special circumstances of frame mode when N=1 that the primary processor among Fig. 1 is connected with N coprocessor.In primary processor and N coprocessor interface and interconnected structure, a plurality of coprocessors can not worked simultaneously.Have only primary processor and a coprocessor concurrent working simultaneously at most in some moment.There is not data communication between coprocessor and coprocessor yet, can not occur situations such as resource access conflict between coprocessor yet.Therefore, in full accord in communication modes between primary processor and coprocessor and primary processor and N coprocessor interface and the interconnected structure in primary processor and coprocessor interface and interconnected structure.
Realize the synoptic diagram of the system of primary processor and N coprocessor interface and interconnection based on the present invention shown in Figure 1, and the present invention shown in Figure 2 realizes the synoptic diagram of the system of primary processor and coprocessor interface and interconnection, Fig. 3 shows the realization flow figure of realization primary processor provided by the invention and coprocessor interface and interconnection overall technological scheme, and this method may further comprise the steps:
Step 301: the data that primary processor passes to coprocessor with need write the designated storage area in the dual port data memory, and send the coprocessor enabled instruction to coprocessor;
Step 302: coprocessor receives after the enabled instruction to primary processor return command accepting state word, and the designated storage area in the visit dual port data memory is obtained the data that primary processor writes, and carries out the operation that defines in the enabled instruction;
Step 303: coprocessor is finished after the operation that defines in the instruction to primary processor return command completion status word, and primary processor obtains the execution result of coprocessor.
The data that primary processor described in the above-mentioned steps 301 passes to coprocessor with need write the designated storage area in the dual port data memory, are to realize by the designated storage area in the data access port visit dual port data memory of primary processor data bus and dual port data memory.
Primary processor described in the above-mentioned steps 301 sends the coprocessor enabled instruction to coprocessor and comprises: primary processor sends to coprocessor by command word register and carries the coprocessor enabled instruction of carrying out defining operation and visit designated storage area domain information at least.
Coprocessor described in the above-mentioned steps 302 returns by status word register to primary processor return command accepting state word.
Coprocessor described in the above-mentioned steps 302 further comprises behind primary processor return command accepting state word: primary processor is carried out normal program flow according to the order accepting state word that receives.
After coprocessor was finished the operation that defines in the instruction in the above-mentioned steps 303, primary processor can obtain execution result by following dual mode:
Mode one, coprocessor further are carried at execution result in the order completion status word after finishing the operation that defines in the instruction, and described coprocessor is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:
Step 3031: coprocessor sends the order completion status word that carries execution result by status word register to primary processor;
Step 3032: primary processor receives the order completion status word that coprocessor sends, and obtains the execution result that coprocessor returns from order completion status word.
Mode two, coprocessor are finished the designated storage area that further the execution result data is write after the operation that defines in the instruction in the dual port data memory, described coprocessor is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:
Step 3031 ': coprocessor sends order completion status word by status word register to primary processor;
Step 3032 ': primary processor receives order completion status word, and the designated storage area in the visit dual port data memory is obtained the execution result data that coprocessor writes.
Below, realization flow figure based on realization primary processor provided by the invention shown in Figure 3 and coprocessor interface and interconnection overall technological scheme, system with primary processor shown in Figure 2 and coprocessor interface and interconnection is an example, describes processor and the interface of coprocessor and interconnected method among the present invention in detail.
As shown in Figure 4, Fig. 4 is a method flow diagram of realizing primary processor and coprocessor interface and interconnection according to first embodiment of the invention, and the concrete implementation step of this method is as follows:
Step 401: beginning.
Step 402: send the coprocessor enabled instruction.Be that primary processor sends coprocessor enabled instruction R by command word register to coprocessor, coprocessor enabled instruction R has defined the concrete operations that coprocessor need be carried out, and the data memory region of having specified coprocessor to visit.
Step 403: return command accepting state word.Being coprocessor sends order accepting state word S by status word register to primary processor, and it is effective to put interrupt request singal simultaneously, and the sign coprocessor has received the coprocessor enabled instruction, begins to carry out the defined operational processes of coprocessor instruction R.
Step 404: cancel the coprocessor enabled instruction.Be that primary processor reception interrupt request singal is effective, enter this outside interrupt service routine that interrupts correspondence, status word in the accepting state word register, if status word is order accepting state word S, then cancel the coprocessor enabled instruction, primary processor begins to carry out normal program flow, but can not the data memory region that coprocessor is being visited be conducted interviews.
Step 405: return command completion status word.Be after coprocessor is finished the defined operation of coprocessor instruction R, execution result is carried among the order completion status word U, send order completion status word U by status word register to primary processor, it is effective to put interrupt request singal simultaneously, the sign coprocessor has been finished the defined operation of coprocessor instruction R, needs the execution result information of returning after finishing by order completion status word U return.
Step 406: receive order completion status word.Be that primary processor reception interrupt request singal is effective, enter and interrupt corresponding interrupt service routine, order completion status word U in the accepting state word register, and primary processor extracts the execution result information that needed coprocessor returns from order completion status word U.
In this step, primary processor could conduct interviews to the particular memory region in the dual port data memory after only receiving order completion status word U.
Step 407: finish.The samsara that coprocessor is carried out finishes.
In the step 405 of this embodiment, after coprocessor is finished the defined operation of coprocessor instruction R, execution result is carried among the order completion status word U, send order completion status word U by status word register to primary processor, it is effective to put interrupt request singal simultaneously, the sign coprocessor has been finished the defined operation of coprocessor instruction R, needs the execution result information of returning after finishing by order completion status word U return.In actual applications, further the execution result data are write designated storage area in the dual port data memory after the operation that coprocessor also can define in finishing instruction.At this moment, after primary processor receives the order completion status word that coprocessor returns, can obtain the execution result information of coprocessor by the designated storage area in the visit dual port data memory.
Said process specifically can be referring to Fig. 5, and Fig. 5 is a method flow diagram of realizing primary processor and coprocessor interface and interconnection according to second embodiment of the invention, and the concrete implementation step of this method is as follows:
Step 501: beginning.
Step 502: send the coprocessor enabled instruction.Be that primary processor sends coprocessor enabled instruction R by command word register to coprocessor, coprocessor enabled instruction R has defined the concrete operations that coprocessor need be carried out, and the data memory region of having specified coprocessor to visit.
Step 503: return command accepting state word.Being coprocessor sends order accepting state word S by status word register to primary processor, and it is effective to put interrupt request singal simultaneously, and the sign coprocessor has received the coprocessor enabled instruction, begins to carry out defined operation place of coprocessor instruction R and buries.
Step 504: cancel the coprocessor enabled instruction.Be that primary processor reception interrupt request singal is effective, enter this outside interrupt service routine that interrupts correspondence, status word in the accepting state word register, if status word is order accepting state word S, then cancel the coprocessor enabled instruction, primary processor begins to carry out normal program flow, but can not the data memory region that coprocessor is being visited be conducted interviews.
Step 505: return command completion status word.Be after coprocessor is finished the defined operation of coprocessor instruction R, the execution result data are write designated storage area in the dual port data memory, and send order completion status word U to primary processor by status word register, it is effective to put interrupt request singal simultaneously, and the sign coprocessor has been finished the defined operation of coprocessor instruction R.
Step 506: receive order completion status word.Be that primary processor reception interrupt request singal is effective, enter and interrupt corresponding interrupt service routine, order completion status word U in the accepting state word register, and, obtain the execution result data that coprocessor writes according to the designated storage area in the order completion status word U visit dual port data memory that receives.
Step 507: finish.The samsara that coprocessor is carried out finishes.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (14)
1, a kind of system that realizes primary processor and coprocessor interface and interconnection comprises a primary processor and at least one coprocessor, it is characterized in that this system also comprises:
Dual port data memory is used to realize the data communication between described primary processor and at least one coprocessor;
The primary processor data bus is used to connect described primary processor and dual port data memory;
The coprocessor data bus is used to connect dual port data memory and described at least one coprocessor;
At least one command word register, the instruction that is used for being received from described primary processor sends to the coprocessor that is connected with self;
At least one status word register, the status information that is used for being received from coprocessor sends to described primary processor.
2, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described dual port data memory comprises:
The data access port that is connected with primary processor by described primary processor data bus;
The data access port that is connected with at least one coprocessor by described coprocessor data bus; With
With described two data access port corresponding address decoding logic circuits.
3, the system of realization primary processor according to claim 2 and coprocessor interface and interconnection, it is characterized in that two data access ports of described dual port data memory comprise respectively at least: clock signal, control signal, address signal and data-signal.
4, the system of realization primary processor according to claim 2 and coprocessor interface and interconnection is characterized in that,
The data access port of described primary processor by being connected with self, and the data access port of coprocessor by being connected with self are carried out read operation or write operation to the different storage zone of dual port data memory simultaneously.
5, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described primary processor is the primary processor of Harvard structure;
Described primary processor data bus is the data bus of Harvard structure primary processor, is used to connect the primary processor of described Harvard structure and a data access port of dual port data memory;
Described coprocessor data bus is used to connect another data access port of described at least one coprocessor and dual port data memory.
6, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described command word register is corresponding one by one with coprocessor;
Described primary processor conducts interviews to the complete order word register by carrying out write operation, and described coprocessor conducts interviews by carrying out the read operation pair command word register corresponding with self.
7, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described status word register is corresponding one by one with coprocessor;
Described primary processor conducts interviews to whole status word registers by carrying out read operation, and described coprocessor conducts interviews by carrying out the write operation pair status word register corresponding with self.
8, a kind of method that realizes primary processor and coprocessor interface and interconnection is characterized in that this method comprises:
The data that A, primary processor pass to coprocessor with need write the designated storage area in the dual port data memory, and send the coprocessor enabled instruction to coprocessor;
B, coprocessor receive after the enabled instruction to primary processor return command accepting state word, and the designated storage area in the visit dual port data memory is obtained the data that primary processor writes, and carries out the operation that defines in the enabled instruction;
C, coprocessor are finished after the operation that defines in the instruction to primary processor return command completion status word, and primary processor obtains the execution result of coprocessor.
9, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection, it is characterized in that, the data that primary processor described in the steps A passes to coprocessor with need write the designated storage area in the dual port data memory, are to realize by the designated storage area in the data access port visit dual port data memory of primary processor data bus and dual port data memory.
10, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, primary processor described in the steps A sends the coprocessor enabled instruction to coprocessor and comprises:
Primary processor sends to coprocessor by command word register and carries the coprocessor enabled instruction of carrying out defining operation and visit designated storage area domain information at least.
11, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, coprocessor described in the step B returns by status word register to primary processor return command accepting state word.
12, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, coprocessor described in the step B further comprises behind primary processor return command accepting state word:
Primary processor is carried out normal program flow according to the order accepting state word that receives.
13, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, coprocessor described in the step C further is carried at execution result in the order completion status word after finishing the operation that defines in the instruction,
Coprocessor described in the step C is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:
C1, coprocessor send the order completion status word that carries execution result by status word register to primary processor;
C2, primary processor receive the order completion status word that coprocessor sends, and obtain the execution result that coprocessor returns from order completion status word.
14, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection, it is characterized in that, coprocessor described in the step C is finished the designated storage area that further the execution result data is write after the operation that defines in the instruction in the dual port data memory
Coprocessor described in the step C is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:
C1 ', coprocessor send order completion status word by status word register to primary processor;
C2 ', primary processor receive order completion status word, and the designated storage area in the visit dual port data memory is obtained the execution result data that coprocessor writes.
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