CN100512007C - Method and device for clock detection - Google Patents
Method and device for clock detection Download PDFInfo
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- CN100512007C CN100512007C CNB2006101093155A CN200610109315A CN100512007C CN 100512007 C CN100512007 C CN 100512007C CN B2006101093155 A CNB2006101093155 A CN B2006101093155A CN 200610109315 A CN200610109315 A CN 200610109315A CN 100512007 C CN100512007 C CN 100512007C
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Abstract
This invention relates to one clock test method and device, which comprises the following steps: firstly generating meter energy signals according to local timing mechanism and the meter can transfer the tested signals into the clock zone to be tested to generate clock timer energy signals of zero and triggering the tested clock zone meter by signal and to start metering at fixed time circle; observing meter results to judge the accuracy of the clock to be tested.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to a kind of method and device of clock detection.
Background technology
The clock detection technology is a most basic demand of present electronic technology field, and the purpose of carrying out clock detection is in order to ensure the operate as normal of electronic system.
At present, usually the clock detection technology that adopts mainly is to detect having or not of measured clock, usually the method that adopts is as follows: at first, by the measured clock actuation counter, to clock division, signal sampling after utilizing local standard time clock to frequency division then, then utilize the periodic signal after sampling that counter is carried out synchronous zero clearing, the value of last detection counter, thus judge whether measured clock is unusual.
In addition, the implementation method of some clock accuracy detection technique exists significantly not enoughly at present, and the method such as in count results one class in Direct Sampling measured clock territory, reference clock territory can cause the probability of testing mechanism omission and flase drop all to increase greatly; Also be difficult to adapt to electronic system to the high-precision requirement of clock.
Along with the continuous increase of the integrated level of circuit scale and circuit, electronic system is also more and more higher to the requirement of processing speed and precision; A key factor that influences the electronic system test or the speed of service and precision is exactly a clock, thereby cause electronic system more and more higher to the requirement of the accuracy of clock, accurate clock can guarantee the precise synchronization of system signal, and then can guarantee the processing accuracy of electronic system.If clock goes wrong, electronic system can not synchronous working, will influence the operating rate and the processing accuracy of system, even cause the paralysis of whole system.
As can be seen, whether accurate reliability, stability and the speed that will directly influence electronic system of clock.This just makes that how accurately detecting clock frequency becomes a major issue that needs to be resolved hurrily.
And from present case, the above-mentioned clock detection technology that prior art provides has two classes, and a class is only judged with regard to having or not of clock, and the precision of measured clock is not had concrete detection implementation method.Also there is apparent in view defective in another kind of frequency detecting method, therefore, can't know reliability of service that measured clock provides exactly.So also just can't really assess the performance and the quality of measured clock exactly, thereby the service that provides when measured clock also just can't be provided the problem that might cause when unusual occurs.
Summary of the invention
The method and the device that the purpose of this invention is to provide a kind of clock detection.Reach device by this method and can know the precision of measured clock frequency exactly, thereby can accurately assess the performance and the quality of service that measured clock provides.
The invention provides a kind of method of clock detection, this method comprises the following steps:
A, by measured clock frequency detecting signal, local count enable signal is transformed into the measured clock territory from the local clock territory, trigger the measured clock counter, the clock cycle quantity that measured clock was dropped in the set time begins counting;
B, finish the clock cycle quantity counting in the set time after, extract described count results, realize detection according to this result at the frequency of measured clock.
Described steps A also comprises:
A1, according to the local count enable signal of local clock signal actuation counter and timing signal for generating, and utilize this enable signal to generate the measured clock count enable signal in measured clock territory, trigger the measured clock counter, described timing signal is used to limit the value of described set time.
Described steps A comprises:
A11, described local count enable signal produce the measured clock count enable signal through the measured clock signal latch, finish the conversion of local count enable signal from the local clock territory to the measured clock territory;
A12, generate measured clock counter O reset signal by the measured clock count enable signal;
A13, measured clock counter O reset signal triggering measured clock counter;
A14, measured clock counter receive the measured clock count enable signal and trigger, and measured clock are dropped on the quantity of the clock cycle in the described set time and count.
Described step B comprises: the clock cycle quantity counting in the set time finishes, described count results is stable promptly keep count results constant after, extract described count results.
Described step B comprises:
After B1 extracts count results, the count results of measured clock counter is compared with the predetermined range of determining based on the desired value of measured clock frequency,, then determine the requirement of measured clock compliance with system if count results meets pre-provisioning request; Otherwise, determine that measured clock does not meet system requirements.
Described step B1 also comprises:
The count results of measured clock counter determines that the measured clock frequency meets predetermined requirement within the predetermined range of determining according to the desired value of the measured clock frequency of expectation; Otherwise, determine that the measured clock frequency does not meet predetermined requirement.
Before described steps A, also comprise:
Reference clock by measured clock detects measured clock, and when confirming that measured clock meets the initial survey requirement, carries out described steps A.
The present invention also provides a kind of device of clock detection, comprising:
The processing unit of count enable signal clock zone conversion: be used for local count enable signal process measured clock signal latch is generated the measured clock count enable signal;
Timing control unit: be used to utilize measured clock count enable signal control count detection unit, measured clock territory in the set time, to count, and control count results discriminating unit is extracted count results;
Count detection unit, measured clock territory: be used in the set time clock cycle quantity and count to the measured clock territory;
Count results discriminating unit: be used for extracting, and differentiate the measured clock count results, determine testing result at measured clock at the measured clock count results.
Described device also comprises:
The generation unit of count enable signal: be used for producing local count enable signal according to the local timing signal that local clock and timing control unit generated based on the set time.
The processing unit of described count enable signal clock zone conversion is used for local count enable signal is transformed into the measured clock territory from clock zone, and generation measured clock count enable signal and measured clock counting reset signal, described timing control unit is used to utilize measured clock counting reset signal control count detection unit, measured clock territory to begin counting, utilizes measured clock count enable signal control count detection unit, measured clock territory to finish counting.
As seen from the above technical solution provided by the invention, clock detection technical scheme of the present invention can detect the precision of measured clock effectively, can in time submit the service scenario of measured clock in system to, and in a single day take place in time to find unusually, make it to be solved.Therefore, the present invention, for the designer provides reliable and stable system service that powerful guarantee is provided to the client and has very important significance to the normal operation of monitor system.
Description of drawings
Fig. 1 is the implementation process flow chart of the method for the invention;
Fig. 2 realizes the signal timing diagram that produces in the specific implementation process of clock detection for the present invention;
Fig. 3 is the specific implementation structural representation of clock detecting device of the present invention;
Fig. 4 is the principle schematic of clock detection process provided by the invention.
Embodiment
Core concept of the present invention is by measured clock frequency detecting signal, and local count enable signal is transformed into the measured clock territory from the local clock territory, triggers the measured clock counter, and the clock cycle quantity that measured clock was dropped in the set time begins counting; After finishing the clock cycle quantity counting in the set time, and when guaranteeing that described count results stablize, extract described count results, according to the detection of this result's realization at the frequency of measured clock.
Say that more specifically the present invention realizes that the process of clock detection comprises:
At first produce count enable signal according to local timing mechanism, then count enable signal is transformed into the measured clock territory through the measured clock frequency by clock zone, produce the measured clock counter enable signals, thereby produce measured clock counting reset signal, and by the counter in this signal triggering measured clock territory, the quantity that measured clock is dropped on the clock cycle in the set time begins counting; After finishing the clock cycle quantity counting in the set time, guaranteeing under the stable situation of count results, extract described count results, observation count results, according to the detection of this result's realization at the frequency of measured clock, thus the precision of judgement measured clock frequency.
Detection of the present invention can be once also can be repeatedly or regularly to detect.Preferable embodiment as shown in Figure 1, the invention provides realize clock detection at electronic technology field detailed process as shown in Figure 1, detailed process comprises:
Step 11: the reference clock Refclk_chk by measured clock detects measured clock, confirm that measured clock meets the initial survey requirement, that is to say do not requiring under the situation of clock accuracy, confirm that measured clock can satisfy system requirements substantially, begin to detect clock accuracy afterwards;
Step 12: the local count enable signal of local clock signal actuation counter and timing signal for generating, so that further generate the measured clock enable signal;
Step 13: local count enable signal latchs n all after date through measured clock, produces the measured clock enable signal, and the measured clock enable signal is used to control the measured clock counter;
Step 14: along triggering for generating measured clock counter O reset signal, measured clock counting reset signal is controlled the clear operation of measured clock counter by the measured clock enable signal;
Step 15: measured clock counting reset signal triggers the measured clock counter and begins counting, and this counter enters operating state;
Step 16: the measured clock enable signal limits the measured clock counter in the limiting time inside counting as timing signal, when promptly arriving at the fixed time, finishes counting by the measured clock enable signal along triggering the measured clock counter;
Step 17: after the measured clock rolling counters forward finishes, keep count results constant, guarantee to be extracted stable count results;
Step 18: when timing signal comes, extract the count results of measured clock counter;
Step 19: count results is compared with preset range,, otherwise confirm that measured clock does not meet system requirements if count results in preset range, is confirmed the requirement of measured clock compliance with system.
Through above-mentioned steps, the present invention has realized the accuracy detection at measured clock, thereby can not meet under the situation of system requirements at measured clock, takes appropriate measures in time, to avoid the operate as normal because of clock accuracy problem EVAC (Evacuation Network Computer Model).
For the present invention there being further understanding, the concrete processing operation in the specific implementation process describes to the method for the invention below in conjunction with concrete example.As shown in Figure 2, specifically comprise following treatment step:
Step 21: produce 1 second timing signal T_1s by local timing mechanism;
Step 22:1 timing signal second T_1s obtains timing signal T_1s_r_n after latching the one or more local clock cycle;
When the trailing edge that step 23:1 timing signal second T_1s and timing signal T_1s_r_n produce local count enable signal Cnt_ena_local:1 timing signal second T_1s comes temporarily that just this signal is low level " 0 " by high level " 1 " saltus step, local count enable signal Cnt_ena_local is low level " 0 " by high level " 1 " saltus step, and keep low level always, up to the trailing edge of timing signal T_1s_r_n when just this signal is low level " 0 " by high level " 1 " saltus step, local count enable signal Cnt_ena_local is high level " 1 " by low level " 0 " saltus step, keep high level " 1 " to arrive simultaneously up to the next trailing edge of 1 second timing signal T_1s, repeat foregoing saltus step again, can generate local count enable signal Cnt_ena_local;
Step 24: local count enable signal Cnt_ena_local latchs through measured clock signal Clk_freq_checked, latchs two bat outputs, produces the measured clock count enable signal Cnt_ena_check_n that conversion is come;
Step 25: the measured clock count enable signal Cnt_ena_check_n that conversion is come is latched once more, and the time of latching is two bats of measured clock signal, just two of the measured clock signal clock cycle; Obtain measured clock count enable signal Cnt_ena_check;
Step 26: when just this signal jumped to high level " 1 " by low level " 0 " when the rising edge of measured clock count enable signal Cnt_ena_check came, trigger measured clock counting reset signal Cnt_clr_check and jump to " 1 " by low level " 0 ";
Step 27: when measured clock reset signal Cnt_clr_check trailing edge came, when just Cnt_clr_check jumped to " 0 " by high level " 1 ", flip-flop number Cnt_check began counting;
Step 28: when the trailing edge of measured clock count enable signal Cnt_ena_check arrived, when just Cnt_ena_check jumped to " 0 " by high level " 1 ", counter Cnt_check finished counting;
Step 29: when the trailing edge of local timing signal T_1s_r_n comes, extract counter Cnt_check count results, determine the frequency of measured clock;
Step 210: count results and preset range are compared, if count results in preset range, is then represented the requirement of measured clock compliance with system, otherwise the expression measured clock does not meet system requirements.
The present invention also provides a kind of device of clock detection, and the specific implementation of this device is described further below in conjunction with accompanying drawing 3 and 4 pairs of device implementation structures of the present invention of accompanying drawing and principle as shown in Figure 3 and Figure 4.
Device implementation structure figure of the present invention as shown in Figure 3.Device of the present invention comprises processing unit, timing control unit, count detection unit, measured clock territory and the count results discriminating unit of count enable signal clock zone conversion.The processing unit of described count enable signal clock zone conversion is used for local count enable signal is transformed into the measured clock count enable signal, generates the measured clock count enable signal; Described timing control unit is used to generate the operate as normal of timing signal, control measured clock and count detection unit, and described device also comprises the generation unit of count enable signal.
Annexation between each unit of device of the present invention is as follows: described count results discriminating unit links to each other with count detection unit, described measured clock territory, count detection unit, described measured clock territory links to each other with the processing unit of described count enable signal clock zone conversion, the processing unit of described count enable signal clock zone conversion and the generation unit of described count enable signal link to each other, and count detection unit, described measured clock territory links to each other with the processing unit of described count enable signal clock zone conversion.
The principle schematic of clock detection method of the present invention as shown in Figure 4, reference clock Refclk_chk by measured clock detects measured clock, confirm that measured clock meets the initial survey requirement, that is to say and do not requiring under the situation of clock accuracy, confirm that measured clock can satisfy system requirements substantially, begin to detect clock accuracy afterwards; In conjunction with Fig. 3 and Fig. 4, the concrete steps that detect clock accuracy comprise:
At first, produce 1 second timing signal T_1s by local timing mechanism; 1 second timing signal T_1s obtains timing signal T_1s_r_n after latching the one or more local clock cycle;
Second, after described count enable signal generation unit receives timing signal T_1s and local clock signal Clk_local, generate count enable signal Cnt_ena_local by the count enable signal generation unit, when the trailing edge that just 1 second timing signal T_1s and timing signal T_1s_r_n produce local count enable signal Cnt_ena_local:1 timing signal second T_1s comes temporarily that just this signal is low level " 0 " by high level " 1 " saltus step, local count enable signal Cnt_ena_local is low level " 0 " by high level " 1 " saltus step, and keep low level always, up to the trailing edge of timing signal T_1s_r_n when just this signal is low level " 0 " by high level " 1 " saltus step, local count enable signal Cnt_era_local is high level " 1 " by low level " 0 " saltus step, keep high level " 1 " to arrive simultaneously up to the next trailing edge of 1 second timing signal T_1s, repeat foregoing saltus step again, can generate local count enable signal Cnt_ena_local;
The 3rd, after count enable signal clock zone conversion processing unit is received count enable signal Cnt_ena_local, this signal is transformed into the measured clock territory and is generated measured clock count enable signal Cnt_ena_check by the local clock territory, and by measured clock count enable signal triggering measured clock counter O reset signal Cnt_clr_check, be that local count enable signal Cnt_ena_local latchs through measured clock signal Clk_freq_checked, latch two bat outputs, produce the measured clock count enable signal Cnt_ena_check_n that conversion is come; The measured clock count enable signal Cnt_ena_check_n that conversion is come is latched once more, and the time of latching is two bats of measured clock signal, just two of the measured clock signal clock cycle; Obtain measured clock count enable signal Cnt_ena_check; When just this signal jumped to high level " 1 " by low level " 0 " when the rising edge of measured clock count enable signal Cnt_ena_check came, trigger measured clock counting reset signal Cnt_clr_check and jump to " 1 " by low level " 0 ";
The 4th, count detection unit, measured clock territory receives measured clock counter O reset signal Cnt_clr_check, begins counting; In measured clock count enable signal Cnt_ena_check limiting time, the measured clock counting finishes, that is to say, when measured clock reset signal Cnt_clr_check trailing edge comes, when just Cnt_clr_check jumped to " 0 " by high level " 1 ", flip-flop number Cnt_check began counting; When the trailing edge of measured clock count enable signal Cnt_ena_check arrived, when just Cnt_ena_check jumped to " 0 " by high level " 1 ", counter Cnt_check finished counting;
At last, the count results discriminating unit is extracted count results and count results is differentiated under the common qualification of timing signal T_1s_r_n and local clock signal, obtains the measured clock index signal freq_chk_result whether compliance with system requires; That is: when the trailing edge of local timing signal T_1s_r_n comes, can guarantee that described count results is stable, on this basis, extract counter Cnt_check count results, determine the frequency of measured clock; Count results and preset range are compared, if count results is in preset range, then represent the requirement of measured clock compliance with system, otherwise the expression measured clock does not meet system requirements, thereby obtain the measured clock index signal freq_chk_result whether compliance with system requires.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (10)
1, a kind of method of clock detection is characterized in that, this method comprises the following steps:
A, local count enable signal produce the measured clock count enable signal through the measured clock signal latch, trigger the measured clock counter, and the clock cycle quantity that measured clock was dropped in the set time begins counting;
B, finish the clock cycle quantity counting in the set time after, extract described count results, realize detection according to this result at the frequency of measured clock.
2, clock detection method according to claim 1 is characterized in that, described steps A also comprises:
A1, according to the local count enable signal of local clock signal actuation counter and timing signal for generating, the value of described set time is limited by described measured clock count enable signal.
3, clock detection method according to claim 1 is characterized in that, described steps A comprises:
Generate measured clock counter O reset signal by the measured clock count enable signal;
Measured clock counter O reset signal triggering measured clock counter;
The measured clock counter receives the measured clock count enable signal and triggers, and measured clock is dropped on the quantity of the clock cycle in the described set time and counts.
4, according to claim 1 or 2 or 3 described clock detection methods, it is characterized in that described step B comprises: the clock cycle quantity counting in the set time finishes, described count results is stable promptly keep count results constant after, extract described count results.
5, according to claim 1 or 2 or 3 described clock detection methods, it is characterized in that described step B comprises:
After B1 extracts count results, the count results of measured clock counter is compared with the predetermined range of determining based on the desired value of measured clock frequency,, then determine the requirement of measured clock compliance with system if count results meets pre-provisioning request; Otherwise, determine that measured clock does not meet system requirements.
6, clock detection method according to claim 5 is characterized in that, described step B1 also comprises:
The count results of measured clock counter determines that the measured clock frequency meets predetermined requirement within the predetermined range of determining according to the desired value of the measured clock frequency of expectation; Otherwise, determine that the measured clock frequency does not meet predetermined requirement.
7, clock detection method according to claim 1 is characterized in that, also comprises before described steps A: the reference clock by measured clock detects measured clock, and when confirming that measured clock meets the initial survey requirement, carries out described steps A.
8, a kind of device of clock detection is characterized in that, comprising:
The processing unit of count enable signal clock zone conversion: be used for local count enable signal process measured clock signal latch is generated the measured clock count enable signal;
Timing control unit: be used to utilize measured clock count enable signal control count detection unit, measured clock territory in the set time, to count, and control count results discriminating unit is extracted count results;
Count detection unit, measured clock territory: be used in the set time clock cycle quantity and count to the measured clock territory;
Count results discriminating unit: be used for extracting, and differentiate the measured clock count results, determine testing result at measured clock at the measured clock count results.
9, clock detecting device according to claim 8 is characterized in that, described device also comprises:
The generation unit of count enable signal: be used for producing local count enable signal according to the local timing signal that local clock and timing control unit generated based on the set time.
10, clock detecting device according to claim 8, it is characterized in that, the processing unit of described count enable signal clock zone conversion is used for local count enable signal is transformed into the measured clock territory from clock zone, and generation measured clock count enable signal and measured clock counting reset signal, described timing control unit is used to utilize measured clock counting reset signal control count detection unit, measured clock territory to begin counting, utilizes measured clock count enable signal control count detection unit, measured clock territory to finish counting.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101093155A CN100512007C (en) | 2006-08-08 | 2006-08-08 | Method and device for clock detection |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101093155A CN100512007C (en) | 2006-08-08 | 2006-08-08 | Method and device for clock detection |
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| CN1925329A CN1925329A (en) | 2007-03-07 |
| CN100512007C true CN100512007C (en) | 2009-07-08 |
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| CNB2006101093155A Expired - Fee Related CN100512007C (en) | 2006-08-08 | 2006-08-08 | Method and device for clock detection |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394244B (en) * | 2007-09-17 | 2011-10-26 | 中兴通讯股份有限公司 | Non-homogeneous time clock region frame synchronization signal generating method in time division base station system |
| CN101227205B (en) * | 2008-01-29 | 2012-07-04 | 中兴通讯股份有限公司 | Clock detection method for wireless communication system |
| CN101252405B (en) * | 2008-03-27 | 2012-09-05 | 华为技术有限公司 | Clock detection and auto switching method and system |
| JP5922494B2 (en) * | 2012-05-24 | 2016-05-24 | 横河電機株式会社 | Physical quantity measuring device, physical quantity measuring method |
| CN103365757B (en) * | 2013-07-29 | 2016-02-17 | 浙江中控技术股份有限公司 | Clock detection method and device |
| CN103728516B (en) * | 2014-01-09 | 2016-05-11 | 福州瑞芯微电子股份有限公司 | Soc chip clock detection circuit |
| CN109426300A (en) * | 2017-08-30 | 2019-03-05 | 比亚迪股份有限公司 | Clock jitter detection method and device for system on chip |
| CN111083940A (en) * | 2018-08-21 | 2020-04-28 | 深圳市汇顶科技股份有限公司 | Detection circuit, method, chip and equipment |
| CN111446960B (en) * | 2020-04-16 | 2023-05-12 | 浙江大华技术股份有限公司 | Clock output circuit |
| CN112230710B (en) * | 2020-10-10 | 2022-07-08 | 烽火通信科技股份有限公司 | Method and device for carrying out clock counting on any clock frequency |
| CN114625208A (en) * | 2020-12-10 | 2022-06-14 | 炬芯科技股份有限公司 | Clock circuit and bluetooth device |
| CN117110707B (en) * | 2023-10-24 | 2024-01-30 | 芯潮流(珠海)科技有限公司 | SOC integrated chip, frequency measurement circuit and frequency measurement method |
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