CN111083940A - Detection circuit, method, chip and equipment - Google Patents

Abstract

The application provides a detection circuit, a method, a chip and equipment, wherein the circuit comprises a synchronous module and a detection module connected with the synchronous circuit; the synchronization module synchronizes the clock domains of the enable signals and transmits the enable signals corresponding to the clock domains of each path of clock signals to the detection module; the detection module detects each path of clock signal under the action of the enabling signal to obtain the frequency of each path of clock signal. The method and the device can accurately detect the frequency of the clock signal and ensure information safety.

Description

Detection circuit, method, chip and equipment Technical Field

The embodiments of the present application relate to security technologies, and in particular, to a detection circuit, a detection method, a chip, and a device.

Background

With the continuous development of Internet Technology (IT), information security is more and more important.

Most of the chips of electronic devices have digital circuits integrated thereon, and for the digital circuits to work normally, one or a group of clocks with specific frequency are often required to drive internal registers. The clock is too fast or too slow, which may cause abnormal operation of the chip and cause data leakage.

It is particularly important how to accurately detect the frequency of the clock signal.

Disclosure of Invention

The embodiment of the application provides a detection circuit, a detection method, a chip and a device, which are used for detecting the frequency of a clock, ensuring the normal work of the chip, avoiding data leakage and improving data safety.

The embodiment of the application provides a detection circuit, includes:

a synchronization module and a detection module; the synchronization module is connected with the detection module;

the synchronization module is configured to synchronize the received enable signal to a clock domain of each clock signal according to each clock signal in multiple clock signals, so as to obtain an enable signal corresponding to the clock domain of each clock signal and transmit the enable signal to the detection module;

the detection module is configured to detect each path of clock signal under the action of an enable signal corresponding to a clock domain of each path of clock signal, so as to obtain a frequency of each path of clock signal.

An embodiment of the present application further provides a chip, including: the detection circuit is provided.

An embodiment of the present application further provides an electronic device, including: a chip, the chip comprising any of the above detection circuits.

The embodiment of the application also provides a detection method, which is suitable for a detection circuit, wherein the detection circuit comprises a synchronization module and a detection module; the method comprises the following steps:

the method comprises the following steps:

the synchronization module synchronizes the received enable signal to the clock domain of each clock signal according to each clock signal in the multiple clock signals, so as to obtain the enable signal corresponding to the clock domain of each clock signal and transmit the enable signal to the detection module;

and the detection module detects each path of clock signal under the action of an enabling signal corresponding to the clock domain of each path of clock signal to obtain the frequency of each path of clock signal.

The detection circuit, the detection method, the detection chip and the detection device provided by the embodiment of the application can comprise a synchronization module and a detection module connected with the synchronization module, and can synchronize a received enable signal to a clock domain of each clock signal according to each clock signal in a plurality of paths of clock signals through the synchronization module so as to obtain an enable signal corresponding to the clock domain of each clock signal and transmit the enable signal to the detection module; and detecting each path of clock signal under the action of an enabling signal corresponding to the clock domain of each path of clock signal through a detection module to obtain the frequency of each path of clock signal. According to the scheme, each path of clock signal can be detected based on the enable signal corresponding to the clock domain of each path of clock signal after synchronization, errors among different clock domains can be effectively avoided, the accuracy of frequency detection of the clock signal is guaranteed, data safety is effectively guaranteed, and data leakage is avoided.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a block diagram of a detection circuit according to an embodiment of the present disclosure;

fig. 2 is another block diagram of a detection circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic block diagram of a detection circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic block diagram of a detection circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit structure diagram of a detection circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a response synchronization circuit for the detection circuit shown in FIG. 5 according to an embodiment of the present disclosure;

FIG. 7 is a diagram illustrating a state machine of a detection circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 10 is a flowchart of a detection method according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The detection circuit, method, chip and device provided by the following embodiments of the present application can be applied to an electronic device having a digital circuit for detecting the frequency of a clock signal.

The following describes a detection circuit, a method, a chip and an apparatus provided by the embodiments of the present application through a plurality of examples.

Fig. 1 is a block diagram of a detection circuit according to an embodiment of the present disclosure. The detection circuit can be applied to electronic equipment with digital circuits. As shown in fig. 1, the detection circuit may include: a synchronization module 11 and a detection module 12. The synchronization module 11 is connected to the detection module 12.

The synchronization module 11 is configured to synchronize the received enable signal to a clock domain of each of the multiple clock signals according to each of the multiple clock signals, so as to obtain an enable signal corresponding to the clock domain of each of the multiple clock signals, and transmit the enable signal to the detection module 12.

The detecting module 12 is configured to detect each path of clock signal under the action of an enable signal corresponding to a clock domain of each path of clock signal, so as to obtain a frequency of each path of clock signal.

Specifically, in the detection circuit, an input terminal of the synchronization module 11 may be connected to output terminals of a plurality of clock circuits (not shown) for receiving a plurality of clock signals output by the plurality of clock circuits. The synchronization module 11 may have a plurality of input terminals, and each input terminal of the synchronization module 11 may be connected to an output terminal of one clock circuit, so that each input terminal may receive one clock signal transmitted by one clock circuit.

The enable terminal of the synchronization module 11 is further connected to the output terminal of the enable module for receiving the enable signal output by the enable module.

Optionally, a plurality of traces for transmitting the enable signal exist between the synchronization module 11 and the enable module.

That is to say, at least two wires (i.e. a plurality of wires) exist between the enable end of the synchronous module 11 and the output end of the enable module, and the other wires except the current transmission wire among the at least two wires may be called redundant wires. Each of the at least two wires may be used to transmit the enable signal.

If only one trace for transmitting the enable signal is provided, once an attack, such as a Focused Ion Beam (FIB) attack, is applied, the enable signal transmitted on the trace is tampered with, and the whole circuit is threatened. Because in the detection circuit in this application, there are at least two lines between the synchronization module 11 and the enable module to be used for transmitting the enable signal, even if one of the lines transmitting the enable signal is attacked, as long as another line is not attacked, the enable signal can be accurately transmitted to the synchronization module 11, and the risk caused by the attack of the enable signal can be avoided.

In order to ensure the accuracy of the enable signal transmitted to the synchronization module 11, an OR (OR) gate may be further connected between the at least two traces and the enable end of the synchronization module 11, and the OR gate processes the enable signal transmitted by the at least two traces and transmits the processed enable signal to the enable end of the synchronization module 11.

Optionally, the at least two wires for transmitting the enable signal are low-layer metal wires in the chip. The upper layer of the lower layer metal wire is covered with at least one layer of metal, namely at least two wires for transmitting the enabling signals are positioned at the lower layer of the multi-layer metal wire structure, wherein the lower layer metal wire is far away from the surface of the chip relative to the upper layer metal wire.

At least one layer of metal covered by the upper layer of the low-layer metal wiring, and the uppermost layer is an Active Shielding layer (Active Shielding) for protecting the whole multilayer metal wiring and preventing the multilayer metal wiring from being attacked.

Because the upper layer of the low-layer metal wire is covered with the metal layer, at least two wires for transmitting the enable signal adopt the low-layer metal wire on the chip, and the attack risk of the wires for transmitting the enable signal can be effectively reduced.

Each clock signal has a respective clock domain, and the same enable signal acts on different clock domains, and the effective time of the enable may be different. Therefore, in the present application, the synchronization module 11 may synchronize the enable signal to the clock domain of each clock signal, so as to obtain the synchronized enable signal corresponding to the clock domain of each clock signal, and transmit the synchronized enable signal to the detection module 12, so as to trigger the detection module 12 to detect the clock signal.

The output end of the synchronization module 11 may be connected to the enable end of the detection module 12, so as to transmit the enable signal corresponding to the clock domain of each clock signal after synchronization to the enable end of the detection module 12.

The detecting module 12 can detect each path of clock signal under the action of the enable signal corresponding to the clock domain of each path of clock signal and under the condition that the enable signal is valid, so as to obtain the frequency of each path of clock signal.

In this application, the enable signal used by the detection module 12 is the synchronized enable signal corresponding to the clock domains of the plurality of clock signals, so that the valid times of the enable signals corresponding to the clock domains of the plurality of clock signals are synchronized. Then, under the effect of the enable signal corresponding to the clock domain of each path of clock signal, it can be ensured that the detection module 12 can simultaneously detect each path of clock signal, so as to ensure the accuracy of the frequency of each path of signal.

The detection circuit provided by the embodiment of the application comprises a synchronization module and a detection module connected with the synchronization module, wherein an enable signal can be synchronized to a clock domain of each path of clock signal through the synchronization module according to each path of clock signal in a plurality of paths of clock signals, and the obtained enable signal corresponding to the clock domain of each path of clock signal is transmitted to the detection module; and detecting each path of clock signal under the action of an enabling signal corresponding to the clock domain of each path of clock signal through a detection module to obtain the frequency of each path of clock signal. According to the scheme, each path of clock signal can be detected based on the enable signal corresponding to the clock domain of each path of clock signal after synchronization, errors among different clock domains can be effectively avoided, the accuracy of frequency detection of the clock signal is guaranteed, data safety is effectively guaranteed, and data leakage is avoided.

The embodiment of the application also provides a detection circuit. The detection circuit can exemplify the detection module 12 in the detection circuit on the basis of the above. Fig. 2 is another block diagram of a detection circuit according to an embodiment of the present disclosure. As shown in fig. 2, in the detection circuit, the detection module 12 may include: a plurality of counters 121. Each counter 121 may correspond to one of the plurality of clock signals. The synchronization module 11 is connected to each counter 121.

The synchronization module 11 is specifically configured to transmit the enable signal corresponding to the clock domain of each clock signal to the counter 121 corresponding to each clock signal.

The counter 121 corresponding to each path of clock signal is used for counting the rising edge or the falling edge of the path of clock signal under the action of the enable signal corresponding to the clock domain of the path of clock signal to obtain a count value corresponding to the path of clock signal; the count value corresponding to the path of clock signal is used for representing the frequency of the path of clock signal.

Specifically, the output end of the synchronization module 11 may be connected to an Enable (EN) end of each counter 121, so as to transmit an Enable signal corresponding to the clock domain of each clock signal to the counter 121 corresponding to each clock signal.

The counter 121 corresponding to each clock signal is further connected to the clock circuit corresponding to each clock signal for receiving the clock signal transmitted by the clock circuit corresponding to the clock signal. For example, the input end of the counter 121 corresponding to the first clock signal may be connected to the output end of the clock circuit corresponding to the first clock signal, the input end of the counter 121 corresponding to the second clock signal may be connected to the output end of the clock circuit corresponding to the second clock signal, and so on. The input terminal of the counter 121 may be a Clock Pulse (CP) terminal of the counter 121.

The counter 121 corresponding to each clock signal starts to count the rising edge or the falling edge of the clock signal under the action of the enable signal corresponding to the clock domain of the clock signal.

On the basis of the embodiment, the detection circuit counts the rising edge or the falling edge of the clock signal through the counter, so that the frequency of the clock signal is detected, and the detection accuracy of the frequency of the clock signal is effectively ensured.

The embodiment of the application also provides a detection circuit. The detection circuit can exemplify the detection module 12 in the detection circuit on the basis of the above. Fig. 3 is a schematic block diagram of a detection circuit according to an embodiment of the present disclosure. As shown in fig. 3, in the detection circuit, the plurality of counters 121 included in the detection module 12 may include: a counter 121 corresponding to the reference clock, and a counter 121' corresponding to at least one clock to be tested. The counter 121 corresponding to the reference clock is configured to receive a path of reference clock signal, and receive an enable signal corresponding to a clock domain of the path of reference clock signal output by the synchronization module 11; the counter 121' corresponding to the clock to be tested is configured to receive a path of clock signal to be tested, and receive an enable signal corresponding to the clock domain of the path of clock signal to be tested, which is output by the synchronization module 11. The counter 121 corresponding to the reference clock is connected with the counter 121' corresponding to the clock to be measured.

The counter 121 corresponding to the reference clock is configured to transmit a first control signal to the counter' corresponding to the clock to be tested when the value of the counter corresponding to the reference clock reaches a preset value.

And each counter 121' corresponding to the clock to be tested is used for stopping counting according to the first control signal.

Specifically, the preset value may be a maximum count value of the counter 121 corresponding to the reference clock, and may also be referred to as a preset full count value of the counter 121 corresponding to the reference clock. The preset value can be fixed in the circuit in advance or can be modified by programming.

When the count value of the counter 121 corresponding to the reference clock reaches a predetermined value, the first control signal, such as a full signal, is output to the counter 121' corresponding to each clock to be tested, wherein the full signal is active high.

The output end of the counter 121 corresponding to the reference clock may be connected to the enable end of the counter 121 'corresponding to each clock to be tested, so as to control the counter 121' corresponding to the clock to be tested to stop counting. In order to ensure that the counter 121 'corresponding to the clock to be tested can count normally before the count value of the counter 121 corresponding to the reference clock reaches the preset value, an inverter may be connected between the output terminal of the counter 121 corresponding to the reference clock and the enable terminal of the counter 121' corresponding to the clock to be tested. The preset count value may be represented as CNT _ REF _ NUM, for example.

Optionally, the detection module 12 further includes: a comparison circuit 122. The comparison circuit 122 is connected to the counter 121' corresponding to the clock to be measured.

And the comparison circuit 122 is configured to compare a count value of the counter 121' corresponding to the clock to be measured when the counting is stopped with a preset upper count limit value and/or a preset lower count limit value, so as to obtain a comparison result.

The input terminal of the comparison circuit 122 is connected to the output terminal, such as the Q port, of the counter 121 'corresponding to the clock to be tested, and is used for receiving the count value of the counter 121' corresponding to each clock to be tested when the counting is stopped.

The count value of the counter 121' corresponding to each clock to be measured when stopping counting can be represented as CNT _ TEST _ NUM. The preset upper limit count value may be denoted as HB, and the preset lower limit count value may be denoted as LB.

The preset upper limit value HB and the preset lower limit value LB may be controlled by programming the error margin δ and the theoretical count value c, where LB is c- δ and HB is c + δ. Therefore, errors caused by processes and the like can be offset, false alarm is prevented, and the method is flexible and controllable. The theoretical count value c may have a preset corresponding relationship with a full count value of a counter corresponding to the reference clock, for example, the preset value.

Optionally, the comparison circuit 122 may also be connected to a counter 121 corresponding to the reference clock.

The comparing circuit 122 is further configured to output a second control signal to the counter 121 corresponding to the reference clock and the counter 121' corresponding to the clock to be tested under a predetermined condition. The predetermined condition may be: the count value of the counter 121' corresponding to the clock to be measured when the counting is stopped is smaller than the preset upper limit value of the counting and larger than the preset lower limit value of the counting.

And the counter 121' corresponding to the clock to be tested and the counter 121 corresponding to the reference clock are used for initializing according to the second control signal.

Specifically, if the count value of the counter 121' corresponding to the clock to be tested when stopping counting is smaller than the preset upper limit value of counting and larger than the preset lower limit value of counting, the frequency of the clock signal of the clock to be tested is within the preset range, it can be determined that the clock signal of the clock to be tested is not attacked, the comparison circuit 122 outputs a second control signal to control the counter 121' corresponding to the clock to be tested and the counter 121 corresponding to the reference clock to initialize, so that the counter 121' corresponding to the clock to be tested counts the rising edge or the falling edge of the clock signal of the clock to be tested again, so as to perform frequency detection on the clock signal of the clock to be detected again, so that the counter 121 corresponding to the reference clock counts the rising edge or the falling edge of the clock signal of the reference clock again, so as to perform frequency detection on the clock signal of the reference clock again.

The second control signal may be, for example, a clear signal, and after receiving the second control signal, the counter 121' corresponding to the clock to be measured and the counter 121 corresponding to the reference clock may initialize the count value according to the second control signal, for example, clear the count value or restore the count value to a preset initial value.

The output terminal of the comparing circuit 122 is further connected to an initialization port, such as a Clear (CLR) port, of the counter 121 'corresponding to the clock to be tested, for transmitting the second control signal to the counter 121' corresponding to the clock to be tested. The output terminal of the comparing circuit 122 is further connected to an initialization port, such as a Clear (CLR) port, of the counter 121 corresponding to the reference clock, for transmitting the second control signal to the counter 121 corresponding to the reference clock.

In order to enable the counter 121 ' corresponding to the clock to be tested and the counter 121 corresponding to the reference clock to be initialized at the same time under the action of the second control signal, a synchronization module is further disposed between the comparison circuit 122 and the counter 121 ' corresponding to the clock to be tested, and is configured to synchronize the second control signal according to the clock signal of the clock to be tested, obtain the second control signal corresponding to the clock domain of each synchronized clock signal, and transmit the second control signal corresponding to the clock domain of the clock to be tested to the counter 121 ' corresponding to the clock to be tested. A synchronization module is further disposed between the comparison circuit 122 and the counter 121 corresponding to the reference clock, and configured to synchronize the second control signal according to the clock signal of the reference clock, obtain the second control signal corresponding to the clock domain of the synchronized clock signal of the reference clock, and transmit the second control signal corresponding to the clock domain of the clock signal of the reference clock to the counter 121 corresponding to the reference clock.

The counter 121' corresponding to the comparison circuit 122 and the clock to be tested, and the synchronization module between the comparison circuit 122 and each counter 121 corresponding to the reference clock may be similar to the synchronization module shown in fig. 1, which is referred to above and will not be described herein again.

In the detection circuit, the reference clock and the clock to be detected are independent respectively, the corresponding counters are independent respectively, the frequency and/or the phase of the reference clock and the frequency and/or the phase of the clock to be detected are not in corresponding relation, and constraint relation does not exist, so that the frequency detection inaccuracy of the clock to be detected caused by the attack of the reference clock can be effectively avoided, and the frequency detection accuracy of the clock signal is improved. In addition, in the detection circuit, the count value of the counter of the clock to be detected has an upper limit value and a lower limit value, namely the count value of the counter of the clock to be detected has a certain tolerance range, so that the frequency of the clock to be detected can have a certain tolerance range, errors caused by clock jitter, clock skew or other processes can be effectively avoided, and the precision is flexible and controllable.

The embodiment of the application also provides a detection circuit. The detection circuit is further described with reference to fig. 3. Fig. 4 is a schematic block diagram of a detection circuit according to an embodiment of the present disclosure. As shown in fig. 4, on the basis of fig. 3, a response module 13 may be further included in the detection circuit. The response module 13 is connected to the comparison circuit 122.

The comparison circuit 122 is further configured to output a third control signal to the response module 13 under a predetermined condition. The predetermined condition may be: the count value of the counter 121' corresponding to the clock to be measured when the counting is stopped is greater than or equal to the preset upper counting limit value, or the count value is less than or equal to the preset lower counting limit value.

And a response module 13, configured to output any one of an interrupt signal, an erase signal, or a reset signal according to the third control signal.

Specifically, if the count value of the counter 121' corresponding to the clock to be tested when the counting is stopped is greater than or equal to the preset upper limit count value, or the count value is less than or equal to the preset lower limit count value, the frequency of the clock signal of the clock to be tested exceeds the preset range, it can be determined that the clock signal of the clock to be tested is possibly attacked, and the comparison circuit 122 outputs a third control signal to control the response module 13 to output any one of an interrupt signal, an erase signal or a reset signal, so as to avoid information leakage.

An output of the comparing module 122 may be connected to an input of the response module 13, so as to output the third control signal to the response module 13. The response module 13 may be an alarm response circuit and the third control signal may be an alarm signal.

After receiving the third control signal, the response module 13 outputs a response signal according to the third control signal, such as outputting any one of a status flag, an interrupt signal, an erasure signal, such as a sensitive information erasure signal, or a reset signal, so as to avoid information leakage.

Optionally, at least two traces, i.e., a plurality of traces, for transmitting the third control signal are connected between the comparing circuit 122 and the response module 13.

That is to say, at least two traces exist between the output end of the comparing circuit 122 and the input end of the response module 13, and the other traces except the current transmission trace in the at least two traces may be referred to as redundant traces. Each of the at least two traces may be configured to transmit the third control signal.

If only one trace for transmitting the third control signal is provided, the third control signal transmitted on the trace can be tampered by an attack, such as FIB attack, and the whole circuit can be threatened. In the detection circuit in the present application, at least two traces exist between the comparison circuit 122 and the response module 13 for transmitting the third control signal, so that even if one trace transmitting the third control signal is attacked, as long as another trace can transmit the third control signal accurately without being attacked, the third control signal can be accurately transmitted to the response module 13, and the risk caused by the attack of the third control signal can be avoided.

In order to ensure the accuracy of the third control signal transmitted to the response module 13, an OR (OR) gate may be further connected between the at least two traces and the input terminal of the response module 13, and the OR gate processes the third control signal transmitted by the at least two traces and then transmits the processed third control signal to the input terminal of the response module 13.

Optionally, the at least two wires for transmitting the third control signal are lower-layer metal wires of the chip; the upper layer of the lower layer metal routing is covered with at least one layer of metal, namely at least two routing for transmitting the enabling signal are positioned at the lower layer of the multi-layer metal routing structure, wherein the lower layer metal routing is far away from the surface of the chip relative to the upper layer metal routing.

The upper layer of the metal layer is an active protective layer for protecting the whole multilayer metal wire and preventing the multilayer metal wire from being attacked.

Because the upper layer of the surface of the lower layer wire is provided with other wires, at least two wires for transmitting the third control signal adopt the lower layer wire on the chip, and the attack risk of the wire for transmitting the third control signal can be effectively reduced.

Fig. 5 is a schematic circuit structure diagram of the detection circuit according to the embodiment of the present application. As shown in fig. 5, the detection circuit may be one possible example of the detection circuit described above in any of fig. 1 to 4. As shown in fig. 5, the detection circuit may include: an enable protection circuit 50, an enable synchronization circuit 51, a counter circuit 52, a comparator circuit 53, a response protection circuit 54, and a response circuit 55.

Among other things, the enable protection circuit 50 may include a first OR gate (OR 1).

The synchronization module 11 may comprise, for example, an enable synchronization circuit 51 as shown in fig. 5. In fig. 5, the enable synchronization circuit 51 includes a flip-flop corresponding to the reference clock, a flip-flop corresponding to the clock to be tested, a first AND gate (AND1), AND a second AND gate (AND 2). The flip-flop corresponding to the reference clock comprises: flip-flop D1, flip-flop D2, flip-flop D5, and flip-flop D6. The trigger corresponding to the clock to be tested comprises: flip-flop D3, flip-flop D4, flip-flop D7, flip-flop D8.

The detection module 12 may include, for example, a counting circuit 52 as shown in fig. 5. The counting circuit 52 shown in fig. 5 includes: counter 1 and counter 2. The counter 121 corresponding to the reference clock may be the counter 1 in fig. 5, and the counter 121' corresponding to the clock to be measured may be the counter 2.

The comparison circuit 122 may be the same as or different from the comparison circuit 53 shown in fig. 5. The comparison circuit 122 or the comparison circuit 53 may be a comparator, for example.

The response protection circuit 54 may include a second OR gate (OR 2).

The response module 13 may include, for example, a response circuit 55 shown in fig. 5.

In the detection circuit shown in fig. 5, the enable protection circuit 50 may receive enable signals transmitted through a plurality of wires, process the enable signals through the first OR gate OR1, and output the processed enable signals to the enable synchronization circuit 51, that is, output a plurality of enable signals to the enable synchronization circuit 51 alternatively. Specifically, the enable signal is output to the D port corresponding to the flip-flop D1 and the flip-flop D3. The enable signals transmitted on the plurality of wires may be n groups of enable signals, which may be denoted as en _1, en _2 …, en _ n, for example. n is an integer greater than 1. The n groups of transmission traces of the enable signals and the output trace of the first OR gate OR1 may be disposed on a lower metal trace layer in the multi-layer metal trace chip.

The clock signal clk _ ref of the reference clock is input to the flip-flops D1, D2, D5 and D6 corresponding to the reference clock in the enable synchronizing circuit 51. The clock signal of the reference clock may also be input to the CP terminal of the counter 1.

The clock signal clk _ test of the clock to be tested is input to the flip-flops corresponding to the clock to be tested in the enable synchronizing circuit 51, namely the flip-flop D3, the flip-flop D4, the flip-flop D7 and the flip-flop D8. The clock signal of the clock to be tested is input to the CP terminal of the counter 2.

The flip-flop D1 is connected to the flip-flop D2. The flip-flop D1 is used for processing the enable signal under the action of the clock signal of the reference clock, and outputting a signal to the flip-flop D2. The flip-flop D1 may transmit the output signal of the flip-flop D1 to the D port of the flip-flop D2 through the Q port.

The flip-flop D2 is further connected to the flip-flop D7 AND the first AND gate AND1, AND the flip-flop D2 is configured to process the output signal of the flip-flop D1 under the action of the clock signal of the reference clock AND output the signal to the flip-flop D7 AND the first AND gate AND 1. The flip-flop D2 may transmit the output signal of the flip-flop D2 through the Q port to the D port of the flip-flop D7 AND the first AND gate AND 1.

The flip-flop D3 is connected to the flip-flop D4. The flip-flop D3 is used for processing the enable signal under the action of the clock signal of the clock to be tested, and outputting a signal to the flip-flop D4. The flip-flop D3 may transmit the output signal of the flip-flop D3 to the D port of the flip-flop D4 through the Q port.

Flip-flop D4 is also connected to flip-flop D5 AND to a second AND gate AND 2. The flip-flop D4 is configured to process an output signal of the flip-flop D3 under the action of a clock signal of the clock to be tested, AND output the signal to the flip-flop D5 AND the second AND gate AND 2. The flip-flop D4 may transmit the output signal of the flip-flop D4 through the Q port to the D port of the flip-flop D5 AND to the second AND gate AND 2.

The flip-flop D5 is configured to process the output signal of the flip-flop D4 under the action of the clock signal of the reference clock, and output the signal to the flip-flop D6. The flip-flop D5 may transmit the output signal of the flip-flop D5 to the D port of the flip-flop D6 through the Q port.

The flip-flop D6 is configured to process the output signal of the flip-flop D5 under the action of the clock signal of the reference clock, AND output the signal to the first AND gate AND 1. The flip-flop D6 may transmit the output signal of the flip-flop D6 to the first AND gate AND1 through the Q port.

The flip-flop D7 is configured to process the output signal of the flip-flop D2 under the action of the clock signal of the clock to be tested, and output the signal to the flip-flop D8. The flip-flop D7 may transmit the output signal of the flip-flop D7 to the D port of the flip-flop D8 through the Q port.

AND the flip-flop D8 is configured to process the output signal of the flip-flop D7 under the action of the clock signal of the clock to be tested, AND output the signal to the second AND gate AND 2. The flip-flop D8 may transmit the output signal of the flip-flop D8 to the second AND gate AND2 through the Q port.

The first AND gate AND1 is used to AND the output signal of the flip-flop D2 AND the output signal of the flip-flop D6, AND output the signals to the counter corresponding to the reference clock, i.e., the counter 1. The output signal of the first AND gate AND1 may be output to the Enable (EN) terminal of the counter 1, triggering the counter 1 to start counting the rising or falling edges of the clock signal of the reference clock. The signal after the AND logic processing by the first AND gate AND1 is the enable signal of the clock domain corresponding to the clock signal of the reference clock after the synchronization processing.

The second AND gate AND2 is used for performing AND logic processing on the signal output by the flip-flop D4 AND the signal output by the flip-flop D8, AND outputting a signal corresponding to the clock to be tested, that is, the counter 2. The output signal of the second AND gate AND2 is sent to the Enable (EN) terminal of the counter 2, which triggers the counter 2 to start counting the rising or falling edges of the clock signal of the clock to be measured. The signal after the AND logic processing by the second AND gate AND2 is the enable signal of the clock domain corresponding to the clock signal of the clock to be measured after the synchronization processing.

The count value of the counter 1 can be used to characterize the frequency of the clock signal of the reference clock, and the count value of the counter 2 can be used to characterize the frequency of the clock signal of the clock to be tested.

Optionally, the enable synchronization circuit 51 as shown above further includes: an inverter. The multiple triggers that the clock to be measured corresponds to still include: flip-flop D9 and flip-flop D10.

The inverters are respectively connected to the counter 1 corresponding to the reference clock, the first AND gate AND1, AND the flip-flop D10. AND the inverter is used for inverting the output signal of the counter 1 AND outputting the signal to the first AND gate AND1 AND the flip-flop D10. The output signal of the counter 1 may for example comprise: the signal output from the full value (full) port of the counter 1.

The first AND gate AND1 is specifically configured to perform AND logic processing on the output signal of the flip-flop D2, the output signal of the flip-flop D6, AND the output signal of the inverter, AND output the signals to the counter D1.

The flip-flop D9 is connected to the flip-flop D10 AND the second AND gate AND2, respectively, AND the flip-flop D10 is configured to process the clock signal of the clock to be tested under the action of the output signal of the inverter, AND output the signal to the flip-flop D9.

The flip-flop D9 is configured to process the clock signal of the clock to be tested under the action of the output signal of the D10 flip-flop, AND output the signal to the second AND gate AND 2.

The second AND gate AND2 is specifically configured to AND the output signal of the flip-flop D4, the output signal of the flip-flop D8, AND the output signal of the flip-flop D9, AND output the signals to the counter 2.

When the count value of the counter 1 reaches a preset value, a full signal output from a full port of the counter 1 is transmitted to an inverter, AND after the full signal is inverted by the inverter, the full signal is output to the first AND gate AND1, so that the output signal of the first AND gate AND1 is disabled, that is, the enable signal of the clock domain corresponding to the clock signal of the reference clock is disabled, AND the counter 1 is controlled to stop counting.

Meanwhile, when the count value of the counter 1 reaches a preset value, a full signal output by a full port of the counter 1 is transmitted to the inverter, is subjected to inversion processing by the inverter, is sequentially processed by the flip-flop D10 AND the flip-flop D9, AND is output to the second AND gate AND2 by the flip-flop D9, so that the output signal of the second AND gate AND2 is disabled, that is, the enable signal of the clock domain corresponding to the clock signal of the clock to be tested is disabled, AND the counter 2 is controlled to stop counting.

After the counter 2 stops counting, the count value of the counter 2 is transmitted to the comparison circuit 53 through the Q port of the counter 2.

The comparison circuit 53 compares the count value after the counter 2 stops counting with a preset upper count limit value and/or a preset lower count limit value, and obtains a comparison result.

If the comparison result is that the count value after the counter 2 stops counting is smaller than the preset upper limit value of counting and the count value is greater than the preset lower limit value of counting, the comparison circuit 53 outputs a clear signal to the CLR ports of the counter 1 and the counter 2 to clear the count value by the counter 1 and the counter 2, thereby realizing the initialization of counting.

If the comparison result is that the count value after the counter 2 stops counting is greater than OR equal to the preset upper count limit value, OR the count value is less than OR equal to the preset lower count limit value, the comparison circuit 53 may transmit an alarm signal to the second OR gate OR2 through at least two wires, perform an OR logic process by the second OR gate OR2, and output a signal to the response circuit 55, so that the response circuit 55 outputs any one of signals such as an interrupt signal, an erase signal, OR a reset signal. The alarm signals transmitted on the at least two wires can be m groups of alarm signals, and can be represented as war _1, war _2 … and war _ m. m is an integer greater than 1. The transmission wires of the m groups of alarm signals and the output wires of the second OR gate OR2 can adopt low-level metal wires.

Fig. 6 is a schematic diagram of a response synchronization circuit for the detection circuit shown in fig. 5 according to an embodiment of the present disclosure. As shown in fig. 6, the detection circuit further includes, for detection by the detection circuit shown in fig. 5: a response synchronization circuit 56 connected between the comparison circuit 53 and the counting circuit 52.

The response synchronization circuit 56 includes: the trigger corresponding to the reference clock, the trigger corresponding to the clock to be tested, a third AND gate (AND3) AND a fourth AND gate (AND 4). The flip-flop corresponding to the reference clock may include: flip-flop D11, flip-flop D12, flip-flop D15, and flip-flop D16; the flip-flop corresponding to the clock to be tested may include: flip-flop D13, flip-flop D14, flip-flop D17, flip-flop D18.

The clock signal clk _ ref of the reference clock is input to the flip-flops corresponding to the reference clock in the response synchronizing circuit 56, i.e., the flip-flop D11, the flip-flop D12, the flip-flop D15, and the flip-flop D16.

The clock signal clk _ test of the clock to be tested is input to the flip-flops D13, D14, D17 and D18 corresponding to the clock to be tested in the response synchronization circuit 56.

If the count value after the stop of the counting of the counter 2 in fig. 5 is smaller than the preset upper limit value and the count value is larger than the preset lower limit value, the comparison circuit 53 outputs a clear signal clear to the response synchronization circuit 56. The response synchronization circuit 56 can synchronize the clear signal to the clock domain corresponding to the clock signal of the reference clock according to the clock signal of the reference clock, obtain the clear signal clear _ ref of the clock domain corresponding to the clock signal of the reference clock, and output a signal to the CLR port of the counter 1, so that the counter 1 clears the count value, thereby implementing the count initialization. The response circuit 56 may synchronize the clear signal to the clock domain corresponding to the clock signal of the clock to be tested according to the clock signal of the clock to be tested, obtain a clear signal clear _ test of the clock domain corresponding to the clock signal of the clock to be tested, and output a signal to the CLR port of the counter 2, so that the counter 2 clears the count value, thereby implementing count initialization.

Specifically, the comparator circuit 53 may input the clear signal clear to the D port of the flip-flop 11 and the D port of the flip-flop 13.

The clock signal of the reference clock is also input to the flip-flop D11, the flip-flop D12, the flip-flop D15, and the flip-flop 16. The clock signal of the clock to be tested is also input to the flip-flop D13, the flip-flop D14, the flip-flop D17, and the flip-flop 18.

The flip-flop D11 is connected to the flip-flop D12. The flip-flop D11 is used for processing the clear signal under the action of the clock signal of the reference clock, and outputting a signal to the flip-flop D12. The flip-flop D11 may transmit the output signal of the flip-flop D11 to the D port of the flip-flop D12 through the Q port.

The flip-flop D12 is further connected to a flip-flop D17 AND a third AND gate AND3, AND the flip-flop D1 is configured to process the output signal of the flip-flop D11 under the action of the clock signal of the reference clock, AND output the signal to the flip-flop D17 AND the third AND gate AND 3. The flip-flop D12 may transmit the output signal of the flip-flop D12 through the Q port to the D port of the flip-flop D17 AND to the third AND gate AND 3.

The flip-flop D13 is connected to the flip-flop D14. The flip-flop D13 is configured to process the clear signal under the action of the clock signal of the clock to be tested, and output a signal to the flip-flop D14. The flip-flop D13 may transmit the output signal of the flip-flop D13 to the D port of the flip-flop D14 through the Q port.

Flip-flop D14 is also connected to flip-flop D15 AND to a fourth AND gate AND 4. The flip-flop D4 is configured to process an output signal of the flip-flop D13 under the action of a clock signal of the clock to be tested, AND output the signal to the flip-flop D15 AND the fourth AND gate AND 4. The flip-flop D14 may transmit the output signal of the flip-flop 14 through the Q port to the D port of the flip-flop D15 AND the fourth AND gate AND 4.

The flip-flop D15 is configured to process the output signal of the flip-flop D14 under the action of the clock signal of the reference clock, and output the signal to the flip-flop D16. The flip-flop D15 may transmit the output signal of the flip-flop D15 to the D port of the flip-flop D16 through the Q port.

AND the flip-flop D16 is configured to process the output signal of the flip-flop D15 under the action of the clock signal of the reference clock, AND output the signal to the third AND gate AND 3. The flip-flop D16 may also transmit the output signal of the flip-flop D16 to the third AND gate AND3 through the Q port.

The flip-flop D17 is configured to process the output signal of the flip-flop D12 under the action of the clock signal of the clock to be tested, and output the signal to the flip-flop D18. The flip-flop D17 may transmit the output signal of the flip-flop D17 to the D port of the flip-flop D18 through the Q port.

AND the flip-flop D18 is configured to process the output signal of the flip-flop D17 under the action of the clock signal of the clock to be tested, AND output the signal to the fourth AND gate AND 4. The flip-flop D18 may transmit the output signal of the flip-flop D18 to the fourth AND gate AND4 through the Q port.

The third AND gate AND3 is used to AND the output signal of the flip-flop D12 AND the output signal of the flip-flop D16, AND output the signals to the counter corresponding to the reference clock, i.e., the counter 1. The output signal of the third AND gate AND3 may be output to the CLR port of the counter 1, so that the counter 1 clears the count value. The signal output by the third AND gate AND3 is the clear signal clear _ ref of the clock domain corresponding to the clock signal of the reference clock.

The fourth AND gate AND4 is configured to perform AND logic processing on the signal output by the flip-flop D14 AND the signal output by the flip-flop D18, AND output a signal to a counter corresponding to the clock to be tested, that is, the counter 2. The output signal of the fourth AND gate AND4 may be output to the CLR port of the counter 2 so that the counter 2 clears the count value. The signal output by the fourth AND gate AND4 is the clear signal clear _ test of the clock domain corresponding to the clock signal outputting the clock to be tested.

The detection circuit provided by the embodiment can realize accurate detection of clock signals, effectively ensure data safety and avoid data leakage; the reference clock and the clock to be detected are independent respectively, the corresponding counters are independent respectively, the frequency and/or the phase of the reference clock and the clock to be detected do not have a corresponding relation, and a constraint relation does not exist, so that the frequency detection inaccuracy of the clock to be detected caused by the attack of the reference clock can be effectively avoided, and the frequency detection accuracy of the clock signal is improved; the counting value of the counter of the clock to be tested has an upper limit value and a lower limit value, namely the counting value of the counter of the clock to be tested has a certain tolerance range, so that the frequency of the clock to be tested can have a certain tolerance range, errors caused by clock jitter, clock skew or other processes can be effectively avoided, and the precision is flexible and controllable. Meanwhile, the signal routing adopts low-layer metal routing, so that the attack difficulty is effectively increased, and the risk caused by the attack of the routing is effectively avoided. And the reliability of the frequency of the detected clock signal is ensured by multiple time delay comparison of the comparison result.

In order to make the detection circuit provided in the above embodiments of the present application operate orderly, the detection circuit may have a plurality of states, may represent a relationship between the plurality of states of the detection circuit, and may be represented as a state machine of the detection circuit. Fig. 7 is a schematic diagram of a state machine of a detection circuit according to an embodiment of the present disclosure. As shown in FIG. 7, the detection circuit includes an idle state, a count state, a compare state, a clear state and an error state.

The detection circuit is in an idle state, the detection circuit waits for an enable signal, and if the enable signal is valid, the detection circuit can enter a counting state.

In the counting state, when the counting value of the counter is not full, the counter counts the rising edge or the falling edge of the respective clock signal under the driving of the respective clock signal, and the counting value of the counter is increased by one at a rising edge or a falling edge. And if the counting value of the counter corresponding to the reference clock is full and the counter corresponding to the clock to be tested stops counting, the detection circuit enters a comparison state.

In a comparison state, the comparison module or the comparison circuit compares the count value of the counter corresponding to the clock to be tested after the counting is stopped with a preset upper counting limit and a preset lower counting limit to obtain a comparison result. And if the count value of the counter corresponding to the clock to be tested after the counting is stopped is smaller than the preset upper counting limit value and the count value is larger than the preset lower counting limit value, entering a zero clearing state. And if the count value of the counter corresponding to the clock to be tested after the counting is stopped is greater than or equal to the preset upper counting limit value, or the count value is less than or equal to the preset lower counting limit value, sending an alarm signal to enter an error state.

In the error state, the response circuit or the response module may output a different signal according to the third control signal, also called an alarm signal, output by the comparison circuit or the comparison module, thereby entering a different state. If the response circuit or the response module outputs the status flag bit or the interrupt signal, an error zero clearing signal can be sent out after relevant processing is carried out in the interrupt processing function, and the detection circuit enters a zero clearing state. If the response circuit or the response module outputs a reset signal, the detection circuit enters an idle state.

In the zero clearing state, the count value of the counter corresponding to the clock signal to be detected can be within a preset count range, and the detection circuit enters the count state again after the count value of the counter is cleared.

The embodiment of the application also provides a chip. Fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present application. As shown in fig. 8, the chip 80 may include: the detection circuit 81, and the detection circuit 81 may be the detection circuit shown in any one of fig. 1 to 6. The detection circuit is respectively connected with a plurality of clock circuits in the chip and is used for receiving a plurality of paths of clock signals generated by the clock circuits. Each clock circuit can generate one path of clock signal, and a plurality of clock circuits can generate a plurality of clock signals.

The chip comprises any one of the detection circuits, and the specific description and the beneficial effects thereof are referred to above, and are not described herein again.

The embodiment of the application also provides the electronic equipment. Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 9, the electronic device 90 may include: chip 91, chip 91 includes a detection circuit 92, and the detection circuit 92 may be the detection circuit shown in any one of fig. 1 to 6. The detection circuit 92 may be connected to a plurality of clock circuits on the chip 91, respectively, for receiving a plurality of clock signals generated by the plurality of clock circuits. Each clock circuit can generate one path of clock signal, and a plurality of clock circuits can generate a plurality of clock signals.

The chip included in the electronic device includes any one of the detection circuits described above, and the detailed description and the beneficial effects thereof are referred to above, and are not described herein again.

The embodiment of the application provides a detection method. The detection method is applicable to any one of the detection circuits described above, and is used for detecting the frequency of the clock signal. The detection circuit comprises a synchronization module and a detection module. Fig. 10 is a flowchart of a detection method according to an embodiment of the present application. As shown in fig. 10, the method may include:

and S1001, synchronizing the received enable signal to the clock domain of each path of clock signal by the synchronization module according to each path of clock signal in the multiple paths of clock signals to obtain the enable signal corresponding to the clock domain of each path of clock signal and transmitting the enable signal to the detection module.

S1002, the detection module detects each path of clock signal under the action of an enabling signal corresponding to the clock domain of each path of clock signal to obtain the frequency of each path of clock signal.

Optionally, the detection module includes: a plurality of counters; each counter corresponds to one clock signal in the multiple clock signals. In the above detection method, the transmitting the enable signal corresponding to the clock domain of each synchronized clock signal to the detection module in S1001 may include:

and the synchronization module transmits the enable signal corresponding to the clock domain of each path of clock signal to the counter corresponding to each path of signal.

Correspondingly, the detecting module in S1002 detects each path of clock signal under the action of the enable signal corresponding to the clock domain of each path of clock signal, and obtaining the frequency of each path of clock signal may include:

and the counter corresponding to each path of clock signal counts the rising edge or the falling edge of each path of clock signal under the action of the enable signal corresponding to the clock domain of each path of clock signal to obtain a count value corresponding to each path of clock signal, wherein the count value corresponding to each path of clock signal is used for representing the frequency of each path of clock signal.

Optionally, the counters include a counter corresponding to a reference clock and a counter corresponding to at least one clock to be measured; the detection module further comprises: a comparison circuit.

The method may further comprise:

when the count value of the counter corresponding to the reference clock reaches a first preset value, transmitting a first control signal to each counter;

each counter stops counting according to the first control signal.

Optionally, the detection module further includes: a comparison circuit.

The method may further comprise:

the comparison circuit compares the count value of the counter corresponding to each clock to be tested when the counting is stopped with a preset upper counting limit value and/or a preset lower counting limit value to obtain a comparison result.

Optionally, the method may further include:

if the count value of the counter corresponding to each clock to be tested when the counting is stopped is smaller than the preset upper limit value of the counting and is larger than the preset lower limit value of the counting, the comparison circuit outputs a second control signal to the counter corresponding to the clock to be tested and the counter corresponding to the reference clock;

and initializing the counter corresponding to the clock to be tested and the counter corresponding to the reference clock according to the second control signal.

Optionally, the detection circuit further includes: a response module;

the method may further comprise:

if the count value of the counter corresponding to each clock to be tested when the counting is stopped is greater than or equal to the preset upper counting limit value, or the count value is less than or equal to the preset lower counting limit value, the comparison circuit transmits a third control signal to the response module;

the response module outputs any one of an interrupt signal, an erase signal or a reset signal according to the third control signal.

The detection method can be executed by the detection circuit, and the specific implementation process and the beneficial effects thereof are referred to above and are not described herein again.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (20)

1. A detection circuit, comprising:

   a synchronization module and a detection module; the synchronization module is connected with the detection module;

   the synchronization module is configured to synchronize the received enable signal to a clock domain of each clock signal according to each clock signal in multiple clock signals, so as to obtain an enable signal corresponding to the clock domain of each clock signal and transmit the enable signal to the detection module;

   the detection module is configured to detect each path of clock signal under the action of an enable signal corresponding to a clock domain of each path of clock signal, so as to obtain a frequency of each path of clock signal.
2. The circuit of claim 1, wherein the synchronization module receives the enable signal from an enable module, and a plurality of traces are connected between the synchronization module and the enable module for transmitting the enable signal.
3. The circuit of claim 2, wherein the plurality of traces for transmitting the enable signal are lower-level metal traces within a chip.
4. The circuit of any one of claims 1-3, wherein the detection module comprises: each counter corresponds to one path of clock signals in the multiple paths of clock signals; the synchronization module is connected with each counter;

   the synchronization module is configured to transmit an enable signal corresponding to a clock domain of each path of clock signal to a counter corresponding to each path of clock signal;

   and the counter corresponding to each path of clock signal is used for counting the rising edge or the falling edge of the path of clock signal under the action of an enable signal corresponding to the clock domain of the path of clock signal to obtain a count value corresponding to the path of clock signal, and the count value corresponding to the path of clock signal is used for representing the frequency of the path of clock signal.
5. The circuit of claim 4, wherein the plurality of counters comprises a counter corresponding to a reference clock and a counter corresponding to at least one clock to be tested, and the counter corresponding to the reference clock is connected with the counter corresponding to the clock to be tested;

   the counter corresponding to the reference clock is used for: when the count value of the counter corresponding to the reference clock reaches a preset value, transmitting a first control signal to the counter corresponding to the clock to be tested;

   and the counter corresponding to the clock to be tested is used for stopping counting according to the first control signal.
6. The circuit of claim 5, wherein the detection module further comprises a comparison circuit, and the comparison circuit is connected with a counter corresponding to the clock to be tested;

   the comparison circuit is used for comparing the count value of the counter corresponding to the clock to be measured when the counting is stopped with a preset upper counting limit value and/or a preset lower counting limit value to obtain a comparison result.
7. The circuit of claim 6, wherein the comparison circuit is further connected to a counter corresponding to the reference clock;

   the comparison circuit is further configured to: if the count value of the counter corresponding to the clock to be tested when the counting is stopped is smaller than the preset upper limit value of the counting, and the count value is larger than the preset lower limit value of the counting, outputting a second control signal to the counter corresponding to the clock to be tested and the counter corresponding to the reference clock;

   and the counter corresponding to the clock to be tested and the counter corresponding to the reference clock are used for initializing according to the second control signal.
8. The circuit of claim 6, wherein the detection circuit further comprises: a response module connected to the comparison circuit;

   the comparison circuit is further configured to: if the count value of the counter corresponding to each clock to be tested when the counting is stopped is greater than or equal to the preset upper limit value of the counting, or the count value is less than or equal to the preset lower limit value of the counting, outputting a third control signal to the response module;

   the response module is used for outputting any one of an interrupt signal, an erasing signal or a reset signal according to the third control signal.
9. The circuit of claim 8, wherein a plurality of traces for transmitting the third control signal are connected between the comparison circuit and the response module.
10. The circuit of claim 9, wherein the plurality of traces transmitting the third control signal are lower level metal signal traces within a chip.
11. The circuit of claim 5, wherein the synchronization module comprises: the clock to be tested comprises a plurality of triggers corresponding to the reference clock, a plurality of triggers corresponding to the clock to be tested, a first AND gate and a second AND gate; the plurality of flip-flops corresponding to the reference clock comprise: a first flip-flop, a second flip-flop, a fifth flip-flop, and a sixth flip-flop; the plurality of triggers corresponding to the clock to be tested comprise: a third trigger, a fourth trigger, a seventh trigger, and an eighth trigger;

    the first flip-flop is connected with the second flip-flop, and is configured to receive the enable signal and the clock signal of the reference clock, process the enable signal under the action of the clock signal of the reference clock, and output a signal to the second flip-flop;

    the second flip-flop is further connected to the seventh flip-flop and the first and gate, and is configured to receive an output signal of the first flip-flop and a clock signal of the reference clock, process the output signal of the first flip-flop under the action of the clock signal of the reference clock, and output a signal to the seventh flip-flop and the first and gate;

    the third trigger is connected with the fourth trigger, and is used for receiving the enable signal and the clock signal of the clock to be tested, processing the enable signal under the action of the clock signal of the clock to be tested, and outputting a signal to the fourth trigger;

    the fourth flip-flop is further connected to the fifth flip-flop and the second and gate, and is configured to receive an output signal of the third flip-flop and a clock signal of the clock to be tested, process the output signal of the third flip-flop under the action of the clock signal of the clock to be tested, and output a signal to the fifth flip-flop and the second and gate;

    the fifth flip-flop is configured to receive an output signal of the fourth flip-flop and a clock signal of the reference clock, process the output signal of the fourth flip-flop under the action of the clock signal of the reference clock, and output a signal to the sixth flip-flop;

    the sixth flip-flop is configured to receive an output signal of the fifth flip-flop and the clock signal of the reference clock, process the output signal of the fifth flip-flop under the action of the clock signal of the reference clock, and output a signal to the first and gate;

    the seventh flip-flop is configured to receive the output signal of the second flip-flop and the clock signal of the clock to be tested, process the output signal of the second flip-flop under the action of the clock signal of the clock to be tested, and output a signal to the eighth flip-flop;

    the eighth flip-flop is configured to receive the output signal of the seventh flip-flop and the clock signal of the clock to be tested, process the output signal of the seventh flip-flop under the action of the clock signal of the clock to be tested, and output a signal to the second and gate;

    the first and gate is used for performing and logic processing on the output signal of the second flip-flop and the output signal of the sixth flip-flop and outputting a signal to the counter corresponding to the reference clock;

    and the second and gate is used for performing and logic processing on the output signal of the fourth trigger and the output signal of the eighth trigger and outputting a signal to the counter corresponding to the clock to be tested.
12. The circuit of claim 11, wherein the synchronization module further comprises: an inverter; the multiple triggers corresponding to the clock to be tested further comprise: a ninth flip-flop and a tenth flip-flop;

    the phase inverter is respectively connected with the counter corresponding to the reference clock, the first AND gate and the tenth trigger; the inverter is used for performing inversion processing on an output signal of the counter corresponding to the reference clock and outputting the signal to the first and gate and the tenth trigger;

    the first and gate is specifically configured to perform and logic processing on the output signal of the second flip-flop, the output signal of the sixth flip-flop, and the output signal of the inverter, and output a signal to a counter corresponding to the reference clock;

    the ninth trigger is respectively connected with the tenth trigger and the second AND gate; the tenth flip-flop is configured to receive the output signal of the inverter and the clock signal of the clock to be detected, process the output signal of the inverter under the action of the clock signal of the clock to be detected, and output a signal to the ninth flip-flop;

    the ninth flip-flop is configured to receive an output signal of the tenth flip-flop and the clock signal of the clock to be tested, process the output signal of the tenth flip-flop under the action of the clock signal of the clock to be tested, and output a signal to the second and gate;

    the second and gate is specifically configured to and process an output signal of the fourth flip-flop, an output signal of the eighth flip-flop, and an output signal of the ninth flip-flop, and output a signal to a counter corresponding to the clock to be tested.
13. A chip, comprising: the detection circuit of any of the above claims 1-12.
14. An electronic device, comprising: a chip having the detection circuit of any one of claims 1-12 above.
15. The detection method is characterized by being applied to a detection circuit, wherein the detection circuit comprises a synchronization module and a detection module; the method comprises the following steps:

    the synchronization module synchronizes the received enable signal to the clock domain of each clock signal according to each clock signal in the multiple clock signals, so as to obtain the enable signal corresponding to the clock domain of each clock signal and transmit the enable signal to the detection module;

    and the detection module detects each path of clock signal under the action of an enabling signal corresponding to the clock domain of each path of clock signal to obtain the frequency of each path of clock signal.
16. The method of claim 15, wherein the detection module comprises: a plurality of counters; each counter corresponds to one path of clock signals in the multiple paths of clock signals;

    the synchronization module transmits an enabling signal corresponding to the clock domain of each path of clock signal to a counter corresponding to each path of signal;

    and the counter corresponding to each path of clock signal counts the rising edge or the falling edge of each path of clock signal under the action of the enable signal corresponding to the clock domain of each path of clock signal to obtain a count value corresponding to each path of clock signal, wherein the count value corresponding to each path of clock signal is used for representing the frequency of each path of clock signal.
17. The method of claim 16, wherein the plurality of counters comprises a counter corresponding to a reference clock and a counter corresponding to at least one clock to be tested;

    the method further comprises the following steps:

    when the count value of the counter corresponding to the reference clock reaches a first preset value, transmitting a first control signal to each counter;

    and each counter stops counting according to the first control signal.
18. The method of claim 17, wherein the detection module further comprises: a comparison circuit;

    the method further comprises the following steps:

    and the comparison circuit compares the count value of the counter corresponding to each clock to be tested when the counting is stopped with a preset upper counting limit value and/or a preset lower counting limit value to obtain a comparison result.
19. The method of claim 18, further comprising:

    if the count value of the counter corresponding to each clock to be tested when the counting is stopped is smaller than the preset upper limit value of the counting, and the count value is larger than the preset lower limit value of the counting, the comparison circuit outputs a second control signal to the counter corresponding to the clock to be tested and the counter corresponding to the reference clock;

    and initializing the counter corresponding to the clock to be tested and the counter corresponding to the reference clock according to the second control signal.
20. The method of claim 18, wherein the detection circuit further comprises: a response module;

    the method further comprises the following steps:

    if the count value of the counter corresponding to each clock to be tested when the counting is stopped is greater than or equal to the preset upper counting limit value, or the count value is less than or equal to the preset lower counting limit value, the comparison circuit transmits a third control signal to the response module;

    the response module outputs any one of an interrupt signal, an erase signal or a reset signal according to the third control signal.

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