WO2020037485A1 - Detection circuit, method, chip, and device - Google Patents

Detection circuit, method, chip, and device Download PDF

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WO2020037485A1
WO2020037485A1 PCT/CN2018/101458 CN2018101458W WO2020037485A1 WO 2020037485 A1 WO2020037485 A1 WO 2020037485A1 CN 2018101458 W CN2018101458 W CN 2018101458W WO 2020037485 A1 WO2020037485 A1 WO 2020037485A1
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clock
signal
flip
flop
counter
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PCT/CN2018/101458
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French (fr)
Chinese (zh)
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申艾麟
韦健
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深圳市汇顶科技股份有限公司
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/40Monitoring; Error detection; Preventing or correcting improper counter operation

Abstract

Provided in the present application are a detection circuit, a method, a chip, and a device. The circuit comprises a synchronization module, and a detection module connected to the synchronization circuit, wherein the synchronization module performs clock domain synchronization on enable signals, and transmits to the detection module an enable signal corresponding to the clock domain of each clock signal; under the action of the enable signal, the detection module detects each clock signal to obtain the frequency of each clock signal. According to the present application, the frequency of a clock signal can be accurately detected, thereby ensuring information security.

Description

检测电路、方法、芯片及设备Detection circuit, method, chip and equipment 技术领域Technical field
本申请实施例涉及安全技术,尤其涉及一种检测电路、方法、芯片及设备。The embodiments of the present application relate to security technologies, and in particular, to a detection circuit, a method, a chip, and a device.
背景技术Background technique
随着互联网技术(Internet Technology,IT)的不断发展,信息安全越来越重要。With the continuous development of Internet technology (IT), information security becomes more and more important.
电子设备的芯片上大多集成有数字电路,对于数字电路来说,其正常工作往往需要一个或一组特定频率的时钟对内部寄存器进行驱动。时钟过快或者过慢都有可能导致芯片的非正常工作,带来数据泄密。Most electronic circuits have integrated digital circuits on their chips. For digital circuits, their normal operation often requires a clock with a specific frequency to drive the internal registers. If the clock is too fast or too slow, it may cause the chip to work improperly and cause data leakage.
如何准确检测时钟信号的频率显得格外重要。How to accurately detect the frequency of a clock signal is extremely important.
发明内容Summary of the Invention
本申请实施例提供一种检测电路、方法、芯片及设备,以检测时钟的频率,保证芯片的正常工作,避免数据泄密,提高数据安全。The embodiments of the present application provide a detection circuit, a method, a chip, and a device to detect a frequency of a clock, ensure normal operation of the chip, avoid data leakage, and improve data security.
本申请实施例提供一种检测电路,包括:An embodiment of the present application provides a detection circuit, including:
同步模块和检测模块;所述同步模块与所述检测模块连接;A synchronization module and a detection module; the synchronization module is connected to the detection module;
所述同步模块,用于根据多路时钟信号中的每路时钟信号,将接收到的使能信号同步至所述每路时钟信号的时钟域,以得到所述每路时钟信号的时钟域对应的使能信号并传输至所述检测模块;The synchronization module is configured to synchronize the received enable signal to a clock domain of each clock signal according to each of the multiple clock signals, so as to obtain a clock domain corresponding to each clock signal. The enable signal and transmit it to the detection module;
所述检测模块,用于在所述每路时钟信号的时钟域对应的使能信号的作用下,对所述每路时钟信号进行检测,得到所述每路时钟信号的频率。The detection module is configured to detect each clock signal under the function of an enable signal corresponding to a clock domain of each clock signal to obtain a frequency of each clock signal.
本申请实施例还提供一种芯片,包括:上述检测电路。An embodiment of the present application further provides a chip, including the foregoing detection circuit.
本申请实施例还提供一种电子设备,包括:芯片,上述芯片包括上述任一检测电路。An embodiment of the present application further provides an electronic device including a chip, and the chip includes any one of the foregoing detection circuits.
本申请实施例还提供一种检测方法,所述检测方法适用于检测电路,所述检测电路包括同步模块和检测模块;包括:An embodiment of the present application further provides a detection method. The detection method is applicable to a detection circuit. The detection circuit includes a synchronization module and a detection module. The detection circuit includes:
所述方法包括:The method includes:
所述同步模块根据多路时钟信号中的每路时钟信号,将接收到的使能信号同步至所述每路时钟信号的时钟域,以得到所述每路时钟信号的时钟域对应的使能信号并传输至所述检测模块;The synchronization module synchronizes the received enable signal to the clock domain of each clock signal according to each of the multiple clock signals to obtain an enable corresponding to the clock domain of each clock signal. The signal is transmitted to the detection module;
所述检测模块在所述每路时钟信号的时钟域对应的使能信号的作用下,对所述每路时钟信号进行检测,得到所述每路时钟信号的频率。The detection module detects each clock signal under the function of an enable signal corresponding to a clock domain of each clock signal to obtain a frequency of each clock signal.
本申请实施例提供的检测电路、方法、芯片及设备,其中,该检测电路可包括同步模块和与该同步模块连接的检测模块,可通过同步模块根据多路时钟信号中的每路时钟信号,将接收到的使能信号同步至该每路时钟信号的时钟域,以得到该每路时钟信号的时钟域对应的使能信号并传输至检测模块;还可通过检测模块在该每路时钟信号的时钟域对应的使能信号的作用下,对该每路时钟信号进行检测,得到该每路时钟信号的频率。本方案,可在基于同步后的每路时钟信号的时钟域对应的使能信号,对该每路时钟信号进行检测,可有效避免不同时钟域之间的误差,保证时钟信号的频率检测的准确度,从而有效保证数据安全,避免数据泄露。The detection circuit, method, chip and device provided in the embodiments of the present application, wherein the detection circuit may include a synchronization module and a detection module connected to the synchronization module, and the synchronization module may use each of the multiple clock signals according to the clock signal, Synchronize the received enable signal to the clock domain of each clock signal to obtain the enable signal corresponding to the clock domain of each clock signal and transmit it to the detection module; the detection module can also use the Under the function of the enable signal corresponding to the clock domain, each clock signal is detected to obtain the frequency of each clock signal. This solution can detect each clock signal based on the enable signal corresponding to the clock domain of each clock signal after synchronization, which can effectively avoid errors between different clock domains and ensure the accuracy of the clock signal frequency detection. To ensure data security and avoid data leakage.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍,显而易见地,下面描述中的附图是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。In order to explain the technical solutions in the embodiments of the present application or the prior art more clearly, the drawings used in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without paying creative labor.
图1为本申请实施例提供的一种检测电路的方框示意图;FIG. 1 is a schematic block diagram of a detection circuit according to an embodiment of the present application; FIG.
图2为本申请实施例提供的一种检测电路的另一种方框示意图;FIG. 2 is another schematic block diagram of a detection circuit according to an embodiment of the present application; FIG.
图3为本申请实施例提供的一种检测电路的又一种方框示意图;3 is another schematic block diagram of a detection circuit according to an embodiment of the present application;
图4为本申请实施例提供的一种检测电路的再一种方框示意图;4 is a schematic block diagram of still another detection circuit according to an embodiment of the present application;
图5为本申请实施例提供的一种检测电路的电路结构示意图;FIG. 5 is a schematic circuit structure diagram of a detection circuit according to an embodiment of the present application; FIG.
图6为本申请实施例提供的一种用于图5所示检测电路的响应同步电路的示意图;6 is a schematic diagram of a response synchronization circuit used in the detection circuit shown in FIG. 5 according to an embodiment of the present application;
图7为本申请实施例提供的一种检测电路的状态机的示意图;7 is a schematic diagram of a state machine of a detection circuit according to an embodiment of the present application;
图8为本申请实施例提供的一种芯片的结构示意图;8 is a schematic structural diagram of a chip according to an embodiment of the present application;
图9为本申请实施例提供的一种电子设备的结构示意图;9 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
图10为本申请实施例提供的一种检测方法的流程图。FIG. 10 is a flowchart of a detection method according to an embodiment of the present application.
具体实施方式detailed description
为使本申请实施例的目的、技术方案和优点更加清楚,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments These are part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
除非另有定义,本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。下面结合附图,对本申请的一些实施方式作详细说明。在不冲突的情况下,下述的实施例及实施例中的特征可以相互组合。Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of the present application is only for the purpose of describing specific embodiments, and is not intended to limit the present application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The embodiments of the present application will be described in detail below with reference to the drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.
本申请下述各实施例提供的检测电路、方法、芯片及设备,可应用于具有数字电路的电子设备,用以对时钟信号的频率进行检测。The detection circuits, methods, chips, and devices provided in the following embodiments of the present application can be applied to electronic devices with digital circuits to detect the frequency of a clock signal.
如下通过多个实例对本申请实施例提供的检测电路、方法、芯片及设备进行说明。The detection circuits, methods, chips, and equipment provided by the embodiments of the present application are described through multiple examples as follows.
图1为本申请实施例提供的一种检测电路的方框示意图。该检测电路可应用于具有数字电路的电子设备中。如图1所示,该检测电路可包括:同步模块11和检测模块12。该同步模块11与检测模块12连接。FIG. 1 is a schematic block diagram of a detection circuit according to an embodiment of the present application. The detection circuit can be applied to an electronic device having a digital circuit. As shown in FIG. 1, the detection circuit may include a synchronization module 11 and a detection module 12. The synchronization module 11 is connected to the detection module 12.
同步模块11,用于根据多路时钟信号的每路时钟信号,将接收到的使能信号同步至该每路时钟信号的时钟域,以得到该每路时钟信号的时钟域对应的使能信号传输至检测模块12。A synchronization module 11 is configured to synchronize the received enable signal to the clock domain of each clock signal according to each clock signal of the multiple clock signals to obtain an enable signal corresponding to the clock domain of each clock signal. Transmission to detection module 12.
检测模块12,用于在该每路时钟信号的时钟域对应的使能信号的作用下,对该每路时钟信号进行检测,得到该每路时钟信号的频率。The detection module 12 is configured to detect each clock signal under the function of an enable signal corresponding to a clock domain of each clock signal to obtain a frequency of each clock signal.
具体地,在该检测电路中,同步模块11的输入端可与多个时钟电路(未 示出)的输出端连接,用以接收该多个时钟电路输出的多路时钟信号。同步模块11可具有多个输入端,同步模块11的每个输入端可连接一个时钟电路的输出端,使得每个输入端可接收一个时钟电路所传输的一路时钟信号。Specifically, in the detection circuit, the input terminal of the synchronization module 11 may be connected to the output terminals of a plurality of clock circuits (not shown) to receive multiple clock signals output by the plurality of clock circuits. The synchronization module 11 may have multiple input terminals, and each input terminal of the synchronization module 11 may be connected to an output terminal of a clock circuit, so that each input terminal may receive a clock signal transmitted by a clock circuit.
同步模块11的使能端,还与使能模块的输出端连接,用以接收使能模块输出的使能信号。The enable terminal of the synchronization module 11 is also connected to the output terminal of the enable module, and is used to receive the enable signal output by the enable module.
可选的,同步模块11与使能模块之间存在用于传输该使能信号的多条走线。Optionally, there are multiple tracks for transmitting the enable signal between the synchronization module 11 and the enable module.
也就是说,同步模块11的使能端与使能模块的输出端之间,存在至少两条走线(即多条走线),该至少两条走线中当前传输走线之外的其它走线,可称为冗余走线。该至少两条走线中,每条走线都可用于传输该使能信号。In other words, there are at least two traces (that is, multiple traces) between the enable end of the synchronization module 11 and the output end of the enable module. The at least two traces are other than the current transmission trace. Traces can be called redundant traces. Each of the at least two traces can be used to transmit the enable signal.
假设传输该使能信号的走线仅有一条,一旦受到攻击,例如聚焦离子束(Focused Ion Beam,FIB)攻击,便会使得该走线上传输的使能信号受到攻击被篡改,便会使得整个电路受到威胁。由于本申请中的检测电路中,同步模块11与使能模块之间存在至少两条走线用以传输该使能信号,因而即便传输该使能信号的其中一条走线受到攻击,只要还有另一条走线未受攻击,便可将该使能信号准确传输至同步模块11,便可避免使能信号攻击带来的风险,因此,本申请有效增加了攻击难度,有效避免使能信号的走线被攻击带来的风险,增加了攻击难度。Assume that there is only one trace transmitting the enable signal. Once under attack, such as a Focused Ion Beam (FIB) attack, the enable signal transmitted on the trace will be attacked and tampered, which will cause The entire circuit is threatened. Because in the detection circuit in this application, there are at least two traces between the synchronization module 11 and the enable module for transmitting the enable signal, so even if one of the traces transmitting the enable signal is attacked, as long as there is still The other trace is not attacked, and the enable signal can be accurately transmitted to the synchronization module 11 to avoid the risk of the enable signal attack. Therefore, this application effectively increases the difficulty of the attack and effectively avoids the enable signal. The risk of being attacked by the alignment increases the difficulty of the attack.
为保证传输至同步模块11的使能信号的准确性,该至少两条走线与同步模块11的使能端之间还可接入或(OR)门,由该或门对该至少两条走线传输的使能信号进行处理后,传输至同步模块11的使能端。In order to ensure the accuracy of the enable signal transmitted to the synchronization module 11, an OR gate can also be connected between the at least two traces and the enable end of the synchronization module 11, and the at least two After the enable signals transmitted by the wires are processed, they are transmitted to the enable end of the synchronization module 11.
可选的,上述传输该使能信号的至少两条走线为芯片内的低层金属走线。该低层金属走线的上层覆盖有至少一层金属,也就是传输使能信号的至少两条走线位于多层金属走线结构的低层,这里的低层金属走线相对于高层金属走线而言更远离芯片的表面。Optionally, the at least two traces transmitting the enable signal are low-level metal traces in the chip. The upper layer of the low-level metal trace is covered with at least one layer of metal, that is, at least two traces transmitting the enable signal are located at the lower level of the multilayer metal trace structure. The low-level metal trace here is relative to the high-level metal trace. Further away from the surface of the chip.
其中,该低层金属走线的上层所覆盖的至少一层金属,最上一层为主动防护层(Active Shielding),用于对整个多层金属走线进行保护,避免该多层金属走线被攻击。Among them, at least one layer of metal covered by the upper layer of the low-level metal trace, and the uppermost layer is Active Shielding, which is used to protect the entire multilayer metal trace and prevent the multilayer metal trace from being attacked. .
由于低层金属走线的上层覆盖有金属层,传输该使能信号的至少两条走线采用芯片上的低层金属走线,可有效减低传输使能信号的走线的被攻击风 险。Because the upper layer of the low-level metal trace is covered with a metal layer, at least two traces transmitting the enable signal use low-level metal traces on the chip, which can effectively reduce the risk of being attacked by the trace that transmits the enable signal.
每路时钟信号都具有各自的时钟域,同一使能信号作用于不同的时钟域,其使能的有效时间可能不同。因此,本申请中可通过同步模块11将使能信号同步至每路时钟信号的时钟域,以得到同步后的该每路时钟信号的时钟域对应的使能信号并传输至检测模块12,以触发检测模块12进行时钟信号的检测。Each clock signal has its own clock domain. The same enable signal acts on different clock domains, and the effective time of its enable may be different. Therefore, in this application, the enable signal can be synchronized to the clock domain of each clock signal through the synchronization module 11 to obtain the enable signal corresponding to the clock domain of each clock signal after synchronization and transmitted to the detection module 12 to The trigger detection module 12 detects a clock signal.
同步模块11的输出端可与检测模块12的使能端连接,用以将同步后的该每路时钟信号的时钟域对应的使能信号传输至检测模块12的使能端。The output end of the synchronization module 11 can be connected to the enable end of the detection module 12 to transmit the enable signal corresponding to the clock domain of each clock signal after synchronization to the enable end of the detection module 12.
检测模块12在该每路时钟信号的时钟域对应的使能信号的作用下,在使能信号有效的情况下,可对该每路时钟信号进行检测,得到该每路时钟信号的频率。The detection module 12 can detect each clock signal under the function of the enable signal corresponding to the clock domain of each clock signal, and obtain the frequency of each clock signal.
本申请中,检测模块12所采用的使能信号为同步后的该多个时钟信号的时钟域对应的使能信号,因此,该多个时钟信号的时钟域对应的使能信号的有效时间同步。那么,采用在该每路时钟信号的时钟域对应的使能信号的作用下,可保证检测模块12可同时对该每路时钟信号进行检测,以保证得到的每路信号的频率的准确度。In this application, the enable signals used by the detection module 12 are the enable signals corresponding to the clock domains of the multiple clock signals after synchronization. Therefore, the effective times of the enable signals corresponding to the clock domains of the multiple clock signals are synchronized. . Then, by using the enable signal corresponding to the clock domain of each clock signal, it can be ensured that the detection module 12 can detect each clock signal at the same time to ensure the accuracy of the frequency of each signal obtained.
本申请实施例提供的检测电路,包括同步模块和与该同步模块连接的检测模块,可通过同步模块根据多路时钟信号中的每路时钟信号,将使能信号同步至该每路时钟信号的时钟域,并将得到的该每路时钟信号的时钟域对应的使能信号传输至检测模块;还可通过检测模块在该每路时钟信号的时钟域对应的使能信号的作用下,对该每路时钟信号进行检测,得到该每路时钟信号的频率。本方案,可在基于同步后的每路时钟信号的时钟域对应的使能信号,对该每路时钟信号进行检测,可有效避免不同时钟域之间的误差,保证时钟信号的频率检测的准确度,从而有效保证数据安全,避免数据泄露。The detection circuit provided in the embodiment of the present application includes a synchronization module and a detection module connected to the synchronization module. The synchronization module can synchronize the enable signal to each of the clock signals according to each of the multiple clock signals. The clock domain, and transmits the enable signal corresponding to the clock domain of each clock signal to the detection module; the detection module can also use the enable signal corresponding to the clock domain of each clock signal to detect the Each clock signal is detected to obtain the frequency of each clock signal. This solution can detect each clock signal based on the enable signal corresponding to the clock domain of each clock signal after synchronization, which can effectively avoid errors between different clock domains and ensure the accuracy of the clock signal frequency detection. To ensure data security and avoid data leakage.
本申请实施例还提供一种检测电路。该检测电路在上述基础上,可对检测电路中的检测模块12进行示例说明。图2为本申请实施例提供的一种检测电路的另一种方框示意图。如图2所示,该检测电路中,检测模块12可包括:多个计数器121。每个计数器121可对应多路时钟时钟信号的一路时钟信号。同步模块11与每个计数器121连接。An embodiment of the present application further provides a detection circuit. Based on the above-mentioned detection circuit, the detection module 12 in the detection circuit can be described as an example. FIG. 2 is another schematic block diagram of a detection circuit according to an embodiment of the present application. As shown in FIG. 2, in the detection circuit, the detection module 12 may include a plurality of counters 121. Each counter 121 may correspond to one clock signal of multiple clock signals. The synchronization module 11 is connected to each counter 121.
同步模块11,具体用于将该每路时钟信号的时钟域对应的使能信号传输至该每路时钟信号对应的计数器121。The synchronization module 11 is specifically configured to transmit an enable signal corresponding to a clock domain of each clock signal to a counter 121 corresponding to each clock signal.
每路时钟信号对应的计数器121,用于在该路时钟信号的时钟域对应的使能信号的作用下,对该路时钟信号的上升沿或下降沿进行计数,得到该路时钟信号对应的计数值;该路时钟信号对应的计数值用于表征该路时钟信号的频率。A counter 121 corresponding to each clock signal is used to count the rising or falling edges of the clock signal under the function of the enable signal corresponding to the clock domain of the clock signal to obtain the count corresponding to the clock signal Value; the count value corresponding to the clock signal is used to characterize the frequency of the clock signal.
具体的,同步模块11的输出端可与每个计数器121的使能(Enable,EN)端连接,用以将该每路时钟信号的时钟域对应的使能信号传输至该每路时钟信号对应的计数器121。Specifically, the output end of the synchronization module 11 may be connected to the enable (EN) end of each counter 121 to transmit the enable signal corresponding to the clock domain of each clock signal to the corresponding clock signal of each channel. Of counter 121.
每路时钟信号对应的计数器121还与该每路时钟信号对应的时钟电路连接,用以接收该路时钟信号对应的时钟电路所传输的该路时钟信号。例如,第一路时钟信号对应的计数器121的输入端可与第一路时钟信号对应的时钟电路的输出端连接,第二路时钟信号对应的计数器121的输入端可与第二路时钟信号对应的时钟电路的输出端连接,等等。其中,计数器121的输入端可以是计数器121的时钟脉冲(Clock Pause,CP)端。The counter 121 corresponding to each clock signal is also connected to a clock circuit corresponding to each clock signal, and is configured to receive the clock signal transmitted by the clock circuit corresponding to the clock signal. For example, the input of the counter 121 corresponding to the first clock signal may be connected to the output of the clock circuit corresponding to the first clock signal, and the input of the counter 121 corresponding to the second clock signal may correspond to the second clock signal. The output of the clock circuit is connected, and so on. The input terminal of the counter 121 may be a clock pulse (CP) terminal of the counter 121.
每路时钟信号对应的计数器121,可在该路时钟信号的时钟域对应的使能信号的作用下,开始对该路时钟信号的上升沿或下降沿进行计数。The counter 121 corresponding to each clock signal can start counting the rising edge or the falling edge of the clock signal under the function of the enable signal corresponding to the clock domain of the clock signal.
该检测电路在上述实施例的基础上,通过计数器对时钟信号的上升沿或下降沿进行计数,实现对该时钟信号的频率检测,有效保证了时钟信号频率的检测准确度。Based on the above embodiment, the detection circuit counts the rising or falling edges of the clock signal through a counter to achieve frequency detection of the clock signal, which effectively ensures the accuracy of the detection of the clock signal frequency.
本申请实施例还提供一种检测电路。该检测电路在上述基础上,可对检测电路中的检测模块12进行示例说明。图3为本申请实施例提供的一种检测电路的又一种方框示意图。如图3所示,该检测电路中,检测模块12所包括的多个计数器121,可包括:参考时钟对应的计数器121,和至少一个待测时钟对应的计数器121′。参考时钟对应的计数器121用于接收一路参考时钟信号,并接收同步模块11输出的该路参考时钟信号的时钟域对应的使能信号;待测时钟对应的计数器121′用于接收一路待测时钟信号,并接收同步模块11输出的该路待测时钟信号的时钟域对应的使能信号。参考时钟对应的计数器121与待测时钟对应的计数器121′连接。An embodiment of the present application further provides a detection circuit. Based on the above-mentioned detection circuit, the detection module 12 in the detection circuit can be described as an example. FIG. 3 is another schematic block diagram of a detection circuit according to an embodiment of the present application. As shown in FIG. 3, in the detection circuit, the plurality of counters 121 included in the detection module 12 may include: a counter 121 corresponding to a reference clock, and at least one counter 121 ′ corresponding to a clock to be measured. The counter 121 corresponding to the reference clock is used to receive a reference clock signal and the enable signal corresponding to the clock domain of the reference clock signal output by the synchronization module 11; the counter 121 ′ corresponding to the clock to be tested is used to receive a clock And receive an enable signal corresponding to a clock domain of the clock signal under test output by the synchronization module 11. The counter 121 corresponding to the reference clock is connected to the counter 121 ′ corresponding to the clock to be measured.
参考时钟对应的计数器121,用于当该参考时钟对应的计数器的值达到预设数值,向该待测时钟对应的计数器′传输第一控制信号。The counter 121 corresponding to the reference clock is configured to transmit a first control signal to the counter corresponding to the clock to be measured when the value of the counter corresponding to the reference clock reaches a preset value.
待测时钟对应的每个计数器121′,用于根据第一控制信号停止计数。Each counter 121 'corresponding to the clock to be measured is used to stop counting according to the first control signal.
具体地,该预设数值可以为参考时钟对应的计数器121的最大计数值,也可称为该参考时钟对应的计数器121的预设计数满值。该预设数值可以预先固定在电路中,也可通过编程进行修改。Specifically, the preset value may be a maximum count value of the counter 121 corresponding to the reference clock, and may also be referred to as a preset count full value of the counter 121 corresponding to the reference clock. The preset value can be fixed in the circuit in advance or can be modified by programming.
当参考时钟对应的计数器121的计数值达到预设数值,便可输出该第一控制信号,例如满(full)信号至该每个待测时钟对应的计数器121′,其中满信号高电平有效。When the count value of the counter 121 corresponding to the reference clock reaches a preset value, the first control signal can be output, such as a full signal to the counter 121 ′ corresponding to each clock to be tested, where the full signal is active at a high level .
参考时钟对应的计数器121的输出端可与每个待测时钟对应的计数器121′的使能端连接,用以控制该待测时钟对应的计数器121′停止计数。其中,为保证待测时钟对应的计数器121′在参考时钟对应的计数器121的计数值达到该预设数值之前,可正常进行计数,该参考时钟对应的计数器121的输出端与待测时钟对应的计数器121′的使能端之间还可接入一反相器。该预设计数值例如可以表示为CNT_REF_NUM。The output terminal of the counter 121 corresponding to the reference clock may be connected to the enable terminal of the counter 121 ′ corresponding to each clock to be tested to control the counter 121 ′ corresponding to the clock to be tested to stop counting. Among them, in order to ensure that the counter 121 ′ corresponding to the clock to be measured can be counted normally before the count value of the counter 121 corresponding to the reference clock reaches the preset value, the output end of the counter 121 corresponding to the reference clock is corresponding to the clock to be measured. An inverter can also be connected between the enable terminals of the counter 121 '. The pre-designed value may be expressed as CNT_REF_NUM, for example.
可选的,检测模块12还包括:比较电路122。比较电路122与待测时钟对应的计数器121′连接。Optionally, the detection module 12 further includes a comparison circuit 122. The comparison circuit 122 is connected to a counter 121 ′ corresponding to the clock to be measured.
比较电路122,用于对该待测时钟对应的计数器121′在停止计数时的计数值和预设的计数上限值和/或预设的计数下限值进行比较,得到比较结果。The comparison circuit 122 is configured to compare the count value of the counter 121 ′ corresponding to the clock to be measured when the counting is stopped with a preset upper limit value and / or a preset lower limit value to obtain a comparison result.
比较电路122的输入端与待测时钟对应的计数器121′的输出端如Q端口连接,用以接收该每个待测时钟对应的计数器121′在停止计数时的计数值。The input terminal of the comparison circuit 122 is connected to the output terminal of the counter 121 ′ corresponding to the clock to be tested, such as the Q port, and is used to receive the count value of the counter 121 ′ corresponding to each clock to be tested when the counting is stopped.
其中,该每个待测时钟对应的计数器121′在停止计数时的计数值可以表示为CNT_TEST_NUM。该预设的计数上限值可以表示为HB,该预设的计数下限值可表示为LB。Wherein, the count value of the counter 121 ′ corresponding to each clock to be measured when stopping counting may be expressed as CNT_TEST_NUM. The preset count upper limit value can be expressed as HB, and the preset count lower limit value can be expressed as LB.
该预设的计数上限值HB和预设的计数下限值LB可以通过编程设定误差容限δ和理论计数值c来控制,其中LB=c-δ,HB=c+δ。故可以抵消因为工艺等引入的误差,防止误报警,灵活可控。其中,理论计数值c可与参考时钟对应的计数器的计数满值,例如上述预设数值,存在预设的对应关系。The preset count upper limit value HB and the preset count lower limit value LB can be controlled by programming an error tolerance δ and a theoretical count value c, where LB = c-δ and HB = c + δ. Therefore, it can offset the errors introduced by the process, prevent false alarms, and be flexible and controllable. The theoretical count value c may be a full value of the counter corresponding to the reference clock. For example, the preset value has a preset correspondence relationship.
可选的,该比较电路122还可与参考时钟对应的计数器121连接。Optionally, the comparison circuit 122 can also be connected to a counter 121 corresponding to a reference clock.
比较电路122,还用于在预定条件下输出第二控制信号至参考时钟对应的 计数器121和待测时钟对应的计数器121′。该预定条件可以是:该待测时钟对应的计数器121′在停止计数时的计数值小于该预设的计数上限值,且,大于该预设的计数下限值。The comparison circuit 122 is further configured to output a second control signal to the counter 121 corresponding to the reference clock and the counter 121 'corresponding to the clock to be measured under predetermined conditions. The predetermined condition may be that the count value of the counter 121 ′ corresponding to the clock to be measured when the counting is stopped is smaller than the preset upper limit value and greater than the preset lower limit value.
待测时钟对应的计数器121′和参考时钟对应的计数器121,用于根据该第二控制信号进行初始化。The counter 121 ′ corresponding to the clock to be measured and the counter 121 corresponding to the reference clock are used for initialization according to the second control signal.
具体地址,若该待测时钟对应的计数器121′在停止计数时的计数值小于该预设的计数上限值,且,大于该预设的计数下限值,则该待测时钟的时钟信号的频率处于预设范围内,可确定该待测时钟的时钟信号未受到攻击,通过比较电路122输出第二控制信号控制该待测时钟对应的计数器121′和参考时钟对应的计数器121进行初始化,用以使得待测时钟对应的计数器121′重新对待测时钟的时钟信号的上升沿或下降沿进行计数,以重新对待测时钟的时钟信号进行频率检测,使得参考时钟对应的计数器121重新对参考时钟的时钟信号的上升沿或下降沿进行计数,以重新对参考时钟的时钟信号进行频率检测。Specific address, if the count value of the counter 121 ′ corresponding to the clock to be measured when the counting is stopped is smaller than the preset upper limit value and greater than the preset lower limit value, the clock signal of the clock to be measured The frequency of the clock is within a preset range, it can be determined that the clock signal of the clock to be tested is not under attack, and the second control signal output by the comparison circuit 122 controls the counter 121 ′ corresponding to the clock to be tested and the counter 121 corresponding to the reference clock to be initialized. It is used to make the counter 121 ′ corresponding to the clock to be tested to count the rising or falling edges of the clock signal of the clock to be tested again to perform frequency detection on the clock signal of the clock to be tested, so that the counter 121 corresponding to the reference clock re-references the reference clock. Count the rising or falling edge of the clock signal to re-frequency detect the clock signal of the reference clock.
该第二控制信号例如可以为清零信号,那么待测时钟对应的计数器121′和参考时钟对应的计数器121在接收到该第二控制信号后,可分别根据该第二控制信号进行计数值的初始化,例如将计数值清零或恢复至预设的起始数值。The second control signal may be, for example, a clear signal. After receiving the second control signal, the counter 121 ′ corresponding to the clock to be measured and the counter 121 corresponding to the reference clock may perform counting based on the second control signal. Initialization, such as resetting the count value to a preset starting value.
比较电路122的输出端还与待测时钟对应的计数器121′初始化端口如清零(CLR)端口连接,用以传输该第二控制信号至待测时钟对应的计数器121′。比较电路122的输出端还与参考时钟对应的计数器121的初始化端口如清零(CLR)端口连接,用以传输该第二控制信号至参考时钟对应的计数器121。The output terminal of the comparison circuit 122 is also connected to a counter 121 ′ initialization port corresponding to the clock to be tested, such as a clear (CLR) port, for transmitting the second control signal to the counter 121 ′ corresponding to the clock to be tested. The output terminal of the comparison circuit 122 is also connected to an initialization port of the counter 121 corresponding to the reference clock, such as a clear (CLR) port, for transmitting the second control signal to the counter 121 corresponding to the reference clock.
为使得待测时钟对应的计数器121′和参考时钟对应的计数器121在第二控制信号的作用下,可同时进行初始化,比较电路122与待测时钟对应的计数器121′之间还存在同步模块,用以根据该待测时钟的时钟信号对该第二控制信号进行同步,得到同步后的每路时钟信号的时钟域对应的该第二控制信号,并将待测时钟的时钟信号的时钟域对应的该第二控制信号传输至待测时钟对应的计数器121′。比较电路122与参考时钟对应的计数器121之间还存在同步模块,用以根据该参考时钟的时钟信号对该第二控制信号进行同步,得到同步后的该参考时钟的时钟信号的时钟域对应的该第二控制信号,并将 参考时钟的时钟信号的时钟域对应的该第二控制信号传输至参考时钟对应的计数器121。In order to make the counter 121 ′ corresponding to the clock to be tested and the counter 121 corresponding to the reference clock to be initialized simultaneously under the action of the second control signal, a synchronization module also exists between the comparison circuit 122 and the counter 121 ′ corresponding to the clock to be tested. The second control signal is synchronized according to the clock signal of the clock to be tested, to obtain the second control signal corresponding to the clock domain of each clock signal after synchronization, and to correspond to the clock domain of the clock signal of the clock to be tested. The second control signal is transmitted to the counter 121 ′ corresponding to the clock to be measured. There is also a synchronization module between the comparison circuit 122 and the counter 121 corresponding to the reference clock, which is used to synchronize the second control signal according to the clock signal of the reference clock to obtain a corresponding clock domain of the clock signal of the reference clock after synchronization. The second control signal transmits the second control signal corresponding to the clock domain of the clock signal of the reference clock to the counter 121 corresponding to the reference clock.
比较电路122与待测时钟对应的计数器121′,以及比较电路122与参考时钟对应的每个计数器121之间的同步模块可类似与上述图1所示的同步模块,参见上述,在此不再赘述。The counter 121 ′ corresponding to the comparison circuit 122 and the clock to be measured, and the synchronization module between the comparison circuit 122 and each counter 121 corresponding to the reference clock may be similar to the synchronization module shown in FIG. 1 described above. To repeat.
该检测电路中,参考时钟与待测时钟各自独立,其对应的计数器也各自独立,参考时钟与待测时钟的频率和/或相位之间不存在对应关系,不存在约束关系,可有效避免参考时钟被攻击导致的待测时钟的频率检测不准确,提高时钟信号的频率检测的准确度。并且,该检测电路中,待测时钟的计数器的计数值具有上下限值,即该待测时钟的计数器的计数值具有一定的容差范围,这使得待测时钟的频率可具有一定的容差范围,可有效避免时钟抖动、时钟偏移或其它工艺引入的误差,精度灵活可控。In this detection circuit, the reference clock and the clock to be tested are independent, and the corresponding counters are also independent. There is no correspondence between the frequency and / or phase of the reference clock and the clock to be tested, and there is no constraint relationship, which can effectively avoid reference The frequency detection of the clock under test caused by the attack of the clock is not accurate, and the accuracy of the frequency detection of the clock signal is improved. Moreover, in the detection circuit, the count value of the counter of the clock to be tested has upper and lower limits, that is, the count value of the counter of the clock to be tested has a certain tolerance range, which allows the frequency of the clock to be tested to have a certain tolerance. The range can effectively avoid clock jitter, clock offset, or errors introduced by other processes, and the accuracy is flexible and controllable.
本申请实施例还提供一种检测电路。该检测电路在上述图3的基础上,对检测电路进行进一步的说明。图4为本申请实施例提供的一种检测电路的再一种方框示意图。如图4所示,在上述图3的基础上,该检测电路中还可包括响应模块13。响应模块13与比较电路122连接。An embodiment of the present application further provides a detection circuit. This detection circuit further describes the detection circuit on the basis of FIG. 3 described above. FIG. 4 is another schematic block diagram of a detection circuit according to an embodiment of the present application. As shown in FIG. 4, based on the above FIG. 3, the detection circuit may further include a response module 13. The response module 13 is connected to the comparison circuit 122.
比较电路122,还用于在预定条件下输出第三控制信号至响应模块13。该预定条件可以是:该待测时钟对应的计数器121′在停止计数时的计数值大于或等于该预设的计数上限值,或者,该计数值小于或等于该预设的计数下限值。The comparison circuit 122 is further configured to output a third control signal to the response module 13 under a predetermined condition. The predetermined condition may be: the count value of the counter 121 ′ corresponding to the clock to be measured when the counting is stopped is greater than or equal to the preset upper limit value, or the count value is less than or equal to the preset lower limit value .
响应模块13,用于根据该第三控制信号输出中断信号、擦除信号或者复位信号中的任一信号。The response module 13 is configured to output any one of an interrupt signal, an erase signal, or a reset signal according to the third control signal.
具体地,若该待测时钟对应的计数器121′在停止计数时的计数值大于或等于该预设的计数上限值,或者,该计数值小于或等于该预设的计数下限值,则该待测时钟的时钟信号的频率超出预设范围,可确定该待测时钟的时钟信号可能受到攻击,通过比较电路122输出第三控制信号控制响应模块13输出中断信号、擦除信号或者复位信号中的任一信号,用以避免信息泄露。Specifically, if the count value of the counter 121 ′ corresponding to the clock to be measured at the time of stopping counting is greater than or equal to the preset upper limit value, or the count value is less than or equal to the preset lower limit value, then The frequency of the clock signal of the clock to be tested exceeds a preset range, it can be determined that the clock signal of the clock to be tested may be attacked. The comparison circuit 122 outputs a third control signal to control the response module 13 to output an interrupt signal, an erase signal or a reset signal. To avoid any information leakage.
比较模块122的输出端可与响应模块13的输入端连接,用以向响应模块13输出该第三控制信号。响应模块13可以为报警响应电路,该第三控制信 号可以为报警信号。The output terminal of the comparison module 122 can be connected to the input terminal of the response module 13 to output the third control signal to the response module 13. The response module 13 may be an alarm response circuit, and the third control signal may be an alarm signal.
响应模块13在接收到第三控制信号后,根据该第三控制信号输出响应信号,如输出状态标志位、输出中断信号、擦除信号如敏感信息擦除信号或者复位信号中的任一,用以避免信息泄露。After receiving the third control signal, the response module 13 outputs a response signal according to the third control signal, such as any one of an output status flag, an interrupt signal, an erasing signal such as a sensitive information erasing signal, or a reset signal. To avoid information leakage.
可选的,比较电路122与响应模块13之间连接有传输该第三控制信号的至少两条走线,即多条走线。Optionally, at least two traces, that is, multiple traces, are connected between the comparison circuit 122 and the response module 13 to transmit the third control signal.
也就是说,比较电路122的输出端与响应模块13的输入端之间,存在至少两条走线,该至少两条走线中当前传输走线之外的其它走线,可称为冗余走线。该至少两条走线中,每条走线都可用于传输该第三控制信号。That is to say, there are at least two traces between the output of the comparison circuit 122 and the input of the response module 13, and other traces other than the current transmission trace in the at least two traces can be called redundant Traces. Each of the at least two traces can be used to transmit the third control signal.
假设传输该第三控制信号的走线仅有一条,一旦受到攻击,例如FIB攻击,便会使得该走线上传输的第三控制信号受到攻击被篡改,便会使得整个电路受到威胁。由于本申请中的检测电路中,比较电路122与响应模块13之间存在至少两条走线用以传输该第三控制信号,因而即便传输该第三控制信号的其中一条走线受到攻击,只要还有另一条走线可传输准确的未受攻击,便可将该第三控制信号准确传输至响应模块13,便可避免该第三控制信号攻击带来的风险,因此,本申请有效增加了攻击难度,有效避免走线被攻击带来的风险。Assume that there is only one trace transmitting the third control signal. Once attacked, such as a FIB attack, the third control signal transmitted on the trace will be attacked and tampered, and the entire circuit will be threatened. Because in the detection circuit in this application, there are at least two traces between the comparison circuit 122 and the response module 13 for transmitting the third control signal, so even if one of the traces transmitting the third control signal is attacked, as long as There is another line that can transmit accurate and unattended, and the third control signal can be accurately transmitted to the response module 13 to avoid the risk brought by the third control signal attack. Therefore, this application effectively increases Attack difficulty, effectively avoiding the risk of being attacked by the wiring.
为保证传输至响应模块13的第三控制信号的准确性,该至少两条走线与响应模块13的输入端之间还可接入或(OR)门,由该或门对该至少两条走线传输的第三控制信号进行处理后,传输至响应模块13的输入端。To ensure the accuracy of the third control signal transmitted to the response module 13, an OR gate may be connected between the at least two traces and the input terminal of the response module 13, and the at least two After the third control signal transmitted by the line is processed, it is transmitted to the input terminal of the response module 13.
可选的,传输该第三控制信号的至少两条走线为芯片的低层金属走线;该低层金属走线的上层还覆盖有至少一层金属,也就是传输使能信号的至少两条走线位于多层金属走线结构的低层,这里的低层金属走线相对于高层金属走线而言更远离芯片的表面。Optionally, at least two traces transmitting the third control signal are low-level metal traces of the chip; the upper layer of the low-level metal traces is also covered with at least one layer of metal, that is, at least two traces transmitting the enable signal The lines are located at the lower layer of the multilayer metal trace structure. The lower metal traces here are farther away from the surface of the chip than the high-level metal traces.
其中,该低层走线的上层所覆盖的至少一层金属,最上一层为主动防护层,用于对该整个多层金属走线进行保护,避免该多层金属走线被攻击。Among them, at least one layer of metal covered by the upper layer of the low-layer trace, and the uppermost layer is an active protection layer, which is used to protect the entire multilayer metal trace from being attacked.
由于低层走线的表面上层有其它走线,传输该第三控制信号的至少两条走线采用芯片上的低层走线,可有效减低传输第三控制信号的走线的被攻击风险。Because there are other traces on the surface of the lower-layer trace, at least two traces transmitting the third control signal adopt low-layer traces on the chip, which can effectively reduce the risk of being attacked by the traces transmitting the third control signal.
本申请实施例还可提供一种检测电路,图5为本申请实施例提供的一种检测电路的电路结构示意图。如图5所示,该检测电路可以为上述图1至图4中任一所述的检测电路的一种可能的示例。如图5所示,该检测电路可包括:使能保护电路50、使能同步电路51、计数电路52,比较电路53、响应保护电路54及响应电路55。An embodiment of the present application may further provide a detection circuit. FIG. 5 is a schematic diagram of a circuit structure of a detection circuit provided by an embodiment of the present application. As shown in FIG. 5, the detection circuit may be a possible example of the detection circuit described in any one of FIG. 1 to FIG. 4. As shown in FIG. 5, the detection circuit may include: an enable protection circuit 50, an enable synchronization circuit 51, a counting circuit 52, a comparison circuit 53, a response protection circuit 54, and a response circuit 55.
其中,使能保护电路50可包括第一或门(OR1)。The enable protection circuit 50 may include a first OR gate (OR1).
上述同步模块11例如可包括图5所示的使能同步电路51。在图5中使能同步电路51包括参考时钟对应的触发器、待测时钟对应的触发器、第一与门(AND1)、第二与门(AND2)。其中,参考时钟对应的触发器包括:触发器D1、触发器D2、触发器D5及触发器D6。待测时钟对应的触发器包括:触发器D3、触发器D4、触发器D7、触发器D8。The above-mentioned synchronization module 11 may include, for example, an enable synchronization circuit 51 shown in FIG. 5. In FIG. 5, the enabling synchronization circuit 51 includes a flip-flop corresponding to a reference clock, a flip-flop corresponding to a clock to be tested, a first AND gate (AND1), and a second AND gate (AND2). The flip-flops corresponding to the reference clock include: flip-flop D1, flip-flop D2, flip-flop D5, and flip-flop D6. The triggers corresponding to the clock to be tested include: trigger D3, trigger D4, trigger D7, and trigger D8.
上述检测模块12例如可包括图5所示的计数电路52。该图5所示的计数电路52包括:计数器1和计数器2。上述参考时钟对应的计数器121可以采用该图5中的计数器1,上述待测时钟对应的计数器121′可以采用计数器2。The detection module 12 may include, for example, a counting circuit 52 shown in FIG. 5. The counting circuit 52 shown in FIG. 5 includes a counter 1 and a counter 2. The counter 121 corresponding to the reference clock may use counter 1 in FIG. 5, and the counter 121 ′ corresponding to the clock to be measured may use counter 2.
上述比较电路122可以与图5所示的比较电路53的具体形态相同,也可不同。比较电路122或比较电路53例如可以为比较器。The specific form of the comparison circuit 122 may be the same as or different from that of the comparison circuit 53 shown in FIG. 5. The comparison circuit 122 or the comparison circuit 53 may be, for example, a comparator.
响应保护电路54可包括第二或门(OR2)。The response protection circuit 54 may include a second OR gate (OR2).
上述响应模块13例如可包括图5所示的响应电路55。The response module 13 may include, for example, a response circuit 55 shown in FIG. 5.
图5所示的检测电路中,使能保护电路50可接收通过多条走线上传输的使能信号,并通过第一或门OR1进行处理后,输出至使能同步电路51中,即,将多路使能信号择一输出到使能同步电路51。具体的,使能信号输出到触发器D1和触发器D3对应的D端口。其中,该多条走线上传输的使能信号可为n组使能信号,例如可表示为en_1、en_2…、en_n。n为大于1的整数。n组使能信号的传输走线,以及第一或门OR1的输出走线,可设置在多层金属走线芯片中的低层金属走线层。In the detection circuit shown in FIG. 5, the enable protection circuit 50 can receive the enable signals transmitted through multiple traces, process them through the first OR gate OR1, and output them to the enable synchronization circuit 51, that is, One of the multiple enable signals is output to the enable synchronization circuit 51. Specifically, the enable signal is output to the D ports corresponding to the flip-flop D1 and the flip-flop D3. The enable signals transmitted on the multiple wires may be n groups of enable signals, for example, they may be represented as en_1, en_2, ..., en_n. n is an integer greater than 1. The n sets of transmission lines for the enable signals and the output lines of the first OR gate OR1 can be set in the lower metal wiring layer in the multilayer metal wiring chip.
参考时钟的时钟信号clk_ref输入至使能同步电路51中的参考时钟对应的触发器,即触发器D1、触发器D2、触发器D5及触发器D6。该参考时钟的时钟信号还可输入至计数器1的CP端。The clock signal clk_ref of the reference clock is input to flip-flops corresponding to the reference clock in the enable synchronization circuit 51, that is, flip-flop D1, flip-flop D2, flip-flop D5, and flip-flop D6. The clock signal of the reference clock can also be input to the CP terminal of the counter 1.
待测时钟的时钟信号clk_test输入至使能同步电路51中待测时钟对应的触发器,即触发器D3、触发器D4、触发器D7、触发器D8。待测时钟的时 钟信号输入至计数器2的CP端。The clock signal clk_test of the clock to be tested is input to the flip-flops corresponding to the clock to be tested in the enable synchronization circuit 51, that is, flip-flop D3, flip-flop D4, flip-flop D7, and flip-flop D8. The clock signal of the clock to be measured is input to the CP terminal of counter 2.
触发器D1与触发器D2连接。触发器D1用于在该参考时钟的时钟信号的作用下对该使能信号进行处理,并输出信号至触发器D2。触发器D1可通过Q端口,将触发器D1的输出信号传输至触发器D2的D端口。The flip-flop D1 is connected to the flip-flop D2. The flip-flop D1 is configured to process the enable signal under the action of the clock signal of the reference clock, and output a signal to the flip-flop D2. The flip-flop D1 can transmit the output signal of the flip-flop D1 to the D port of the flip-flop D2 through the Q port.
触发器D2还与触发器D7和第一与门AND1连接,触发器D2用于在该参考时钟的时钟信号的作用下对触发器D1的输出信号进行处理,并输出信号至触发器D7和第一与门AND1。触发器D2可通过Q端口将触发器D2的输出信号传输至触发器D7的D端口和第一与门AND1。The flip-flop D2 is also connected to the flip-flop D7 and the first AND gate AND1. The flip-flop D2 is used to process the output signal of the flip-flop D1 under the function of the clock signal of the reference clock, and output the signal to the flip-flop D7 and the first One AND gate AND1. The flip-flop D2 can transmit the output signal of the flip-flop D2 to the D port of the flip-flop D7 and the first AND gate AND1 through the Q port.
触发器D3与触发器D4连接。触发器D3用于在该待测时钟的时钟信号的作用下对该使能信号进行处理,并输出信号至触发器D4。触发器D3可通过Q端口,将触发器D3的输出信号传输至触发器D4的D端口。The flip-flop D3 is connected to the flip-flop D4. The flip-flop D3 is used to process the enable signal under the action of the clock signal of the clock to be tested, and output a signal to the flip-flop D4. The flip-flop D3 can transmit the output signal of the flip-flop D3 to the D-port of the flip-flop D4 through the Q port.
触发器D4还与触发器D5和第二与门AND2连接。触发器D4用于在该待测时钟的时钟信号的作用下对触发器D3的输出信号进行处理,并输出信号至触发器D5和第二与门AND2。触发器D4可通过Q端口将触发器D4的输出信号传输至触发器D5的D端口和第二与门AND2。Flip-flop D4 is also connected to flip-flop D5 and a second AND gate AND2. The flip-flop D4 is used to process the output signal of the flip-flop D3 under the action of the clock signal of the clock to be tested, and output the signal to the flip-flop D5 and the second AND gate AND2. The flip-flop D4 can transmit the output signal of the flip-flop D4 to the D port of the flip-flop D5 and the second AND gate AND2 through the Q port.
触发器D5,用于在该参考时钟的时钟信号的作用下对触发器D4的输出信号进行处理,并输出信号至触发器D6。触发器D5可通过Q端口将触发器D5的输出信号传输至触发器D6的D端口。The flip-flop D5 is configured to process an output signal of the flip-flop D4 under the action of the clock signal of the reference clock, and output the signal to the flip-flop D6. The flip-flop D5 can transmit the output signal of the flip-flop D5 to the D port of the flip-flop D6 through the Q port.
触发器D6,用于在该参考时钟的时钟信号的作用下对触发器D5的输出信号进行处理,并输出信号至第一与门AND1。触发器D6可通过Q端口将触发器D6的输出信号传输至第一与门AND1。The flip-flop D6 is configured to process an output signal of the flip-flop D5 under the action of the clock signal of the reference clock, and output the signal to the first AND gate AND1. The flip-flop D6 can transmit the output signal of the flip-flop D6 to the first AND gate AND1 through the Q port.
触发器D7,用于在该待测时钟的时钟信号的作用下对触发器D2的输出信号进行处理,并输出信号至触发器D8。触发器D7可通过Q端口将触发器D7的输出信号传输至触发器D8的D端口。The flip-flop D7 is configured to process an output signal of the flip-flop D2 under the action of the clock signal of the clock to be tested, and output the signal to the flip-flop D8. The flip-flop D7 can transmit the output signal of the flip-flop D7 to the D port of the flip-flop D8 through the Q port.
触发器D8,用于在该待测时钟的时钟信号的作用下对触发器D7的输出信号进行处理,并输出信号至第二与门AND2。触发器D8可通过Q端口将触发器D8的输出信号传输至第二与门AND2。The flip-flop D8 is configured to process an output signal of the flip-flop D7 under the action of the clock signal of the clock to be tested, and output the signal to the second AND gate AND2. The flip-flop D8 can transmit the output signal of the flip-flop D8 to the second AND gate AND2 through the Q port.
第一与门AND1用于对触发器D2的输出信号和触发器D6的输出信号,进行与逻辑处理,并输出信号至该参考时钟对应的计数器,即计数器1。第一与门AND1的输出信号可输出至计数器1的使能(EN)端,触发计数器1 开始对参考时钟的时钟信号的上升沿或下降沿进行计数。第一与门AND1进行与逻辑处理后的信号即为同步处理后的该参考时钟的时钟信号对应的时钟域的使能信号。The first AND gate AND1 is configured to perform AND logic processing on an output signal of the flip-flop D2 and an output signal of the flip-flop D6, and output a signal to a counter corresponding to the reference clock, that is, counter 1. The output signal of the first AND gate AND1 can be output to the enable (EN) terminal of the counter 1, and trigger the counter 1 to start counting the rising or falling edge of the clock signal of the reference clock. The signal after the AND logic processing by the first AND gate AND1 is the enable signal of the clock domain corresponding to the clock signal of the reference clock after the synchronization processing.
第二与门AND2用于对触发器D4输出的信号和触发器D8输出的信号,进行与逻辑处理,并输出信号至待测时钟对应的,即计数器2。第二与门AND2的输出信号至计数器2的使能(EN)端,触发计数器2开始对待测时钟的时钟信号的上升沿或下降沿进行计数。第二与门AND2进行与逻辑处理后的信号即为同步处理后的该待测时钟的时钟信号对应的时钟域的使能信号。The second AND gate AND2 is used to perform AND logic processing on the signal output from the flip-flop D4 and the signal output from the flip-flop D8, and output a signal corresponding to the clock to be measured, namely, the counter 2. The output signal of the second AND gate AND2 is connected to the enable (EN) terminal of the counter 2 to trigger the counter 2 to start counting the rising or falling edge of the clock signal of the clock to be measured. The signal after the logical processing of the second AND gate AND2 is the enable signal of the clock domain corresponding to the clock signal of the clock to be tested after the synchronous processing.
计数器1的计数值可用于表征参考时钟的时钟信号的频率,计数器2的计数值可用于表征待测时钟的时钟信号的频率。The count value of counter 1 can be used to characterize the frequency of the clock signal of the reference clock, and the count value of counter 2 can be used to characterize the frequency of the clock signal of the clock to be tested.
可选的,如上所示的使能同步电路51还包括:反相器。待测时钟对应的多个触发器,还包括:触发器D9和触发器D10。Optionally, the enabling synchronization circuit 51 shown above further includes: an inverter. The multiple flip-flops corresponding to the clock to be tested further include a flip-flop D9 and a flip-flop D10.
反相器分别与参考时钟对应的计数器即计数器1、第一与门AND1和触发器D10连接。反相器,用于对计数器1的输出信号进行反相处理后,并输出信号至第一与门AND1和触发器D10。该计数器1的输出信号例如可以包括:该计数器1的满值(full)端口输出的信号。The inverters are respectively connected to the counters corresponding to the reference clock, that is, the counter 1, the first AND gate AND1, and the flip-flop D10. The inverter is configured to invert the output signal of the counter 1 and output the signal to the first AND gate AND1 and the flip-flop D10. The output signal of the counter 1 may include, for example, a signal output from a full port of the counter 1.
第一与门AND1,具体用于对触发器D2的输出信号、触发器D6的输出信号以及反相器的输出信号进行与逻辑处理,并输出信号至计数器D1。The first AND gate AND1 is specifically configured to perform AND logic processing on the output signal of the flip-flop D2, the output signal of the flip-flop D6, and the output signal of the inverter, and output the signal to the counter D1.
触发器D9分别与触发器D10和第二与门AND2连接,触发器D10用于在反相器的输出信号的作用下对该待测时钟的时钟信号进行处理,并输出信号至触发器D9。The flip-flop D9 is connected to the flip-flop D10 and the second AND gate AND2 respectively. The flip-flop D10 is used to process the clock signal of the clock to be tested under the action of the output signal of the inverter, and output the signal to the flip-flop D9.
触发器D9用于在D10触发器的输出信号的作用下对该待测时钟的时钟信号进行处理,并输出信号至第二与门AND2。The flip-flop D9 is used to process the clock signal of the clock to be tested under the effect of the output signal of the D10 flip-flop, and output the signal to the second AND gate AND2.
第二与门AND2,具体用于对触发器D4的输出信号、触发器D8的输出信号以及触发器D9的输出信号进行与处理,并输出信号至计数器2。The second AND gate AND2 is specifically configured to AND process an output signal of the flip-flop D4, an output signal of the flip-flop D8, and an output signal of the flip-flop D9, and output the signal to the counter 2.
当计数器1的计数值达到预设数值时,计数器1的满值(full)端口输出的满值信号传输至反相器,经该反相器进行反相处理后,输出信号至第一与门AND1,使得第一与门AND1的输出信号失效,即该参考时钟的时钟信号对应的时钟域的使能信号失效,从而控制计数器1停止计数。When the count value of counter 1 reaches a preset value, the full-value signal output from the full port of counter 1 is transmitted to the inverter, and after the inverter performs inversion processing, the output signal is output to the first AND gate. AND1 makes the output signal of the first AND gate AND1 invalid, that is, the enable signal of the clock domain corresponding to the clock signal of the reference clock becomes invalid, thereby controlling the counter 1 to stop counting.
同时,当计数器1的计数值达到预设数值时,该计数器1的满值(full) 端口输出的满值信号传输至反相器,经该反相器进行反相处理后,依次经触发器D10及触发器D9处理,并由触发器D9输出信号至第二与门AND2,使得第二与门AND2的输出信号失效,即该待测时钟的时钟信号对应的时钟域的使能信号失效,从而控制计数器2停止计数。At the same time, when the count value of the counter 1 reaches the preset value, the full value signal output from the full port of the counter 1 is transmitted to the inverter, and after the inverter performs inversion processing, it sequentially passes the trigger D10 and flip-flop D9 are processed, and the flip-flop D9 outputs a signal to the second AND gate AND2, so that the output signal of the second AND gate AND2 becomes invalid, that is, the enable signal of the clock domain corresponding to the clock signal of the clock to be tested is invalid. Thus, the control counter 2 stops counting.
在计数器2停止计数后,计数器2的计数值通过计数器2的Q端口传输至比较电路53。After the counter 2 stops counting, the count value of the counter 2 is transmitted to the comparison circuit 53 through the Q port of the counter 2.
比较电路53对在计数器2停止计数后的计数值和预设的计数上限值和/或预设的计数下限值进行比较,得到比较结果。The comparison circuit 53 compares the count value after the counter 2 stops counting with a preset count upper limit value and / or a preset count lower limit value to obtain a comparison result.
若该比较结果为计数器2停止计数后的计数值小于预设的计数上限值,且,该计数值大于该预设的计数下限值,则比较电路53输出清零信号至计数器1和计数器2的CLR端口,用以使得计数器1和计数器2将计数值清零,实现计数初始化。If the comparison result is that the count value after the counter 2 stops counting is less than the preset upper limit value, and the count value is greater than the preset lower limit value, the comparison circuit 53 outputs a clear signal to the counter 1 and the counter The CLR port of 2 is used to make counter 1 and counter 2 clear the count value to realize the count initialization.
若该比较结果为计数器2停止计数后的计数值大于或等于预设的计数上限值,或者,该计数值小于或等于该预设的计数下限值,比较电路53可通过至少两条走线传输报警信号至第二或门OR2,由第二或门OR2进行或逻辑处理,并输出信号至响应电路55,以使得响应电路55输出中断信号、擦除信号或者复位信号等信号中的任一信号。其中,该至少两条走线上传输的报警信号可为m组报警信号,例如可表示为war_1、war_2…、war_m。m为大于1的整数。m组报警信号的传输走线,以及第二或门OR2的输出走线,可采用低层金属走线。If the comparison result is that the count value after the counter 2 stops counting is greater than or equal to the preset upper limit value, or the count value is less than or equal to the preset lower limit value, the comparison circuit 53 may pass at least two steps. The line transmits an alarm signal to the second OR gate OR2, which is OR-processed by the second OR gate OR2, and outputs a signal to the response circuit 55, so that the response circuit 55 outputs any of an interrupt signal, an erase signal, or a reset signal. A signal. The alarm signals transmitted on the at least two tracks may be m groups of alarm signals, for example, they may be expressed as war_1, war_2, ..., war_m. m is an integer greater than 1. The transmission lines of the m group of alarm signals, and the output lines of the second OR gate OR2, can use low-level metal lines.
图6为本申请实施例提供的一种用于图5所示的检测电路的响应同步电路的示意图。如图6所示,该检测电路在上述图5所示的检测电路的检测上,还包括:响应同步电路56,其连接于所述比较电路53与所述计数电路52之间。FIG. 6 is a schematic diagram of a response synchronization circuit used in the detection circuit shown in FIG. 5 according to an embodiment of the present application. As shown in FIG. 6, in the detection of the detection circuit shown in FIG. 5, the detection circuit further includes a response synchronization circuit 56 connected between the comparison circuit 53 and the counting circuit 52.
响应同步电路56包括:参考时钟对应的触发器、待测时钟对应的触发器、第三与门(AND3)和第四与门(AND4)。其中,该参考时钟对应的触发器可包括:触发器D11、触发器D12、触发器D15及触发器D16;该待测时钟对应的触发器可包括:触发器D13、触发器D14、触发器D17、触发器D18。The response synchronization circuit 56 includes a flip-flop corresponding to a reference clock, a flip-flop corresponding to a clock to be tested, a third AND gate (AND3), and a fourth AND gate (AND4). The trigger corresponding to the reference clock may include: trigger D11, trigger D12, trigger D15, and trigger D16; the trigger corresponding to the clock to be tested may include: trigger D13, trigger D14, trigger D17 Trigger D18.
参考时钟的时钟信号clk_ref输入至响应同步电路56中的参考时钟对应 的触发器,即触发器D11、触发器D12、触发器D15及触发器D16。The clock signal clk_ref of the reference clock is input to flip-flops corresponding to the reference clock in the response synchronization circuit 56, that is, flip-flop D11, flip-flop D12, flip-flop D15, and flip-flop D16.
待测时钟的时钟信号clk_test输入至响应同步电路56中待测时钟对应的触发器,即触发器D13、触发器D14、触发器D17、触发器D18。The clock signal clk_test of the clock to be tested is input to flip-flops corresponding to the clock to be tested in the response synchronization circuit 56, that is, flip-flop D13, flip-flop D14, flip-flop D17, and flip-flop D18.
若上述图5中计数器2停止计数后的计数值小于预设的计数上限值,且,该计数值大于该预设的计数下限值,则比较电路53输出清零信号clear至响应同步电路56。由该响应同步电路56可根据该参考时钟的时钟信号将清零信号进行同步至参考时钟的时钟信号对应的时钟域,得到该参考时钟的时钟信号对应的时钟域的清零信号clear_ref,并输出信号至计数器1的CLR端口,使得计数器1将计数值清零,实现计数初始化。该响应电路56可根据该待测时钟的时钟信号将清零信号同步至待测时钟的时钟信号对应的时钟域,得到该待测时钟的时钟信号对应的时钟域的清零信号clear_test,并输出信号至计数器2的CLR端口,使得计数器2将计数值清零,实现计数初始化。If the count value after the counter 2 stops counting in FIG. 5 is smaller than the preset upper limit value, and the count value is greater than the preset lower limit value, the comparison circuit 53 outputs a clear signal clear to the response synchronization circuit. 56. The response synchronization circuit 56 can synchronize the clear signal to the clock domain corresponding to the clock signal of the reference clock according to the clock signal of the reference clock, obtain the clear signal of the clock domain clear_ref corresponding to the clock signal of the reference clock, and output Signal to the CLR port of counter 1, so that counter 1 clears the count value to zero and initializes the count. The response circuit 56 may synchronize the clear signal to the clock domain corresponding to the clock signal of the clock to be tested according to the clock signal of the clock to be tested, obtain the clear signal test_clear_test of the clock domain corresponding to the clock signal of the clock to be tested, and output The signal is sent to the CLR port of the counter 2, so that the counter 2 clears the count value to realize the count initialization.
具体地,比较电路53可将清零信号clear,输入至触发器11的D端口及触发器13的D端口。Specifically, the comparison circuit 53 may input a clear signal clear to the D port of the flip-flop 11 and the D port of the flip-flop 13.
该参考时钟的时钟信号还输入至触发器D11、触发器D12、触发器D15以及触发器16。该待测时钟的时钟信号还输入至触发器D13、触发器D14、触发器D17以及触发器18。The clock signal of the reference clock is also input to the flip-flop D11, the flip-flop D12, the flip-flop D15, and the flip-flop 16. The clock signal of the clock to be tested is also input to the flip-flop D13, the flip-flop D14, the flip-flop D17, and the flip-flop 18.
触发器D11与触发器D12连接。触发器D11用于在该参考时钟的时钟信号的作用下对该清零信号进行处理,并输出信号至触发器D12。触发器D11可通过Q端口,将触发器D11的输出信号传输至触发器D12的D端口。The flip-flop D11 is connected to the flip-flop D12. The flip-flop D11 is used to process the clear signal under the action of the clock signal of the reference clock, and output a signal to the flip-flop D12. The flip-flop D11 can transmit the output signal of the flip-flop D11 to the D-port of the flip-flop D12 through the Q port.
触发器D12还与触发器D17和第三与门AND3连接,触发器D1用于在该参考时钟的时钟信号对触发器D11的输出信号的作用下进行处理,并输出信号至触发器D17和第三与门AND3。触发器D12可通过Q端口将触发器D12的输出信号传输至触发器D17的D端口和第三与门AND3。The flip-flop D12 is also connected to the flip-flop D17 and the third AND gate AND3. The flip-flop D1 is used to process the output signal of the flip-flop D11 under the clock signal of the reference clock, and output the signal to the flip-flop D17 and the Three AND gates AND3. The flip-flop D12 can transmit the output signal of the flip-flop D12 to the D port of the flip-flop D17 and the third AND gate AND3 through the Q port.
触发器D13与触发器D14连接。触发器D13用于在该待测时钟的时钟信号的作用下对该清零信号进行处理,并输出信号至触发器D14。触发器D13可通过Q端口,将触发器D13的输出信号传输至触发器D14的D端口。The flip-flop D13 is connected to the flip-flop D14. The flip-flop D13 is used to process the clear signal under the function of the clock signal of the clock to be tested, and output a signal to the flip-flop D14. The flip-flop D13 can transmit the output signal of the flip-flop D13 to the D port of the flip-flop D14 through the Q port.
触发器D14还与触发器D15和第四与门AND4连接。触发器D4用于在该待测时钟的时钟信号的作用下对触发器D13的输出信号进行处理,并输出信号至触发器D15和第四与门AND4。触发器D14可通过Q端口将触发器 14的输出信号传输至触发器D15的D端口和第四与门AND4。Flip-flop D14 is also connected to flip-flop D15 and a fourth AND gate AND4. The flip-flop D4 is used to process the output signal of the flip-flop D13 under the action of the clock signal of the clock to be tested, and output the signal to the flip-flop D15 and the fourth AND gate AND4. The flip-flop D14 can transmit the output signal of the flip-flop 14 to the D port of the flip-flop D15 and the fourth AND gate AND4 through the Q port.
触发器D15,用于在该参考时钟的时钟信号的作用下对触发器D14的输出信号进行处理,并输出信号至触发器D16。触发器D15可通过Q端口将触发器D15的输出信号传输至触发器D16的D端口。The flip-flop D15 is configured to process an output signal of the flip-flop D14 under the action of the clock signal of the reference clock, and output the signal to the flip-flop D16. The flip-flop D15 can transmit the output signal of the flip-flop D15 to the D port of the flip-flop D16 through the Q port.
触发器D16,用于在该参考时钟的时钟信号的作用下对触发器D15的输出信号进行处理,并输出信号至第三与门AND3。触发器D16可通过Q端口还将触发器D16的输出信号传输至第三与门AND3。The flip-flop D16 is configured to process an output signal of the flip-flop D15 under the action of the clock signal of the reference clock, and output the signal to the third AND gate AND3. The flip-flop D16 can also transmit the output signal of the flip-flop D16 to the third AND gate AND3 through the Q port.
触发器D17,用于在该待测时钟的时钟信号的作用下对触发器D12的输出信号进行处理,并输出信号至触发器D18。触发器D17可Q端口将触发器D17的输出信号传输至触发器D18的D端口。The flip-flop D17 is configured to process an output signal of the flip-flop D12 under the action of the clock signal of the clock to be measured, and output a signal to the flip-flop D18. The flip-flop D17 can transmit the output signal of the flip-flop D17 to the D-port of the flip-flop D18 through the Q port.
触发器D18,用于在该待测时钟的时钟信号的作用下对触发器D17的输出信号进行处理,并输出信号至第四与门AND4。触发器D18可通过Q端口将触发器D18的输出信号传输至第四与门AND4。The flip-flop D18 is configured to process an output signal of the flip-flop D17 under the action of the clock signal of the clock to be measured, and output a signal to the fourth AND gate AND4. The flip-flop D18 can transmit the output signal of the flip-flop D18 to the fourth AND gate AND4 through the Q port.
第三与门AND3用于对触发器D12的输出信号和触发器D16的输出信号,进行与逻辑处理,并输出信号至该参考时钟对应的计数器,即计数器1。第三与门AND3的输出信号可输出至计数器1的CLR端口,使得计数器1将计数值清零。第三与门AND3输出的信号即为该参考时钟的时钟信号对应的时钟域的清零信号clear_ref。The third AND gate AND3 is used to perform AND logic processing on the output signal of the flip-flop D12 and the output signal of the flip-flop D16, and output the signal to the counter corresponding to the reference clock, namely, the counter 1. The output signal of the third AND gate AND3 can be output to the CLR port of the counter 1, so that the counter 1 clears the count value to zero. The signal output by the third AND gate AND3 is the clear signal ref_ref of the clock domain corresponding to the clock signal of the reference clock.
第四与门AND4用于对触发器D14输出的信号和触发器D18输出的信号,进行与逻辑处理,并输出信号至该待测时钟对应的计数器,即计数器2。第四与门AND4的输出信号可输出至计数器2的CLR端口,使得计数器2将计数值清零。第四与门AND4输出的信号即为输出该待测时钟的时钟信号对应的时钟域的清零信号clear_test。The fourth AND gate AND4 is used to perform AND logic processing on the signal output from the flip-flop D14 and the signal output from the flip-flop D18, and output the signal to the counter corresponding to the clock to be tested, namely, the counter 2. The output signal of the fourth AND gate AND4 can be output to the CLR port of the counter 2, so that the counter 2 clears the count value to zero. The signal output by the fourth AND gate AND4 is the clear signal of the clock domain clear_test corresponding to the clock signal outputting the clock to be tested.
该实施例提供的检测电路,可实现时钟信号的准确检测,有效保证数据安全,避免数据泄露;并且参考时钟与待测时钟各自独立,其对应的计数器也各自独立,参考时钟与待测时钟的频率和/或相位之间不存在对应关系,不存在约束关系,可有效避免参考时钟被攻击导致的待测时钟的频率检测不准确,提高时钟信号的频率检测的准确度;待测时钟的计数器的计数值具有上下限值,即该待测时钟的计数器的计数值具有一定的容差范围,这使得待测时钟的频率可具有一定的容差范围,可有效避免时钟抖动、时钟偏移或其它 工艺引入的误差,精度灵活可控。同时,信号走线采用低层金属走线,有效增加了攻击难度,有效避免走线被攻击带来的风险。比较结果的多次延时比较,保证检测到的时钟信号的频率的可靠性。The detection circuit provided in this embodiment can accurately detect the clock signal, effectively ensure data security, and avoid data leakage; and the reference clock and the clock to be measured are independent, and their corresponding counters are also independent. There is no corresponding relationship between frequencies and / or phases, and there is no constraint relationship, which can effectively avoid the inaccurate frequency detection of the clock to be tested caused by the reference clock being attacked, and improve the accuracy of the frequency detection of the clock signal; the counter of the clock to be tested The count value of has a lower and upper limit value, that is, the count value of the counter of the clock to be tested has a certain tolerance range, which allows the frequency of the clock to be tested to have a certain tolerance range, which can effectively avoid clock jitter, clock offset, or The errors introduced by other processes are flexible and controllable. At the same time, the signal wiring uses low-level metal wiring, which effectively increases the difficulty of the attack and effectively avoids the risk of being attacked by the wiring. Multiple delay comparisons of the comparison result ensure the reliability of the frequency of the detected clock signal.
为使得本申请上述实施例提供的检测电路有序的工作,该检测电路可具有多个状态,可表示该检测电路的多个状态之间的关系,可表示为该检测电路的状态机。图7为本申请实施例提供的一种检测电路的状态机的示意图。如图7所示,该检测电路包括空闲态、计数态、比较态、清零态及错误态。In order to make the detection circuit provided by the above embodiments of the present application work in an orderly manner, the detection circuit may have multiple states, may indicate a relationship between the multiple states of the detection circuit, and may be expressed as a state machine of the detection circuit. FIG. 7 is a schematic diagram of a state machine of a detection circuit according to an embodiment of the present application. As shown in FIG. 7, the detection circuit includes an idle state, a count state, a comparison state, a clear state, and an error state.
该检测电路处于空闲态,检测电路等待使能信号,若使能信号有效,则检测电路可进入计数态。The detection circuit is in an idle state. The detection circuit waits for an enable signal. If the enable signal is valid, the detection circuit can enter a counting state.
在计数态下,在计数器的计数值未满的情况下,计数器在各自时钟信号的驱动下,对各自时钟信号的上升沿或下降沿进行计数,一个上升沿或一个下降沿,计数器的计数值便加一。若参考时钟对应的计数器的计数值满的情况下,且,待测时钟对应的计数器停止计数后,则检测电路进入比较态。In the counting state, when the count value of the counter is not full, the counter counts the rising or falling edge of the respective clock signal under the driving of the respective clock signal. One rising or one falling edge, the counter's count value Plus one. If the count value of the counter corresponding to the reference clock is full, and after the counter corresponding to the clock to be measured stops counting, the detection circuit enters a comparison state.
在比较态下,比较模块或比较电路将待测时钟对应的计数器在停止计数后的计数值与预设的计数上限及预设计数下限进行比较,得到比较结果。若待测时钟对应的计数器在停止计数后的计数值小于预设的计数上限,且,该计数值大于预设计数下限值时,进入清零态。若待测时钟对应的计数器在停止计数后的计数值大于或等于预设的计数上限,或者,该计数值小于或等于预设计数下限值时,发出报警信号进入错误态。In the comparison state, the comparison module or the comparison circuit compares the count value of the counter corresponding to the clock to be measured after the counting is stopped with the preset upper limit and the preset lower limit to obtain a comparison result. If the count value of the counter corresponding to the clock to be measured after stopping counting is smaller than the preset upper limit, and when the count value is greater than the preset lower limit, it enters a clear state. If the count value of the counter corresponding to the clock to be measured after stopping counting is greater than or equal to the preset upper count limit, or when the count value is less than or equal to the preset lower count limit, an alarm signal is issued to enter an error state.
在错误态下,响应电路或响应模块可根据比较电路或比较模块输出的第三控制信号又称报警信号输出不同的信号,从而进入不同的状态。若响应电路或响应模块输出状态标志位或中断信号,可在中断处理函数中进行相关处理后发出错误清零信号,检测电路进入清零态。若响应电路或响应模块输出复位信号,则检测电路进入空闲态。In the error state, the response circuit or the response module can output different signals according to the third control signal or alarm signal output by the comparison circuit or the comparison module, thereby entering different states. If the response circuit or the response module outputs a status flag or an interrupt signal, an error clear signal can be issued after the relevant processing in the interrupt processing function, and the detection circuit enters the clear state. If the response circuit or the response module outputs a reset signal, the detection circuit enters an idle state.
在清零态下,待测时钟信号对应的计数器的计数值可在预设计数范围内,则对计数器的计数值进行清零后,使得检测电路再次进入计数态。In the cleared state, the count value of the counter corresponding to the clock signal to be measured can be within a preset count range. After the count value of the counter is cleared, the detection circuit enters the count state again.
本申请实施例还提供一种芯片。图8为本申请实施例提供的一种芯片的结构示意图。如图8所示,该芯片80可包括:检测电路81,检测电路81可 以为上述图1至图6中任一所示的检测电路。该检测电路与芯片内的多个时钟电路分别连接,用以接收该多个时钟电路所产生的多路时钟信号。其中,每个时钟电路可产生一路时钟信号,则多个时钟电路便可产生多个时钟信号。An embodiment of the present application further provides a chip. FIG. 8 is a schematic structural diagram of a chip according to an embodiment of the present application. As shown in FIG. 8, the chip 80 may include a detection circuit 81, and the detection circuit 81 may be any one of the detection circuits shown in FIGS. 1 to 6 described above. The detection circuit is respectively connected to a plurality of clock circuits in the chip, and is used for receiving multiple clock signals generated by the plurality of clock circuits. Wherein, each clock circuit can generate one clock signal, and then multiple clock circuits can generate multiple clock signals.
该芯片包括有上述任一所述的检测电路,其具体描述及有益效果参见上述,在此不再赘述。This chip includes any one of the above-mentioned detection circuits. For the detailed description and beneficial effects, refer to the above description, which will not be repeated here.
本申请实施例还提供一种电子设备。图9为本申请实施例提供的一种电子设备的结构示意图。如图9所示,电子设备90可包括:芯片91,芯片91包括检测电路92,该检测电路92可为上述图1至图6中任一所示的检测电路。检测电路92可与芯片91上的多个时钟电路分别连接,用以接收该多个时钟电路所产生的多路时钟信号。其中,每个时钟电路可产生一路时钟信号,则多个时钟电路便可产生多个时钟信号。An embodiment of the present application further provides an electronic device. FIG. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in FIG. 9, the electronic device 90 may include a chip 91 that includes a detection circuit 92. The detection circuit 92 may be any one of the detection circuits shown in FIG. 1 to FIG. 6. The detection circuit 92 may be respectively connected to a plurality of clock circuits on the chip 91 and configured to receive multiple clock signals generated by the plurality of clock circuits. Wherein, each clock circuit can generate one clock signal, and then multiple clock circuits can generate multiple clock signals.
该电子设备所包括的芯片包括有上述任一所述的检测电路,其具体描述及有益效果参见上述,在此不再赘述。The chip included in the electronic device includes any one of the detection circuits described above. For a detailed description and beneficial effects, refer to the foregoing, and details are not described herein again.
本申请实施例提供一种检测方法。该检测方法适用于上述任一所述的检测电路,用以检测时钟信号的频率。该检测电路包括同步模块和检测模块。图10为本申请实施例提供的一种检测方法的流程图。如图10所示,该方法可包括:The embodiment of the present application provides a detection method. The detection method is applicable to any one of the detection circuits described above, and is used to detect the frequency of a clock signal. The detection circuit includes a synchronization module and a detection module. FIG. 10 is a flowchart of a detection method according to an embodiment of the present application. As shown in FIG. 10, the method may include:
S1001、同步模块根据多路时钟信号中的每路时钟信号,将接收到的使能信号同步至该每路时钟信号的时钟域,以得到该每路时钟信号的时钟域对应的使能信号并传输至该检测模块。S1001. The synchronization module synchronizes the received enable signal to the clock domain of each clock signal according to each of the multiple clock signals to obtain the enable signal corresponding to the clock domain of each clock signal. Transfer to the detection module.
S1002、检测模块在该每路时钟信号的时钟域对应的使能信号的作用下,对所述每路时钟信号进行检测,得到该每路时钟信号的频率。S1002. The detection module detects each clock signal under the function of an enable signal corresponding to the clock domain of each clock signal to obtain the frequency of each clock signal.
可选的,该检测模块包括:多个计数器;每个计数器对应多路时钟信号中的一路时钟信号。上述检测方法中S1001中将同步后的该每路时钟信号的时钟域对应的使能信号传输至该检测模块可包括:Optionally, the detection module includes: a plurality of counters; each counter corresponds to one of a plurality of clock signals. In the above detection method, transmitting the enable signal corresponding to the clock domain of each clock signal after synchronization to the detection module in S1001 may include:
同步模块将该每路时钟信号的时钟域对应的使能信号传输至该每路信号对应的计数器。The synchronization module transmits an enable signal corresponding to a clock domain of each clock signal to a counter corresponding to each signal.
对应的,S1002中检测模块在该每路时钟信号的时钟域对应的使能信号 的作用下,对所述每路时钟信号进行检测,得到该每路时钟信号的频率可包括:Correspondingly, the detection module in S1002 detects each clock signal under the function of the enable signal corresponding to the clock domain of each clock signal, and the frequency of each clock signal may include:
该每路时钟信号对应的计数器在该每路时钟信号的时钟域对应的使能信号的作用下,对该每路时钟信号的上升沿或下降沿进行计数,得到该每路时钟信号对应的计数值,该每路时钟信号对应的计数值用于表征该每路时钟信号的频率。The counter corresponding to each clock signal counts the rising or falling edge of each clock signal under the function of the enable signal corresponding to the clock domain of each clock signal to obtain the count corresponding to each clock signal Value, the count value corresponding to each clock signal is used to characterize the frequency of each clock signal.
可选的,该多个计数器包括参考时钟对应的计数器,和至少一个待测时钟对应的计数器;该检测模块还包括:比较电路。Optionally, the multiple counters include a counter corresponding to a reference clock and a counter corresponding to at least one clock to be tested; the detection module further includes a comparison circuit.
该方法还可包括:The method may further include:
当该参考时钟对应的计数器的计数值达到第一预设数值,向该每个计数器传输第一控制信号;Transmitting a first control signal to each counter when the count value of the counter corresponding to the reference clock reaches a first preset value;
该每个计数器根据该第一控制信号停止计数。Each counter stops counting according to the first control signal.
可选的,检测模块还包括:比较电路。Optionally, the detection module further includes: a comparison circuit.
该方法还可包括:The method may further include:
该比较电路对该每个待测时钟对应的计数器在停止计数时的计数值和预设的计数上限值和/或预设的计数下限值进行比较,得到比较结果。The comparison circuit compares the count value of the counter corresponding to each clock to be measured when the counting is stopped with a preset upper limit value and / or a preset lower limit value to obtain a comparison result.
可选的,该方法还可包括:Optionally, the method may further include:
若该每个待测时钟对应的计数器在停止计数时的计数值小于该预设的计数上限值,且,该计数值大于该预设的计数下限值,该比较电路输出第二控制信号至该待测时钟对应的计数器和该参考时钟对应的计数器;If the count value of the counter corresponding to each clock under test stops counting is less than the preset upper limit value, and the count value is greater than the preset lower limit value, the comparison circuit outputs a second control signal. To the counter corresponding to the clock to be tested and the counter corresponding to the reference clock;
该待测时钟对应的计数器和该参考时钟对应的计数器根据该第二控制信号进行初始化。The counter corresponding to the clock to be measured and the counter corresponding to the reference clock are initialized according to the second control signal.
可选的,该检测电路还包括:响应模块;Optionally, the detection circuit further includes: a response module;
该方法还可包括:The method may further include:
若该每个待测时钟对应的计数器在停止计数时的计数值大于或等于该预设的计数上限值,或者,该计数值小于或等于该预设的计数下限值,该比较电路传输第三控制信号至该响应模块;If the count value of the counter corresponding to each clock under test stops counting is greater than or equal to the preset upper limit value, or the count value is less than or equal to the preset lower limit value, the comparison circuit transmits A third control signal to the response module;
该响应模块根据该第三控制信号输出中断信号、擦除信号或者复位信号中的任一信号。The response module outputs any one of an interrupt signal, an erase signal, or a reset signal according to the third control signal.
该检测方法可由上述检测电路执行,其具体实现过程及有益效果参见上 述,在此不再赘述。This detection method can be executed by the above detection circuit. For the specific implementation process and beneficial effects, refer to the above description, which will not be repeated here.
本领域普通技术人员可以理解:实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成,前述的程序可以存储于一计算机可读取存储介质中,该程序在执行时,执行包括上述方法实施例的步骤;而前述的存储介质包括:ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。A person of ordinary skill in the art may understand that all or part of the steps of the foregoing method embodiments may be completed by a program instructing related hardware. The foregoing program may be stored in a computer-readable storage medium. When the program is executed, the program is executed. The method includes the steps of the foregoing method embodiment; and the foregoing storage medium includes: a ROM, a RAM, a magnetic disk, or an optical disc, which can store various program codes.
最后应说明的是:以上各实施例仅用以说明本申请的技术方案,而非对其限制;尽管参照前述各实施例对本申请进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。Finally, it should be noted that the above embodiments are only used to describe the technical solution of the present application, rather than limiting it. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: The technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features are equivalently replaced; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present application. range.

Claims (20)

  1. 一种检测电路,其特征在于,包括:A detection circuit, comprising:
    同步模块和检测模块;所述同步模块与所述检测模块连接;A synchronization module and a detection module; the synchronization module is connected to the detection module;
    所述同步模块,用于根据多路时钟信号中的每路时钟信号,将接收到的使能信号同步至所述每路时钟信号的时钟域,以得到所述每路时钟信号的时钟域对应的使能信号并传输至所述检测模块;The synchronization module is configured to synchronize the received enable signal to a clock domain of each clock signal according to each of the multiple clock signals, so as to obtain a clock domain corresponding to each clock signal. The enable signal and transmit it to the detection module;
    所述检测模块,用于在所述每路时钟信号的时钟域对应的使能信号的作用下,对所述每路时钟信号进行检测,得到所述每路时钟信号的频率。The detection module is configured to detect each clock signal under the function of an enable signal corresponding to a clock domain of each clock signal to obtain a frequency of each clock signal.
  2. 根据权利要求1所述的电路,其特征在于,所述同步模块从使能模块接收所述使能信号,所述同步模块与所述使能模块之间连接有传输所述使能信号的多条走线。The circuit according to claim 1, wherein the synchronization module receives the enable signal from an enable module, and a connection between the synchronization module and the enable module is provided for transmitting the enable signal. Lines.
  3. 根据权利要求2所述的电路,其特征在于,所述传输所述使能信号的多条走线为芯片内的低层金属走线。The circuit according to claim 2, wherein the plurality of traces transmitting the enable signal are low-level metal traces in a chip.
  4. 根据权利要求1-3中任一项所述的电路,其特征在于,所述检测模块包括:多个计数器,每个计数器对应多路时钟信号中的一路时钟信号;所述同步模块与所述每个计数器连接;The circuit according to any one of claims 1-3, wherein the detection module comprises: a plurality of counters, each counter corresponding to one of a plurality of clock signals; the synchronization module and the Each counter is connected;
    所述同步模块,用于将所述每路时钟信号的时钟域对应的使能信号传输至所述每路时钟信号对应的计数器;The synchronization module is configured to transmit an enable signal corresponding to a clock domain of each clock signal to a counter corresponding to each clock signal;
    所述每路时钟信号对应的计数器,用于在所述路时钟信号的时钟域对应的使能信号的作用下,对所述路时钟信号的上升沿或下降沿进行计数,得到所述路时钟信号对应的计数值,所述路时钟信号对应的计数值用于表征所述路时钟信号的频率。The counter corresponding to each clock signal is used to count the rising or falling edge of the clock signal under the function of the enable signal corresponding to the clock domain of the clock signal to obtain the clock of the channel. The count value corresponding to the signal, and the count value corresponding to the clock signal is used to characterize the frequency of the clock signal.
  5. 根据权利要求4所述的电路,其特征在于,所述多个计数器包括参考时钟对应的计数器,和至少一个待测时钟对应的计数器,所述参考时钟对应的计数器与所述待测时钟对应的计数器连接;The circuit according to claim 4, wherein the plurality of counters include a counter corresponding to a reference clock, and a counter corresponding to at least one clock to be measured, and the counter corresponding to the reference clock corresponds to the clock to be measured Counter connection
    所述参考时钟对应的计数器用于:当所述参考时钟对应的计数器的计数值达到预设数值,向所述待测时钟对应的计数器传输第一控制信号;The counter corresponding to the reference clock is configured to: when the count value of the counter corresponding to the reference clock reaches a preset value, transmit a first control signal to the counter corresponding to the clock to be measured;
    所述待测时钟对应的计数器,用于根据第一控制信号停止计数。The counter corresponding to the clock to be measured is used to stop counting according to the first control signal.
  6. 根据权利要求5所述的电路,其特征在于,所述检测模块还包括比较电路,所述比较电路与所述待测时钟对应的计数器连接;The circuit according to claim 5, wherein the detection module further comprises a comparison circuit, and the comparison circuit is connected to a counter corresponding to the clock to be measured;
    所述比较电路用于对所述待测时钟对应的计数器在停止计数时的计数值和预设的计数上限值和/或预设的计数下限值进行比较,得到比较结果。The comparison circuit is configured to compare the count value of the counter corresponding to the clock to be measured when the counting is stopped with a preset upper limit value and / or a preset lower limit value to obtain a comparison result.
  7. 根据权利要求6所述的电路,其特征在于,所述比较电路还与所述参考时钟对应的计数器连接;The circuit according to claim 6, wherein the comparison circuit is further connected to a counter corresponding to the reference clock;
    所述比较电路还用于:若所述待测时钟对应的计数器在停止计数时的计数值小于所述预设的计数上限值,且,所述计数值大于所述预设的计数下限值,则输出第二控制信号至所述待测时钟对应的计数器和所述参考时钟对应的计数器;The comparison circuit is further configured to: if the count value of the counter corresponding to the clock to be measured stops counting is less than the preset upper limit value, and the count value is greater than the preset lower limit value Value, output a second control signal to a counter corresponding to the clock to be measured and a counter corresponding to the reference clock;
    所述待测时钟对应的计数器和所述参考时钟对应的计数器,用于根据所述第二控制信号进行初始化。The counter corresponding to the clock to be measured and the counter corresponding to the reference clock are used for initialization according to the second control signal.
  8. 根据权利要求6所述的电路,其特征在于,所述检测电路还包括:响应模块,所述响应模块与所述比较电路连接;The circuit according to claim 6, wherein the detection circuit further comprises: a response module, the response module being connected to the comparison circuit;
    所述比较电路,还用于:若所述每个待测时钟对应的计数器在停止计数时的计数值大于或等于所述预设的计数上限值,或者,所述计数值小于或等于所述预设的计数下限值,输出第三控制信号至所述响应模块;The comparison circuit is further configured to: if the count value of the counter corresponding to each clock to be measured at the time of stopping counting is greater than or equal to the preset upper count value, or the count value is less than or equal to the preset count value The preset count lower limit value, and output a third control signal to the response module;
    所述响应模块用于根据所述第三控制信号输出中断信号、擦除信号或者复位信号中的任一信号。The response module is configured to output any one of an interrupt signal, an erase signal, or a reset signal according to the third control signal.
  9. 根据权利要求8所述的电路,其特征在于,所述比较电路与所述响应模块之间连接有传输所述第三控制信号的多条走线。The circuit according to claim 8, wherein a plurality of traces transmitting the third control signal are connected between the comparison circuit and the response module.
  10. 根据权利要求9所述的电路,其特征在于,所述传输所述第三控制信号的多条走线为芯片内的低层金属信号走线。The circuit according to claim 9, wherein the plurality of traces transmitting the third control signal are low-level metal signal traces in a chip.
  11. 根据权利要求5所述的电路,其特征在于,所述同步模块包括:所述参考时钟对应的多个触发器、所述待测时钟对应的多个触发器、第一与门、第二与门;所述参考时钟对应的多个触发器包括:第一触发器、第二触发器、第五触发器和第六触发器;所述待测时钟对应的多个触发器包括:第三触发器、第四触发器、第七触发器、第八触发器;The circuit according to claim 5, wherein the synchronization module comprises: a plurality of flip-flops corresponding to the reference clock, a plurality of flip-flops corresponding to the clock to be tested, a first AND gate, and a second AND Gate; multiple triggers corresponding to the reference clock include: first, second, fifth, and sixth triggers; multiple triggers corresponding to the clock to be tested include: third trigger Device, fourth trigger, seventh trigger, eighth trigger;
    所述第一触发器与所述第二触发器连接,所述第一触发器用于接收所述使能信号以及所述参考时钟的时钟信号,并在所述参考时钟的时钟信号的作用下对所述使能信号进行处理,并输出信号至所述第二触发器;The first flip-flop is connected to the second flip-flop, and the first flip-flop is configured to receive the enable signal and a clock signal of the reference clock, and to react to the clock signal of the reference clock Processing the enable signal and outputting the signal to the second trigger;
    所述第二触发器还与所述第七触发器和所述第一与门连接,所述第二触 发器用于接收所述第一触发器的输出信号以及所述参考时钟的时钟信号,并在所述参考时钟的时钟信号的作用下对所述第一触发器的输出信号进行处理,并输出信号至所述第七触发器和所述第一与门;The second flip-flop is also connected to the seventh flip-flop and the first AND gate, and the second flip-flop is configured to receive an output signal of the first flip-flop and a clock signal of the reference clock, and Processing an output signal of the first flip-flop under the function of a clock signal of the reference clock, and outputting a signal to the seventh flip-flop and the first AND gate;
    所述第三触发器与所述第四触发器连接,所述第三触发器用于接收所述使能信号以及所述待测时钟的时钟信号,并在所述待测时钟的时钟信号的作用下对所述使能信号进行处理,并输出信号至第四触发器;The third flip-flop is connected to the fourth flip-flop, and the third flip-flop is configured to receive the enable signal and a clock signal of the clock to be tested, and play a role in the clock signal of the clock to be tested Processing the enable signal and outputting the signal to a fourth trigger;
    所述第四触发器还与所述第五触发器和所述第二与门连接,所述第四触发器用于接收所述第三触发器的输出信号以及所述待测时钟的时钟信号,在所述待测时钟的时钟信号的作用下对所述第三触发器的输出信号进行处理,并输出信号至所述第五触发器和所述第二与门;The fourth flip-flop is further connected to the fifth flip-flop and the second AND gate, and the fourth flip-flop is configured to receive an output signal of the third flip-flop and a clock signal of the clock to be tested, Processing an output signal of the third flip-flop under the function of a clock signal of the clock to be tested, and outputting a signal to the fifth flip-flop and the second AND gate;
    所述第五触发器,用于接收所述第四触发器的输出信号以及所述参考时钟的时钟信号,并在所述参考时钟的时钟信号的作用下对所述第四触发器的输出信号进行处理,并输出信号至所述第六触发器;The fifth flip-flop is configured to receive an output signal of the fourth flip-flop and a clock signal of the reference clock, and output an output signal of the fourth flip-flop under the action of the clock signal of the reference clock. Perform processing, and output a signal to the sixth trigger;
    所述第六触发器,用于接收所述第五触发器的输出信号以及所述参考时钟的时钟信号,并在所述参考时钟的时钟信号的作用下对所述第五触发器的输出信号进行处理,并输出信号至所述第一与门;The sixth flip-flop is configured to receive an output signal of the fifth flip-flop and a clock signal of the reference clock, and output an output signal of the fifth flip-flop under the action of the clock signal of the reference clock. Perform processing, and output a signal to the first AND gate;
    所述第七触发器,用于接收所述第二触发器的输出信号以及所述待测时钟的时钟信号,并在所述待测时钟的时钟信号的作用下对所述第二触发器的输出信号进行处理,并输出信号至所述第八触发器;The seventh flip-flop is configured to receive an output signal of the second flip-flop and a clock signal of the clock to be tested, and perform an operation on the second flip-flop under the action of the clock signal of the clock to be tested. Outputting signals for processing, and outputting signals to the eighth trigger;
    所述第八触发器,用于接收所述第七触发器的输出信号以及所述待测时钟的时钟信号,并在所述待测时钟的时钟信号作用下对所述第七触发器的输出信号的进行处理,并输出信号至所述第二与门;The eighth flip-flop is configured to receive an output signal of the seventh flip-flop and a clock signal of the clock to be tested, and output the seventh flip-flop to the clock signal of the clock to be tested. Processing the signals and outputting the signals to the second AND gate;
    所述第一与门,用于对所述第二触发器的输出信号,和所述第六触发器的输出信号进行与逻辑处理,并输出信号至所述参考时钟对应的计数器;The first AND gate is configured to perform AND logic processing on an output signal of the second flip-flop and an output signal of the sixth flip-flop, and output a signal to a counter corresponding to the reference clock;
    所述第二与门,用于对所述第四触发器的输出信号,和所述第八触发器的输出信号进行与逻辑处理,并输出信号至所述待测时钟对应的计数器。The second AND gate is configured to perform AND logic processing on an output signal of the fourth flip-flop and an output signal of the eighth flip-flop, and output a signal to a counter corresponding to the clock to be measured.
  12. 根据权利要求11所述的电路,其特征在于,所述同步模块还包括:反相器;所述待测时钟对应的多个触发器,还包括:第九触发器和第十触发器;The circuit according to claim 11, wherein the synchronization module further comprises: an inverter; a plurality of flip-flops corresponding to the clock to be tested, further comprising: a ninth flip-flop and a tenth flip-flop;
    所述反相器分别与所述参考时钟对应的计数器、所述第一与门和所述第 十触发器连接;所述反相器,用于对所述参考时钟对应的计数器的输出信号进行反相处理后,并输出信号至所述第一与门和所述第十触发器;The inverter is respectively connected to a counter corresponding to the reference clock, the first AND gate, and the tenth flip-flop; and the inverter is configured to perform an output signal of the counter corresponding to the reference clock After inversion processing, and outputting signals to the first AND gate and the tenth flip-flop;
    所述第一与门,具体用于对所述第二触发器的输出信号、所述第六触发器的输出信号以及所述反相器的输出信号进行与逻辑处理,并输出信号至所述参考时钟对应的计数器;The first AND gate is specifically configured to perform AND logic processing on an output signal of the second flip-flop, an output signal of the sixth flip-flop, and an output signal of the inverter, and output a signal to the Counter corresponding to the reference clock;
    所述第九触发器分别与所述第十触发器和所述第二与门连接;所述第十触发器用于接收所述反相器的输出信号以及所述待测时钟的时钟信号,并在所述待测时钟的时钟信号的作用下对所述反相器的输出信号进行处理,并输出信号至所述第九触发器;The ninth flip-flop is connected to the tenth flip-flop and the second AND gate, respectively; the tenth flip-flop is configured to receive an output signal of the inverter and a clock signal of the clock to be tested, and Processing an output signal of the inverter under a function of a clock signal of the clock to be tested, and outputting the signal to the ninth flip-flop;
    所述第九触发器用于接收所述第十触发器的输出信号以及所述待测时钟的时钟信号,并在所述待测时钟的时钟信号的作用下对所述第十触发器的输出信号进行处理,并输出信号至所述第二与门;The ninth flip-flop is configured to receive an output signal of the tenth flip-flop and a clock signal of the clock to be tested, and output an output signal of the tenth flip-flop under the action of the clock signal of the clock to be tested. Perform processing, and output a signal to the second AND gate;
    所述第二与门,具体用于对所述第四触发器的输出信号、所述第八触发器的输出信号以及所述第九触发器的输出信号进行与处理,并输出信号至所述待测时钟对应的计数器。The second AND gate is specifically configured to AND process an output signal of the fourth flip-flop, an output signal of the eighth flip-flop, and an output signal of the ninth flip-flop, and output a signal to the Counter corresponding to the clock under test.
  13. 一种芯片,其特征在于,包括:上述权利要求1-12中任一项所述的检测电路。A chip, comprising: the detection circuit according to any one of claims 1-12.
  14. 一种电子设备,其特征在于,包括:具有上述权利要求1-12中任一项所述的检测电路的芯片。An electronic device, comprising: a chip having the detection circuit according to any one of claims 1-12.
  15. 一种检测方法,其特征在于,所述检测方法适用于检测电路,所述检测电路包括同步模块和检测模块;所述方法包括:A detection method, wherein the detection method is applicable to a detection circuit, the detection circuit includes a synchronization module and a detection module, and the method includes:
    所述同步模块根据多路时钟信号中的每路时钟信号,将接收到的使能信号同步至所述每路时钟信号的时钟域,以得到的所述每路时钟信号的时钟域对应的使能信号并传输至所述检测模块;The synchronization module synchronizes the received enable signal to the clock domain of each clock signal according to each of the multiple clock signals, so as to obtain the corresponding clock domain of each clock signal. Energy signals and transmission to the detection module;
    所述检测模块在所述每路时钟信号的时钟域对应的使能信号的作用下,对所述每路时钟信号进行检测,得到所述每路时钟信号的频率。The detection module detects each clock signal under the function of an enable signal corresponding to a clock domain of each clock signal to obtain a frequency of each clock signal.
  16. 根据权利要求15所述的方法,其特征在于,所述检测模块包括:多个计数器;每个计数器对应所述多路时钟信号中的一路时钟信号;The method according to claim 15, wherein the detection module comprises: a plurality of counters; each counter corresponds to one of the plurality of clock signals;
    所述同步模块将所述每路时钟信号的时钟域对应的使能信号传输至所述每路信号对应的计数器;The synchronization module transmits an enable signal corresponding to a clock domain of each clock signal to a counter corresponding to each signal;
    所述每路时钟信号对应的计数器在所述每路时钟信号的时钟域对应的使能信号的作用下,对所述每路时钟信号的上升沿或下降沿进行计数,得到所述每路时钟信号对应的计数值,所述每路时钟信号对应的计数值用于表征所述每路时钟信号的频率。The counter corresponding to each clock signal counts the rising or falling edge of each clock signal under the function of the enable signal corresponding to the clock domain of each clock signal to obtain the clock of each channel The count value corresponding to the signal, and the count value corresponding to each clock signal is used to characterize the frequency of each clock signal.
  17. 根据权利要求16所述的方法,其特征在于,所述多个计数器包括参考时钟对应的计数器,和至少一个待测时钟对应的计数器;The method according to claim 16, wherein the plurality of counters include a counter corresponding to a reference clock and a counter corresponding to at least one clock to be measured;
    所述方法还包括:The method further includes:
    当所述参考时钟对应的计数器的计数值达到第一预设数值,向所述每个计数器传输第一控制信号;Transmitting a first control signal to each counter when the count value of a counter corresponding to the reference clock reaches a first preset value;
    所述每个计数器根据所述第一控制信号停止计数。Each counter stops counting according to the first control signal.
  18. 根据权利要求17所述的方法,其特征在于,所述检测模块还包括:比较电路;The method according to claim 17, wherein the detection module further comprises: a comparison circuit;
    所述方法还包括:The method further includes:
    所述比较电路对所述每个待测时钟对应的计数器在停止计数时的计数值和预设的计数上限值和/或预设的计数下限值进行比较,得到比较结果。The comparison circuit compares a count value of the counter corresponding to each clock to be measured when the counting is stopped with a preset upper limit value and / or a preset lower limit value to obtain a comparison result.
  19. 根据权利要求18所述的方法,其特征在于,所述方法还包括:The method according to claim 18, further comprising:
    若所述每个待测时钟对应的计数器在停止计数时的计数值小于所述预设的计数上限值,且,所述计数值大于所述预设的计数下限值,所述比较电路输出第二控制信号至所述待测时钟对应的计数器和所述参考时钟对应的计数器;If the count value of the counter corresponding to each clock to be measured when stopping counting is smaller than the preset upper limit value, and the count value is greater than the preset lower limit value, the comparison circuit Outputting a second control signal to a counter corresponding to the clock to be tested and a counter corresponding to the reference clock;
    所述待测时钟对应的计数器和所述参考时钟对应的计数器根据所述第二控制信号进行初始化。The counter corresponding to the clock to be measured and the counter corresponding to the reference clock are initialized according to the second control signal.
  20. 根据权利要求18所述的方法,其特征在于,所述检测电路还包括:响应模块;The method according to claim 18, wherein the detection circuit further comprises: a response module;
    所述方法还包括:The method further includes:
    若所述每个待测时钟对应的计数器在停止计数时的计数值大于或等于所述预设的计数上限值,或者,所述计数值小于或等于所述预设的计数下限值,所述比较电路传输第三控制信号至所述响应模块;If the count value of the counter corresponding to each clock to be measured when stopping counting is greater than or equal to the preset upper limit value, or the count value is less than or equal to the preset lower limit value, The comparison circuit transmits a third control signal to the response module;
    所述响应模块根据所述第三控制信号输出中断信号、擦除信号或者复位信号中的任一信号。The response module outputs any one of an interrupt signal, an erase signal, or a reset signal according to the third control signal.
PCT/CN2018/101458 2018-08-21 2018-08-21 Detection circuit, method, chip, and device WO2020037485A1 (en)

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CN1655454A (en) * 2004-02-10 2005-08-17 大唐移动通信设备有限公司 Clock signal detection method and apparatus in electronic devices
CN102044291A (en) * 2009-10-26 2011-05-04 海力士半导体有限公司 Semiconductor device and method for operating the same
CN106707020A (en) * 2016-12-22 2017-05-24 武汉盛帆智能科技有限公司 Pulse detection device and pulse detection method

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Publication number Priority date Publication date Assignee Title
CN1655454A (en) * 2004-02-10 2005-08-17 大唐移动通信设备有限公司 Clock signal detection method and apparatus in electronic devices
CN102044291A (en) * 2009-10-26 2011-05-04 海力士半导体有限公司 Semiconductor device and method for operating the same
CN106707020A (en) * 2016-12-22 2017-05-24 武汉盛帆智能科技有限公司 Pulse detection device and pulse detection method

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