CN1655454A - Clock signal detection method and apparatus in electronic devices - Google Patents
Clock signal detection method and apparatus in electronic devices Download PDFInfo
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Abstract
This invention provides an electron device clock testing method, which comprises the following steps: determining the said CPU interval terminal signals and inputting the tested clock signal into the interval end of the said CPU; triggering the said tested clock signals for testing according to the interval signal. The invention provides an electron clock test device, which comprises clock input module, triggering module and clock signal test module.
Description
Technical field
The present invention relates to the network communications technology field, be specifically related to clock signal detection method and device in a kind of electronic equipment.
Background technology
Clock is the basis of the intercommunication of various communication apparatus in the communication system, if clock signal is of poor quality, clock signal is lost, digital information will confusion reigned in transmittance process, so that make whole communication apparatus in paralyzed state.Therefore, guarantee the reliability of communication apparatus clock signal, it is crucial in communication system that clock signal is carried out the clock signal detection.
At present, the method that clock signal is detected mainly is: install a clock vibration source in the circuit of communication apparatus additional, by clock vibration source clocking, output in the counter after using the frequency shift of needs with this clock signal of method according to communication apparatus of frequency division then, remove counter clearly with detected clock signal, clock signal to be detected is undesired if counter overflows explanation.
Needing to use 40.96 seconds clock signal, this clock signal in some communication apparatus is the interior a kind of extremely low frequency clock signal of low-frequency clock scope.The extremely low frequency clock is meant that generally frequency is lower than the signal of 30Hz.The waveform of this clock signal as shown in Figure 1.When the clock signal of these low frequencies, extremely low frequency is carried out the clock signal detection, use the method for above-mentioned clock vibration source just to seem unable to do what one wishes, because the general frequency of clock vibration source is all than higher, will take a large amount of hardware resource of communication apparatus in the time of the clock signal frequency division of clock vibration source being become very low frequency.Arrive to a certain degree when detected clock frequency is low, even can't realize the detection of clock signal.
In addition, use the clock signal detection circuit of clock vibration source method to design more complicated, cost than higher, and, clock signal detection circuit in a single day design is finished, can only a kind of clock signal of frequency be detected, if detect the clock signal of other frequencies, just can only design and realize that the versatility of testing circuit is poor by the change testing circuit.
Summary of the invention
The objective of the invention is to, clock signal detection method and device in a kind of electronic equipment are provided, utilize CPU to realize the simplifier clock signal deteching circuit, improve the versatility of testing circuit, reduce the purpose of communication apparatus cost with interruptive port.
For achieving the above object, clock signal detection method in a kind of electronic equipment provided by the invention comprises:
A, determine the interrupt signal of the interruptive port of described CPU;
B, detected clock signal imported the interruptive port of described CPU;
C, trigger according to the described detected clock signal of described definite interrupt signal described detected clock signal is carried out clock detection.
Described step a comprises:
Determine two mutually different interrupt signals of interruptive port of described CPU respectively.
Described two mutually different interrupt signals of interruptive port are respectively high level, low level;
And described step b comprises:
Obtain described detected rising edge of clock signal, trailing edge;
Described rising edge, each self-corresponding high level of trailing edge, low level are imported two interruptive ports of described CPU respectively.
Described two mutually different interrupt signals of interruptive port are respectively rising edge, trailing edge;
Described step b comprises:
Described detected clock signal and its are got two interruptive ports that signal after non-is imported described CPU respectively.
Described step c comprises:
Described two interruptive ports enter interruption under the break signal triggering therein respectively, begin high level/low level counting to described detected clock signal, and when receiving interrupt signal, another interruptive port removes interrupt signal, go out to interrupt, stop low level/high level counting described detected clock signal;
Obtain the high level/low level count value of described two interruptive ports respectively;
High level/low level predetermined count value according to the standard of described high level/low level count value, described detected clock signal correspondence is carried out the corresponding clock signals faulty indication to described detected clock signal.
Clock signal detection device in a kind of electronic equipment provided by the invention comprises:
Have the CPU of interruptive port, it is characterized in that, described device further comprises:
Clock input module: the interruptive port of detected clock signal being imported described CPU;
Trigger module: obtain the signal of the described interruptive port of input, and triggering signal is transferred to the clock signal detection module according to described interruptive port predetermined interrupt signal;
Clock signal detection module: described detected clock signal is carried out the clock signal detection according to the triggering signal that described trigger module transmission comes.
Described clock input module comprises:
First clock input submodule: when described detected clock signal was rising edge, the high level that it is corresponding was imported the interruptive port of described CPU;
Second clock input submodule: when described detected clock signal was trailing edge, the low level that it is corresponding was imported another interruptive port of described CPU.
Described first clock input submodule comprises first d type flip flop, and described second clock input submodule comprises not gate, second d type flip flop;
According to the D end ground connection/power supply of described first d type flip flop of interrupt signal of the interruptive port of described CPU, described detected clock signal is as the clock signal of first d type flip flop, and the Q of described first d type flip flop end exports the interruptive port of described CPU to;
Described not gate receives detected clock signal, and described not gate output signal is as the clock signal of described second d type flip flop;
According to the D end ground connection/power supply of described second d type flip flop of interrupt signal of another interruptive port of described CPU, the Q end of described second d type flip flop exports another interruptive port of described CPU to.
Described clock input module comprises:
The 3rd clock input submodule a: interruptive port described detected clock signal directly being imported described CPU;
The 4th clock input submodule: another interruptive port of described detected clock signal being got the described CPU of non-back input.
Described trigger module comprises:
First triggers submodule: obtain the signal of the described interruptive port of input, and according to this interruptive port predetermined interrupt signal first triggering signal is transferred to high level, low level counting submodule, the interrupt signal of another interruptive port of clear described CPU;
Second triggers submodule: the signal that obtains described another interruptive port of input, and second triggering signal is transferred to described high level, low level counting submodule, the interrupt signal of the interruptive port of clear described CPU according to this interruptive port predetermined interrupt signal;
And described clock signal detection module comprises:
Predetermined count value submodule: the high level/low level predetermined count value of storing the standard of described detected clock signal correspondence;
High level counting submodule: trigger the first next triggering signal of submodule transmission according to described first and begin the high level of described detected signal is counted, trigger the second next triggering signal of submodule transmission according to described second and stop the high level of described detected signal is counted, and storage high level count value;
Low level counting submodule: trigger the second next triggering signal of submodule transmission according to described second and begin the low level of described detected signal is counted, trigger the first next triggering signal of submodule transmission according to described first and stop the low level of described detected signal is counted, and storage low level count value;
Judgement submodule: obtain storage high level predetermined count value, low level predetermined count value, high level count value and low level count value in described predetermined count value submodule, described high level counting submodule and the described low level counting submodule respectively, carry out the corresponding clock signals faulty indication.
Description by technique scheme can obviously be learnt, utilization of the present invention has the CPU of interruptive port, clock signal at various frequency ranges, especially the clock signal of low frequency, extremely low frequency can simply realize the detection to detected clock signal, the clock signal detection circuit simplicity of design, used electronic device seldom, improved the reliability of clock signal detection circuit, the hardware resource that takies communication apparatus simultaneously is few; Based on clock signal detection circuit of the present invention, can carry out clock signal to the detected clock signal of different frequency under the prerequisite of testing circuit and detect not needing to change, shortened the construction cycle and the development cost of testing circuit greatly; Thereby realized the simplifier clock signal deteching circuit, improved the versatility of testing circuit, reduced the purpose of communication apparatus cost.
Description of drawings
Fig. 1 is a low-frequency clock signal waveform schematic diagram;
Fig. 2 is a clock signal detection method flow chart of the present invention;
Fig. 3 is the process chart at interruptive port 1 of the present invention;
Fig. 4 is the process chart at interruptive port 2 of the present invention;
Fig. 5 is a clock signal detection device schematic diagram of the present invention;
Fig. 6 is a clock input module logic diagram 1 in the clock signal detection device of the present invention;
Fig. 7 is a clock input module logic diagram 2 in the clock signal detection device of the present invention.
Embodiment
Core of the present invention is to utilize the interruptive port of CPU to realize the detection of detected clock signal.Therefore, the interrupt signal that at first needs the interruptive port of definite described CPU, then detected clock signal is imported the interruptive port of described CPU, triggered according to the described detected clock signal of described definite interrupt signal described detected clock signal is carried out clock detection.
Now in conjunction with the accompanying drawings technical scheme provided by the invention is done and described in further detail.
Clock signal detection method flow process of the present invention as shown in Figure 2.
In Fig. 2, step 200 is determined the clock frequency of detected clock signal, according to high level predetermined count value, the low level predetermined count value of its this clock standard of clock frequency setting.
To step 210, the interrupt signal of two interruptive ports of CPU is set respectively.For the interruptive port of CPU, its interrupt mode generally has two kinds: a kind of is level triggering mode, and another kind is along triggering mode.Level triggering mode triggers interruption by high level, low level as interrupt signal; Trigger interruption by rising edge, trailing edge as interrupt signal along triggering mode.
In this flow chart respectively according to the level triggers of CPU interruptive port, describe along triggering mode.In step 210, the triggering mode of setting CPU interruptive port 1 and interruptive port 2 is a level triggers, and the interrupt signal of interruptive port 1 is high level, and the interrupt signal of interruptive port 2 is a low level.
To step 220, when detected clock signal is rising edge, high level is imported interruptive port 1, when detected clock signal is trailing edge, low level is imported interruptive port 2.Interruptive port 1, interruptive port 2 receive high level/low level signal respectively, under its interrupt signal high level/low level triggering separately, enter interruption respectively, begin the high/low level of detected clock signal is counted, and respectively when another interruptive port receives interrupt signal, go out to interrupt, stop high/low level counting to detected clock signal, simultaneously, storage high level count value/low level count value.At two interruptive ports enter interruption, the handling process of go out interrupting shown in accompanying drawing 3 and accompanying drawing 4, these two the description of the drawings are introduced in the back in detail.The specific implementation device that high level, the low level of detected rising edge of clock signal, trailing edge correspondence are imported interruptive port 1, interruptive port 2 respectively as shown in Figure 6, this description of the drawings is introduced in the back in detail.
To step 230, periodically read high level count value and low level count value.
To step 240, high level count value, low level count value are compared with high level predetermined count value, low level predetermined count value respectively, if numerical value differs in preset range, illustrate that detected clock signal is normal, to step 250, with high level count value, the zero clearing of low level count value,, carry out the high level to detected clock signal/low level counting process next time to step 220.
In step 240, if high level count value, low level count value differ above preset range with high level predetermined count value, low level predetermined count value respectively, illustrate that detected clock signal is undesired, to step 241, detected clock signal is carried out faulty indication, arrive step 250 again, with high level count value, the zero clearing of low level count value, to step 220, carry out the high level to detected clock signal/low level counting process next time.
If the interruptive port of CPU adopts along triggering mode, so, in step 210, the interrupt signal of setting interruptive port 1 is a rising edge, and the interrupt signal of interruptive port 2 is a trailing edge.
To step 220, detected clock signal is directly imported interruptive port 1, detected clock signal is got non-back input interruptive port 2.Interruptive port 1, interruptive port 2 receive rising edge, trailing edge signal, under the triggering of its separately interrupt signal rising edge, trailing edge, enter interruption respectively, begin the high/low level of detected clock signal is counted, and respectively when another interruptive port receives interrupt signal, go out to interrupt, stop counting, store high level count value/low level count value simultaneously the high/low level of detected clock signal.The specific implementation device that detected rising edge of clock signal, trailing edge are imported interruptive port 1, interruptive port 2 respectively as shown in Figure 7, this description of the drawings is introduced in the back in detail.
The interruptive port of CPU adopts all the other steps of detected clock signal being carried out clock detection along triggering mode identical with the flow process of foregoing description, here no longer describes in detail.
Clock signal detection method provided by the invention only needs corresponding change high level predetermined count value and low level predetermined count value can realize detecting carry out clock signal based on the detected clock signal of different clock frequencies.
Handling process at interruptive port 1 of the present invention as shown in Figure 3.
In Fig. 3, the interrupt signal of setting interruptive port 1 is a high level.In step 300, detected clock signal transfers to interruptive port 1 with high level signal when rising edge, interruptive port 1 receives high level signal, and the interruptive port 1 of CPU needs to interrupt, to step 310, the interruptive port 1 of CPU enters interruption, and the disable interrupts port one interrupts.
To step 320, begin high level counting to detected clock signal, simultaneously, stop the low level counting to detected clock signal of interruptive port 2, the interrupt signal of clear interruptive port 2 allows interruptive port 2 to interrupt.
To step 330, when interruptive port 2 receives the low level interrupt signal, stop the high level counting to detected clock signal of interruptive port 1, and storage high level count value.
To step 340, the interrupt signal of clear interruptive port 1, the interruptive port 1 of CPU goes out to interrupt, and allows interruptive port 1 to interrupt.
Handling process at interruptive port 2 of the present invention as shown in Figure 4.
In Fig. 4, the interrupt signal of setting interruptive port 2 is a low level.In step 400, detected clock signal transfers to interruptive port 2 with low level signal when trailing edge, interruptive port 2 receives low level signal, and the interruptive port 2 of CPU needs to interrupt, to step 410, the interruptive port 2 of CPU enters interruption, and disable interrupts port 2 interrupts.
To step 420, begin low level counting to detected clock signal, simultaneously, stop the high level counting to detected clock signal of interruptive port 1, the interrupt signal of clear interruptive port 1 allows interruptive port 1 to interrupt.
To step 430, when interruptive port 1 receives the low level interrupt signal, stop the low level counting to detected clock signal of interruptive port 2, and storage low level count value.
To step 440, the interrupt signal of clear interruptive port 2, the interruptive port 2 of CPU goes out to interrupt, and allows interruptive port 2 to interrupt.
The interrupt signal of setting interruptive port 1 is a rising edge, and the interrupt signal of interruptive port 2 is a trailing edge, and handling process such as above-mentioned description process at interruptive port 1, interruptive port 2 of the present invention here no longer specify.
Clock signal detection device schematic diagram provided by the invention as shown in Figure 5.
In Fig. 5, clock signal detection device comprises clock input module 500, trigger module 510 and clock signal detection module 520.
When the interrupt signal that is provided with when the interruptive port 1 of CPU and interruptive port 2 was high level, low level, the function of clock input module 500 was finished by first clock input submodule 501, second clock input submodule 502.
The function of trigger module 510 triggers submodule 512 by the first triggering submodule 511, second and finishes.
The function of clock signal detection module 520 is by predetermined count value submodule 521, and high level is counted submodule 522, and low level counting submodule 523, judgement submodule 524 are finished.
When described detected clock signal was rising edge, first clock input submodule 501 was imported high level the interruptive port 1 of CPU.
When described detected clock signal was trailing edge, first clock input submodule 502 was imported low level the interruptive port 2 of CPU.
First triggers the signal that submodule 511 obtains input interruptive port 1, when the signal of this interruptive port is high level, first triggering signal is transferred to high level counting submodule 522, low level counting submodule 523, and the interrupt signal of clear interruptive port 2, make interruptive port 2 go out to interrupt.
Second triggers the signal that submodule 512 obtains input interruptive port 2, when the signal of this interruptive port is low level, second triggering signal is transferred to high level counting submodule 522 and low level counting submodule 523, and the interrupt signal of clear interruptive port 1, make interruptive port 1 go out to interrupt.
The high level predetermined count value and the low level predetermined count value of the standard of the detected clock signal correspondence of predetermined count value submodule 521 storages.
High level counting submodule 522 triggers the first next triggering signal of submodule 511 transmission according to first to begin the high level of detected clock signal is counted, trigger the second next triggering signal of submodule 512 transmission according to second and stop the high level of detected clock signal is counted, and storage is to the high level count value of detected clock signal.
Low level counting submodule 523 triggers the second next triggering signal of submodule 512 transmission according to second to begin the low level of detected clock signal is counted, trigger submodule 511 according to described first and transmit the low level counting that first triggering signal of coming stops detected clock signal, and storage is to the low level count value of detected clock signal.
When the interrupt signal that is provided with when the interruptive port 1 of CPU and interruptive port 2 is rising edge, trailing edge, first clock input submodule 501, second clock input submodule 502 are substituted by the 3rd clock input submodule, the 4th clock input submodule respectively among Fig. 5, and the function of clock input module 500 is finished by the 3rd clock input submodule, the 4th clock input submodule.
The 3rd clock input submodule is directly imported interruptive port 1 with detected clock signal.
The 4th clock input submodule is got non-back input interruptive port 2 with detected clock signal.
When the function of clock input module 500 by the 3rd clock input submodule, when the 4th clock input submodule is finished, first triggers the signal that submodule 511 obtains input interruptive port 1, when the signal of this interruptive port is rising edge, first triggering signal is transferred to high level counting submodule 522, low level counting submodule 523, and the interrupt signal of clear interruptive port 2, make interruptive port 2 go out to interrupt.
Second triggers the signal that submodule 512 obtains input interruptive port 2, when the signal of this interruptive port is trailing edge, second triggering signal is transferred to high level counting submodule 522 and low level counting submodule 523, and the interrupt signal of clear interruptive port 1, make interruptive port 1 go out to interrupt.
The function when clock input module 500 of the function of predetermined count value submodule 521, high level counting submodule 522, low level counting submodule 523, judgement submodule 524 and foregoing description is identical when finishing by first clock input submodule 501, second clock input submodule 502, no longer describes in detail in the present embodiment.
Clock signal detection device provided by the invention only needs the high level predetermined count value and the low level predetermined count value of storage in the corresponding change predetermined count value submodule 521, can realize that carrying out clock signal based on the detected clock signal of different clock frequencies detects.
The logic diagram of clock input module is shown in accompanying drawing 6, accompanying drawing 7 in the clock signal detection device of the present invention.
The circuit design logic diagram that comprises first clock input submodule 501, second clock input submodule 502 in the accompanying drawing 6.
Among Fig. 6, the I/O of CPU (0) and I/O (1) are I/O (input and output) ports of CPU, and its effect is to interrupt clearly.INT0 and INT1 are respectively the interrupt signal of CPU interruptive port 1, interruptive port 2.
First d type flip flop is realized the function of first clock input submodule 501, and the not gate and second d type flip flop are realized the function of second clock input submodule 502.Not gate and two d type flip flops can adopt discrete device, also can adopt the programmable logic device design.
Circuit design principle is: the interruptive port 1 of CPU, interruptive port 2 adopt level triggering mode, utilize monitored rising edge of clock signal and trailing edge to make two d type flip flops produce high level/low level respectively, thereby make the interruptive port of CPU enter interruption.Be set to according to the interrupt type of CPU interruptive port 1 and interruptive port 2 that low level is interrupted or high level interrupts, the D end of two d type flip flops can adopt GND (ground connection) or VCC (connecing power supply) respectively, in the ordinary course of things power source voltage be+5V or+3.3V.
The circuit design logic diagram that comprises the 3rd clock input submodule, the 4th clock input submodule in the accompanying drawing 7.
The 3rd clock input submodule is directly imported detected clock signal the interruptive port 1 of CPU.
Not gate among Fig. 7 is realized the function of the 4th clock input submodule.Circuit design principle is: the interruptive port 1 of CPU, interruptive port 2 adopt along triggering mode, utilize detected rising edge of clock signal, trailing edge to make interruptive port 1/ interruptive port 2 of CPU enter interruption respectively.
Though described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wishes that appended claim comprises these distortion and variation.
Claims (10)
1, clock signal detection method in a kind of electronic equipment, this method has been utilized the CPU with interruptive port, it is characterized in that comprising:
A, determine the interrupt signal of the interruptive port of described CPU;
B, detected clock signal imported the interruptive port of described CPU;
C, trigger according to the described detected clock signal of described definite interrupt signal described detected clock signal is carried out clock detection.
2, clock signal detection method in a kind of electronic equipment as claimed in claim 1 is characterized in that described step a comprises:
Determine two mutually different interrupt signals of interruptive port of described CPU respectively.
3, clock signal detection method in a kind of electronic equipment as claimed in claim 2 is characterized in that, described two mutually different interrupt signals of interruptive port are respectively high level, low level;
And described step b comprises:
Obtain described detected rising edge of clock signal, trailing edge;
Described rising edge, each self-corresponding high level of trailing edge, low level are imported two interruptive ports of described CPU respectively.
4, clock signal detection method in a kind of electronic equipment as claimed in claim 2 is characterized in that, described two mutually different interrupt signals of interruptive port are respectively rising edge, trailing edge;
Described step b comprises:
Described detected clock signal and its are got two interruptive ports that signal after non-is imported described CPU respectively.
5, as clock signal detection method in claim 2 or the 3 or 4 described a kind of electronic equipments, it is characterized in that described step c comprises:
Described two interruptive ports enter interruption under the break signal triggering therein respectively, begin high level/low level counting to described detected clock signal, and when receiving interrupt signal, another interruptive port removes interrupt signal, go out to interrupt, stop low level/high level counting described detected clock signal;
Obtain the high level/low level count value of described two interruptive ports respectively;
High level/low level predetermined count value according to the standard of described high level/low level count value, described detected clock signal correspondence is carried out the corresponding clock signals faulty indication to described detected clock signal.
6, clock signal detection device in a kind of electronic equipment comprises the CPU with interruptive port, it is characterized in that, described device further comprises:
Clock input module: the interruptive port of detected clock signal being imported described CPU;
Trigger module: obtain the signal of the described interruptive port of input, and triggering signal is transferred to the clock signal detection module according to described interruptive port predetermined interrupt signal;
Clock signal detection module: described detected clock signal is carried out the clock signal detection according to the triggering signal that described trigger module transmission comes.
7, clock signal detection device in a kind of electronic equipment as claimed in claim 6 is characterized in that described clock input module comprises:
First clock input submodule: when described detected clock signal was rising edge, the high level that it is corresponding was imported the interruptive port of described CPU;
Second clock input submodule: when described detected clock signal was trailing edge, the low level that it is corresponding was imported another interruptive port of described CPU.
8, clock signal detection device in a kind of electronic equipment as claimed in claim 7 is characterized in that described first clock input submodule comprises first d type flip flop, and described second clock input submodule comprises not gate, second d type flip flop;
According to the D end ground connection/power supply of described first d type flip flop of interrupt signal of the interruptive port of described CPU, described detected clock signal is as the clock signal of first d type flip flop, and the Q of described first d type flip flop end exports the interruptive port of described CPU to;
Described not gate receives detected clock signal, and described not gate output signal is as the clock signal of described second d type flip flop;
According to the D end ground connection/power supply of described second d type flip flop of interrupt signal of another interruptive port of described CPU, the Q end of described second d type flip flop exports another interruptive port of described CPU to.
9, clock signal detection device in a kind of electronic equipment as claimed in claim 6 is characterized in that described clock input module comprises:
The 3rd clock input submodule a: interruptive port described detected clock signal directly being imported described CPU;
The 4th clock input submodule: another interruptive port of described detected clock signal being got the described CPU of non-back input.
10, as clock signal detection device in claim 7 or the 8 or 9 described a kind of electronic equipments, it is characterized in that described trigger module comprises:
First triggers submodule: obtain the signal of the described interruptive port of input, and according to this interruptive port predetermined interrupt signal first triggering signal is transferred to high level, low level counting submodule, the interrupt signal of another interruptive port of clear described CPU;
Second triggers submodule: the signal that obtains described another interruptive port of input, and second triggering signal is transferred to described high level, low level counting submodule, the interrupt signal of the interruptive port of clear described CPU according to this interruptive port predetermined interrupt signal;
And described clock signal detection module comprises:
Predetermined count value submodule: the high level/low level predetermined count value of storing the standard of described detected clock signal correspondence;
High level counting submodule: trigger the first next triggering signal of submodule transmission according to described first and begin the high level of described detected signal is counted, trigger the second next triggering signal of submodule transmission according to described second and stop the high level of described detected signal is counted, and storage high level count value;
Low level counting submodule: trigger the second next triggering signal of submodule transmission according to described second and begin the low level of described detected signal is counted, trigger the first next triggering signal of submodule transmission according to described first and stop the low level of described detected signal is counted, and storage low level count value;
Judgement submodule: obtain storage high level predetermined count value, low level predetermined count value, high level count value and low level count value in described predetermined count value submodule, described high level counting submodule and the described low level counting submodule respectively, carry out the corresponding clock signals faulty indication.
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2004
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