CN111290888A - Method for interrupting output - Google Patents
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- CN111290888A CN111290888A CN202010232212.8A CN202010232212A CN111290888A CN 111290888 A CN111290888 A CN 111290888A CN 202010232212 A CN202010232212 A CN 202010232212A CN 111290888 A CN111290888 A CN 111290888A
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
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Abstract
The application provides a method, a device and an electronic device for interrupt output, which can improve the accuracy of interrupt detection, and the method is applied to an interrupt output device, wherein the interrupt output device comprises an interrupt port, the interrupt port is used for outputting an interrupt signal, the interrupt port is connected to an interrupt detection device, the interrupt detection device is used for detecting the interrupt signal to determine whether the interrupt output device generates an interrupt, and the method comprises the following steps: and when the interrupt output device is reset, outputting a first interrupt signal through the interrupt port, wherein the first interrupt signal comprises a rising edge signal and a falling edge signal, and the first interrupt signal is used for the interrupt detection device to determine whether the interrupt output device interrupts.
Description
Technical Field
The present application relates to the field of chip technology, and more particularly, to a method, an apparatus, and an electronic device for interrupting output.
Background
During the operation of the chip, a chip reset may occur, for example, a reset caused by software version upgrade, a watchdog reset, a power-down reset or a reset caused by other hardware faults, and the like. After the chip is reset, a controller of the chip, for example, a master (Host) needs to be notified of its current state, so that the master can reconfigure the chip conveniently, and thus the execution of the normal functions of the chip is not affected. In one implementation, the chip may output an interrupt signal to the master, and the master determines a current state of the chip, such as an interrupt or normal operation, through the interrupt signal output by the chip.
The method of outputting the interrupt signal by the chip may be referred to as an interrupt output method, and the interrupt output method may be, for example, active low, active high, or the like. In a specific implementation, the interrupt output mode adopted by the chip may be configured, so that the chip may output a corresponding interrupt signal when an interrupt occurs according to the configured interrupt output mode. For example, if the interrupt output mode of the chip is set to active low, the interrupt signal output therefrom is low, and, for example, if the interrupt output mode of the chip is set to active high, the interrupt signal output therefrom is high.
After the chip is reset, the interrupt output mode configured for the chip is also reset to the default interrupt output mode, and in general, the default interrupt output mode is active low, and the interrupt signal output by the chip is active low after the chip is reset. On the master side, it may perform interrupt detection based on a specific interrupt detection mode, and in general, the specific interrupt detection mode is active at a high level, and the master may determine that the chip is interrupted when detecting that an interrupt signal output by the chip is at a high level.
As described above, when the chip is reset, the interrupt output mode of the chip is reset to the default interrupt output mode, which is usually low level valid, that is, the interrupt signal output by the chip is low level, and the interrupt detection mode of the master control is usually high level valid, so that the master control cannot identify that the chip has been interrupted, and further the master control cannot perform corresponding configuration on the chip, which affects the execution of the normal function of the chip, and further affects the user experience.
Disclosure of Invention
The application provides an interrupt output method, an interrupt output device and electronic equipment, which can improve the accuracy of interrupt identification.
In a first aspect, a method for interrupting output is provided, which is applied to an interrupt output device, the interrupt output device includes an interrupt port, the interrupt port is used for outputting an interrupt signal, the interrupt port is connected to an interrupt detection device, the interrupt detection device is used for detecting the interrupt signal to determine whether an interrupt occurs in the interrupt output device, and the method includes:
and when the interrupt output device is reset, outputting a first interrupt signal through the interrupt port, wherein the first interrupt signal comprises a rising edge signal and a falling edge signal, and the first interrupt signal is used for the interrupt detection device to determine whether the interrupt output device interrupts.
In some optional implementations, the first interrupt signal is a pulse signal with alternating high and low levels, wherein the low level to high level forms the rising edge signal and the high level to low level forms the falling edge signal.
In some alternative implementations, the first interrupt signal includes one pulse signal from a low level to a high level to a low level, or the first interrupt signal includes one pulse signal from a high level to a low level to a high level.
In some optional implementations, the method further comprises:
in a case where the interrupt output means is reset, the interrupt output means is configured to a first interrupt output mode and outputs the first interrupt signal through the interrupt port, wherein the interrupt detection means determines whether the interrupt output means is interrupted based on a first interrupt detection mode, the first interrupt output mode being one of: active low, active high, active rising and active falling edges, the first interrupt detection mode being one of: active low, active high, active rising and active falling.
In some optional implementations, the first interrupt detection mode and the first interrupt output mode are different.
In some optional implementations, the method further comprises:
the interrupt output device outputs a second interrupt signal through the interrupt port under the condition that an interrupt event which does not trigger reset occurs, wherein the second interrupt signal is one of low level, high level, rising edge and falling edge.
In some optional implementations, the interrupt output device is a chip, the interrupt detection device is a processor, and an interrupt port of the chip outputs the first interrupt signal to the processor, so that the processor determines whether an interrupt occurs to the chip according to the first interrupt signal.
In some optional implementation manners, the chip is a fingerprint sensing chip, the fingerprint sensing chip is configured to be disposed in an electronic device, the fingerprint sensing chip is configured to acquire fingerprint information of a finger of a user pressing the electronic device, the processor is a processor in the electronic device, and the processor in the electronic device is configured to perform fingerprint authentication according to the fingerprint information of the finger of the user.
In some alternative implementations, the interrupt output device being reset may be caused by any one of the following events: power-up or power-down, external restart signal, software command, clock loss detector or watchdog timer
In a second aspect, there is provided an interrupt output device including an interrupt port connected to an interrupt detection device, wherein the interrupt output device includes:
and the processing module is used for outputting a first interrupt signal through the interrupt port under the condition that the interrupt output device is reset, wherein the first interrupt signal comprises a rising edge signal and a falling edge signal, and the first interrupt signal is used for the interrupt detection device to determine whether the interrupt output device generates an interrupt or not.
In some optional implementations, the first interrupt signal is a pulse signal with alternating high and low levels, wherein the low level to high level forms the rising edge signal and the high level to low level forms the falling edge signal.
In some alternative implementations, the first interrupt signal includes one pulse signal from a low level to a high level to a low level, or the first interrupt signal includes one pulse signal from a high level to a low level to a high level.
In some optional implementations, the processing module is further configured to:
in a case where the interrupt output means is reset, the interrupt output means is configured to a first interrupt output mode and outputs the first interrupt signal through the interrupt port, wherein the interrupt detection means determines whether the interrupt output means is interrupted based on a first interrupt detection mode, the first interrupt output mode being one of: the first interrupt output mode is one of the following modes: active low, active high, active rising and active falling.
In some optional implementations, the first interrupt detection mode and the first interrupt output mode are different.
In some optional implementations, the processing module is further configured to:
and in the case of an interrupt event which does not trigger reset, outputting a second interrupt signal through the interrupt port, wherein the second interrupt signal is one of low level, high level, rising edge and falling edge.
In some optional implementations, the interrupt output device is a chip, the interrupt detection device is a processor, and an interrupt port of the chip outputs the first interrupt signal to the processor, so that the processor determines whether an interrupt occurs to the chip according to the first interrupt signal.
In some optional implementation manners, the chip is a fingerprint sensing chip, the fingerprint sensing chip is configured to be disposed in an electronic device, the fingerprint sensing chip is configured to acquire fingerprint information of a finger of a user pressing the electronic device, the processor is a processor in the electronic device, and the processor in the electronic device is configured to perform fingerprint authentication according to the fingerprint information of the finger of the user.
In a third aspect, an electronic device is provided, which includes: including a processor and memory. The memory is used for storing a computer program, and the processor is used for calling and running the computer program stored in the memory, and executing the method in the first aspect or each implementation manner thereof.
In a fourth aspect, a chip is provided for implementing the method in the first aspect or its implementation manners.
Specifically, the chip includes: a processor configured to call and run the computer program from the memory, so that the device on which the chip is installed performs the method according to the first aspect or the implementation manner thereof.
In a fifth aspect, a computer-readable storage medium is provided for storing a computer program, which causes a computer to execute the method of the first aspect or its implementations.
A sixth aspect provides a computer program product comprising computer program instructions for causing a computer to perform the method of the first aspect or its implementations.
In a seventh aspect, a computer program is provided, which, when run on a computer, causes the computer to perform the method of the first aspect or its implementations.
Therefore, in the embodiment of the present application, when a chip is reset, an interrupt port of the chip may output a first interrupt signal, where the first interrupt signal includes a rising edge signal and a falling edge signal, that is, four signal types including a low level, a high level, a rising edge, and a falling edge may be included in the first interrupt signal, so that no matter which interrupt detection manner of a master is configured, a valid interrupt signal may be detected in the first interrupt signal, and thus, an interrupt of the chip may be recognized.
Drawings
FIG. 1 is a schematic diagram of several exemplary interrupt detection schemes.
Fig. 2 is a schematic diagram of a method of interrupting an output according to an embodiment of the present application.
FIG. 3 is an exemplary diagram of an interrupt signal according to an embodiment of the present application.
Fig. 4 is a schematic block diagram of an interrupt output device according to an embodiment of the present application.
Fig. 5 is a schematic block diagram of an electronic device according to an embodiment of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.
In some scenarios, for example, a processor (or master) of the electronic device may configure and control a chip within the electronic device so that it can perform corresponding functions in the electronic device. Taking the chip as a fingerprint sensing chip as an example, the processor of the electronic device may configure the fingerprint sensing chip so that the fingerprint sensing chip can collect fingerprint information of a user touching the electronic device under appropriate conditions.
When an event triggering the interrupt occurs, the fingerprint sensing chip can inform the processor of the current state in a mode of sending an interrupt signal, so that the processor can configure and control the fingerprint sensing chip accordingly. For example, when the chip is reset, the fingerprint sensing chip may send an interrupt signal to the processor, so that the processor may detect the interrupt signal to determine the current state of the fingerprint sensing chip.
As described above, the chip may output the interrupt signal according to the configured interrupt output mode, and the master may also perform interrupt detection according to the configured interrupt detection mode, where fig. 1 shows four typical interrupt detection modes of the master. Specifically, if the interrupt detection mode of the master control is low level and effective, when the interrupt signal output by the chip is detected to be low level, the chip is determined to be interrupted; if the main control interrupt detection mode is high level effective, determining that the chip is interrupted when detecting that an interrupt signal output by the chip is high level; if the main control interrupt detection mode is that the rising edge is effective, determining that the chip is interrupted when detecting that the interrupt signal output by the chip comprises the rising edge; if the main control interrupt detection mode is that the falling edge is effective, when the interrupt signal output by the chip is detected to comprise the falling edge, the chip is determined to be interrupted.
However, when the chip is reset, the interrupt output mode of the chip is also reset, and at this time, if the interrupt output mode of the chip after reset is inconsistent with the interrupt detection mode configured by the main control, the main control may misjudge the state of the chip, which affects the execution of the normal function of the chip, and further affects the user experience.
In view of this, the present application provides an interrupt output scheme, which enables a master control to correctly identify a state of a chip even when an interrupt output mode of the chip is inconsistent with an interrupt detection mode of the master control by specially designing an interrupt signal output by the chip when the chip is reset, so that normal functions of the chip can be guaranteed to operate, and user experience is improved.
Fig. 2 is a schematic flow chart of a method 200 for interrupting output according to an embodiment of the present application, which is described below with an interrupt output device as an execution subject.
The interrupt output device may include an interrupt port, and the interrupt port is used for outputting an interrupt signal, and it should be understood that the interrupt port may be an actually existing physical port, or may also be an analog virtual port as long as the interrupt port can output an interrupt signal, which is not limited in this embodiment of the application.
In the embodiment of the present application, the interrupt output device is connected to the interrupt detection device through the interrupt port, so that the interrupt detection device performs interrupt detection according to an interrupt signal output by the interrupt port, and further determines a current state of the interrupt output device, such as occurrence of an interrupt, normal operation, or the like.
It should be noted that the embodiment of the present application does not specifically limit the connection relationship between the interrupt output device and the interrupt detection device. In some embodiments, the interrupt output device may be directly connected to the interrupt detection device, for example, the interrupt output device is connected to the interrupt detection device through a bus, such as an SPI bus, an I2C bus, or the like, or in other embodiments, the interrupt output device may also be indirectly connected to the interrupt detection device through other devices or apparatuses, for example, the interrupt output device is first connected to a third apparatus, such as an interrupt controller, and is further connected to the interrupt detection device through a third apparatus, and the third apparatus may directly transmit the interrupt signal output by the interrupt output device to the interrupt detection device, or may transmit the interrupt signal to the interrupt detection device after processing the interrupt signal.
It should be understood that, in the embodiment of the present application, the interrupt output device may be any device, chip or apparatus capable of outputting an interrupt signal, and the interrupt detection device may be a processor in the apparatus to which the interrupt output device is installed, which may monitor the state of the interrupt output device according to the interrupt signal output by the interrupt output device for timely processing.
In some embodiments, the interrupt output device may be a chip or module in the electronic device that performs a specific function, and as one example, the interrupt output device is a fingerprint sensing chip that can collect fingerprint information of a finger of a user pressing the electronic device for fingerprint recognition. The embodiment of the present application does not specifically limit the specific manner in which the fingerprint sensing chip collects fingerprint information, for example, the fingerprint sensing chip may be a capacitive fingerprint chip, an optical fingerprint chip, or an ultrasonic fingerprint chip. Correspondingly, the interruption detection device may be a processor of the electronic device, and the processor may be configured to process fingerprint information collected by the fingerprint sensing chip to determine whether the user is an authorized user.
As shown in fig. 2, a method 200 for interrupting an output according to an embodiment of the present application includes the following steps:
s210, when the interrupt output device is reset, outputting a first interrupt signal through the interrupt port, where the first interrupt signal includes a rising edge signal and a falling edge signal, and the first interrupt signal is used by the interrupt detection device to determine whether the interrupt output device is interrupted.
Optionally, in some embodiments, the interrupt output device being reset may be caused by any one of the following events: power up or power down, Reset (RST) pin of the interrupt output device, external restart (CNVSTR) signal, software command, comparator 0, clock loss detector or watchdog timer.
It should be understood that the present embodiment may be applied to a scenario in which the interrupt output mode is changed due to the reset of the interrupt output device, and further, the interrupt output mode is not consistent with the interrupt detection mode of the interrupt detection device, and of course, may also be applied to another scenario in which the interrupt output mode of the interrupt output device may be changed, and the following description will take a reset scenario as an example, but the present embodiment is not limited thereto.
For simplicity, the interrupt output device is taken as a chip, and the interrupt detection device is taken as a main control for explanation, but the embodiment of the present application is not limited thereto, and may also be the other cases described above, and for brevity, no further description is provided here.
In the embodiment of the application, when the chip is reset, the interrupt port of the chip can output a first interrupt signal, the first interrupt signal includes a rising edge signal and a falling edge signal, where, the order of the rising edge signal and the falling edge signal is not particularly limited, where the rising edge signal is formed by a low-to-high transition and the falling edge signal is formed by a high-to-low transition, that is, four signal types of low, high, rising and falling edges may be included in the first interrupt signal, whereby, regardless of which of the above-described interrupt detection modes the master is configured to, it can detect a valid interrupt signal in the first interrupt signal so as to be able to identify that the chip is interrupted, and further can perform appropriate processing, such as reconfiguration, on the chip.
It should be understood that the first interrupt signal may be any signal including a rising edge and a falling edge. As an embodiment, the first interrupt signal may be a pulse signal with a high level and a low level alternately, and preferably, as shown in fig. 3, the first interrupt signal may be a pulse signal from a low level to a high level and then to a low level, or a pulse signal from a high level to a low level and then to a high level.
It should be noted that, in this embodiment of the present application, the duration of the high level and the low level in the first interrupt signal is not specifically limited, and in some implementations, the duration of the high level in the first interrupt signal may be set to be not less than 10ms, for example, if the interrupt detection manner of the master is active in the high level and the duration of the high level is required to be 10ms, the master may be adapted to detect an active interrupt signal according to the interrupt detection manner of the master.
It should be understood that the interrupt detection manner listed in the embodiment of the present application is only an example, and of course, a specific implementation may also include more interrupt detection manners, and accordingly, the first interrupt signal may also be adaptively adjusted. For example, the interruption detection mode may be active as low-high-low-high (i.e. 0101), the first interruption signal may include at least two pulse signals with alternating high and low levels, and further, the interruption detection mode may also restrict the width of the pulse, so that the width of the pulse may also be adjusted to meet the requirement of the interruption detection mode when the first interruption signal is designed.
In the embodiment of the application, in addition to the reset scenario, the chip may output the interrupt signal, and in other scenarios, the chip may also output the interrupt signal, and in this case, the chip may output the interrupt signal according to the configured interrupt output mode, which is beneficial to better compatibility with the existing interrupt mechanism, and reduces the complexity of chip implementation.
Specifically, when an interrupt event that does not trigger a chip reset occurs, the chip outputs a second interrupt signal through the interrupt port, where the second interrupt signal is determined according to an interrupt output mode currently configured by the chip, for example, if the currently configured interrupt output mode is low level and valid, the second interrupt signal is output low level, and for example, if the currently configured interrupt output mode is rising edge and valid, the second interrupt signal is output rising edge.
It should be understood that the interrupt event may be any event that does not trigger the chip reset and that triggers an interrupt, by way of example and not limitation, the interrupt event may be a chip operation exception, such as a memory read error, a register abort, and the like. The occurrence of the interrupt event does not trigger the change of the interrupt output mode configured by the chip, that is, the problem of inconsistency between the interrupt detection mode configured by the main control and the interrupt output mode configured by the chip is not generated, therefore, the chip only needs to output the interrupt signal according to the configured interrupt output mode, and the main control can accurately judge the state of the chip by performing interrupt detection according to the configured interrupt detection mode.
The method embodiment of the present application is described in detail above with reference to fig. 2 to 3, and the apparatus according to the embodiment of the present application is described below with reference to fig. 4 to 5, and technical features described in the method embodiment are applicable to the following apparatus embodiments, and are not repeated herein for brevity.
Fig. 4 is a schematic structural diagram of an interrupt detection apparatus according to an embodiment of the present application, and as shown in fig. 4, the interrupt detection apparatus 400 may include an interrupt port 401, the interrupt port 401 being connected to the interrupt detection apparatus 300, wherein the interrupt output apparatus 400 includes:
a processing module 402, configured to output a first interrupt signal through the interrupt port if the interrupt output device is reset, where the first interrupt signal includes a rising edge signal and a falling edge signal, and the first interrupt signal is used by the interrupt detection device to determine whether an interrupt occurs in the interrupt output device.
In some embodiments of the present application, the processing module 402 may be a processor for invoking and executing the computer program from the memory for performing the method steps in the embodiment shown in fig. 2.
In some embodiments of the present application, the first interrupt signal is a pulse signal with alternating high and low levels, wherein the low level to high level forms the rising edge signal, and the high level to low level forms the falling edge signal.
In some embodiments of the present application, the first interrupt signal includes one pulse signal from a low level to a high level and then to a low level, or the first interrupt signal includes one pulse signal from a high level to a low level and then to a high level.
In some embodiments of the present application, the processing module 402 is further configured to:
in a case where the interrupt output means is reset, the interrupt output means is configured to a first interrupt output mode and outputs the first interrupt signal through the interrupt port, wherein the interrupt detection means determines whether the interrupt output means is interrupted based on a first interrupt detection mode, the first interrupt output mode being one of: the first interrupt output mode is one of the following modes: active low, active high, active rising and active falling.
In some embodiments of the present application, the first interrupt detection mode and the first interrupt output mode are different.
In some embodiments of the present application, the processing module 402 is further configured to:
and in the case of an interrupt event which does not trigger reset, outputting a second interrupt signal through the interrupt port, wherein the second interrupt signal is one of low level, high level, rising edge and falling edge.
In some embodiments of the present application, the interrupt output device is a chip, the interrupt detection device is a processor, and an interrupt port of the chip outputs the first interrupt signal to the processor, so that the processor determines whether the chip is interrupted according to the first interrupt signal.
In some embodiments of the present application, the chip is a fingerprint sensor chip, the fingerprint sensor chip is configured to be disposed in an electronic device, the fingerprint sensor chip is configured to obtain fingerprint information of a finger of a user pressing the electronic device, the processor is a processor in the electronic device, and the processor in the electronic device is configured to perform fingerprint authentication according to the fingerprint information of the finger of the user.
Fig. 5 is a schematic block diagram of an electronic device provided in an embodiment of the present application, and as shown in fig. 5, the electronic device 500 may include an interrupt output device 501 and a processor 502, where the interrupt output device 501 is connected to the processor 502, the interrupt output device 501 is configured to output an interrupt signal, and the processor 502 is configured to determine whether an interrupt occurs in the interrupt output device according to the interrupt signal.
In some embodiments of the present application, the interrupt output device 501 may be the interrupt output device 400 in fig. 4, and for concrete implementation, reference is made to the related description of the foregoing embodiments, and for brevity, detailed description is not repeated here.
In some embodiments of the present application, the processor 502 may be the interrupt detection apparatus 30 in fig. 4, and for concrete implementation, reference is made to the related description of the foregoing embodiments, and for brevity, no further description is provided here.
By way of example and not limitation, the electronic device 500 may be a mobile phone, a tablet computer, a notebook computer, a desktop computer, a vehicle-mounted electronic device, or a wearable smart device.
In some optional implementations, the interrupt output device 501 is a biometric sensor chip configured to be disposed in the electronic device 500, the biometric sensor chip is configured to obtain biometric information of a user pressing the electronic device 500, and the processor 502 is a processor in the electronic device 500, and the processor in the electronic device 500 is configured to perform identification authentication according to the biometric information of the user. For example, but not limited to, the biometric information includes any one or more of fingerprint information, palm print information, three-dimensional image information, three-dimensional face information, and the like.
The processing module may be an integrated circuit chip having signal processing capability. In implementation, the steps of the above method embodiments may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.
The memory module described above may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of example, but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (DDR SDRAM), Enhanced Synchronous SDRAM (ESDRAM), Synchronous link SDRAM (SLDRAM), and Direct Rambus RAM (DRRAM).
The embodiment of the present application further provides a chip, which is used for implementing the method in the embodiment shown in fig. 3. Specifically, the chip includes: and a processor for calling and running the computer program from the memory so that the device in which the chip is installed performs the method as in the above embodiments.
The embodiment of the application also provides a computer readable storage medium for storing the computer program. The computer-readable storage medium can be applied to the apparatus in the embodiment of the present application, and the computer program enables a computer to execute the corresponding process implemented by the interrupt output apparatus in each method in the embodiment of the present application, which is not described again for brevity.
Embodiments of the present application also provide a computer program product comprising computer program instructions. The computer program product can be applied to the apparatuses in the embodiments of the present application, and the computer program instructions enable a computer to execute corresponding processes implemented by the interrupt output apparatus in the methods in the embodiments of the present application, which are not described herein again for brevity.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The specific examples in the embodiments of the present application are only for helping those skilled in the art to better understand the embodiments of the present application, and do not limit the scope of the embodiments of the present application, and those skilled in the art may make various modifications and variations on the embodiments described above, and those modifications and variations fall within the scope of the present application.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method for interrupting output, applied to an interrupt output device, the interrupt output device comprising an interrupt port, the interrupt port being configured to output an interrupt signal, the interrupt port being connected to an interrupt detection device, the interrupt detection device being configured to detect the interrupt signal to determine whether an interrupt occurs in the interrupt output device, the method comprising:
and when the interrupt output device is reset, outputting a first interrupt signal through the interrupt port, wherein the first interrupt signal comprises a rising edge signal and a falling edge signal, and the first interrupt signal is used for the interrupt detection device to determine whether the interrupt output device interrupts.
2. The method of claim 1, wherein the first interrupt signal is a pulse signal with alternating high and low levels, wherein the low to high level forms the rising edge signal and the high to low level forms the falling edge signal.
3. The method according to claim 2, wherein the first interrupt signal comprises one pulse signal from low level to high level to low level, or the first interrupt signal comprises one pulse signal from high level to low level to high level.
4. The method according to any one of claims 1-3, further comprising:
in a case where the interrupt output means is reset, the interrupt output means is configured to a first interrupt output mode and outputs the first interrupt signal through the interrupt port, wherein the interrupt detection means determines whether the interrupt output means is interrupted based on a first interrupt detection mode, the first interrupt output mode being one of: active low, active high, active rising and active falling edges, the first interrupt detection mode being one of: active low, active high, active rising and active falling.
5. The method of claim 4, wherein the first interrupt detection mode and the first interrupt output mode are different.
6. The method according to any one of claims 1-3, further comprising:
the interrupt output device outputs a second interrupt signal through the interrupt port under the condition that an interrupt event which does not trigger reset occurs, wherein the second interrupt signal is one of low level, high level, rising edge and falling edge.
7. The method according to any one of claims 1-3, wherein the interrupt output device is a chip, the interrupt detection device is a processor, and an interrupt port of the chip outputs the first interrupt signal to the processor, so that the processor determines whether the chip is interrupted according to the first interrupt signal.
8. The method according to claim 7, wherein the chip is a fingerprint sensor chip configured to be disposed in an electronic device, the fingerprint sensor chip is configured to obtain fingerprint information of a finger of a user pressing the electronic device, and the processor is a processor in the electronic device, and the processor in the electronic device is configured to perform fingerprint authentication according to the fingerprint information of the finger of the user.
9. The method according to claim 7, wherein the chip is a biometric sensor chip configured to be disposed in an electronic device, the biometric sensor chip is configured to obtain biometric information of a user pressing the electronic device, and the processor is a processor in the electronic device configured to perform identification authentication according to the biometric information of the user.
10. The method of claim 1, wherein the interrupt output device being reset may be caused by any one of the following events: power up or power down, an external restart signal, a software command, a clock loss detector, or a watchdog timer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010232212.8A CN111290888A (en) | 2020-03-27 | 2020-03-27 | Method for interrupting output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010232212.8A CN111290888A (en) | 2020-03-27 | 2020-03-27 | Method for interrupting output |
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| CN111290888A true CN111290888A (en) | 2020-06-16 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0628913A1 (en) * | 1993-06-08 | 1994-12-14 | Nec Corporation | Interrupt signal detection circuit |
| CN1655454A (en) * | 2004-02-10 | 2005-08-17 | 大唐移动通信设备有限公司 | Clock signal detection method and apparatus in electronic devices |
| CN215814142U (en) * | 2020-03-27 | 2022-02-11 | 深圳阜时科技有限公司 | Interrupt output device and electronic apparatus |
-
2020
- 2020-03-27 CN CN202010232212.8A patent/CN111290888A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0628913A1 (en) * | 1993-06-08 | 1994-12-14 | Nec Corporation | Interrupt signal detection circuit |
| CN1655454A (en) * | 2004-02-10 | 2005-08-17 | 大唐移动通信设备有限公司 | Clock signal detection method and apparatus in electronic devices |
| CN215814142U (en) * | 2020-03-27 | 2022-02-11 | 深圳阜时科技有限公司 | Interrupt output device and electronic apparatus |
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Application publication date: 20200616 |