CN100511632C - 半导体制造装置 - Google Patents

半导体制造装置 Download PDF

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CN100511632C
CN100511632C CNB2005800270071A CN200580027007A CN100511632C CN 100511632 C CN100511632 C CN 100511632C CN B2005800270071 A CNB2005800270071 A CN B2005800270071A CN 200580027007 A CN200580027007 A CN 200580027007A CN 100511632 C CN100511632 C CN 100511632C
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semiconductor chip
metal part
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CN101019221A (zh
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德田法史
冈田裕子
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Mitsubishi Electric Corp
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Abstract

本发明涉及半导体制造装置，其目的在于不降低处理中的操作性地防止半导体基片的破损和变形。为了达成上述目的，半导体制造装置具有装载半导体基片(30)的承载台(100)，承载台(100)具有：由金属构成的与装载的半导体基片(30)触碰的第1金属部(10)；由导电弹性体组成的与装载的半导体基片(30)触碰的导电弹性体部(20)。异物(40)埋入导电弹性体部(20)。

Description

半导体制造装置
技术领域
本发明涉及半导体制造装置，具体涉及半导体基片的处理。
背景技术
半导体基片(半导体晶圆)的第一主面和第二主面之间流过电流的纵型半导体装置中，为了改善特性(例如降低导通电压)而进行着半导体基片的薄厚化。这样的半导体基片在一般的片页处理型半导体制造装置内，搬送到由金属构成的具有大致平坦表面的承载台后，通过吸附而装载在承载台上。
但是，在例如口径为6英寸且厚度薄至200μm以下的半导体基片中，半导体基片自身的强度降低。另外，半导体基片的背面附着灰尘和Si屑等组成的异物时，半导体基片为了加工或检查处理而装载在承载台上时，该异物夹在半导体基片和承载台之间。该异物若具有规定以上的硬度，则以该异物为基点对半导体基片施加大的应力，因此有半导体基片破损或变形的情况产生的问题。
为了解决这样的问题，专利文献1公开了在半导体基片和承载台之间介入由弹性体组成的缓冲体的半导体制造装置的例。另外，专利文献2～4公开在承载台的表面形成孔等的半导体制造装置的例。
专利文献1：特开昭55-43853
专利文献2：特开昭62-199030
专利文献3：特开昭59-135742
专利文献4：特开平4-152512
专利文献1中公开的半导体制造装置中，由于在与承载台之间另外介入缓冲体，因此产生处理中的操作性降低的问题。另外，专利文献2～4中公开的半导体制造装置中，从承载台的表面形成的孔等使半导体基片吸附。因而，在孔等大的场合，以该孔等为基点对半导体基片施加大的应力，因此产生半导体基片破损或变形的问题。
发明内容
本发明鉴于解决上述的问题而提出，目的在于提供：可不降低处理中的操作性地防止半导体基片的破损和变形的半导体制造装置。
本发明的半导体制造装置的第1方面，是一种设有装载半导体基片的承载台的半导体制造装置，其中，承载台包含：由金属构成的与装载的半导体基片触碰的第1金属部；由导电弹性体构成的与装载的半导体基片触碰的导电弹性体部。
根据本发明的半导体制造装置的第1方面，即使半导体基片装载在承载台上，由半导体基片的背面附着的异物施加到半导体基片的应力也能够降低，使半导体基片保持平坦。从而，可不使处理中的操作性降低地防止半导体基片的破损和变形。
本发明的半导体制造装置的第2方面，是一种具有装载半导体基片的承载台的半导体制造装置，其中，承载台包含：
由在表面未进行形成极多凹坑的处理的金属构成的与装载的半导体基片触碰的第1金属部；以及
由在表面进行了形成极多凹坑的处理的金属构成的与装载的半导体基片触碰的第2金属部，
在第1金属部上形成吸附用的多个孔，
在第2金属部的凹坑中未形成吸附用的孔。
根据本发明的半导体制造装置的第2方面，即使将半导体基片放置在承载台，也可降低由半导体基片的背面附着的异物施加到半导体基片的应力，使半导体基片保持平坦。从而，可不使处理中的操作性降低地防止半导体基片的破损和变形。通过以下的详细说明和添附图面可更加明白本发明的目的、特征、形态及优点。
附图说明
图1是本发明的实施例1的承载台的顶面图。
图2是承载台的截面图。
图3是承载台的截面图。
图4是承载台的截面图。
图5是承载台的顶面图。
图6是承载台的顶面图。
图7是承载台的顶面图。
图8是承载台的顶面图。
图9是承载台的顶面图。
图10是本发明的实施例2的承载台的顶面图。
图11是承载台截面的局部放大图。
图12是承载台截面的局部放大图。
图13是承载台截面的局部放大图。
图14是承载台的顶面图。
图15是承载台的顶面图。
图16是承载台的顶面图。
图17是承载台的顶面图。
图18是承载台的顶面图。
图19是承载台截面的局部放大图。
图20是承载台截面的局部放大图。
图21是承载台截面的局部放大图。
图22是承载台截面的局部放大图。
图23是承载台截面的局部放大图。
具体实施方式
(实施例1)
图1是本发明的实施例1的半导体制造装置设有的承载台100的顶面图。另外，图2是图1中的A-A’截面图。
如图1～2所示，承载台100由金属构成的平坦金属部(第1金属部)10a～10b和导电性硅胶等构成的平坦导电弹性体部20组成。金属部10a～10b及导电弹性体部20与承载台100上装载的1片半导体基片密合。再有，承载台100是真空吸附型的场合，在金属部10a～10b形成有许多吸附用的孔(图1～2中省略)。或者，该孔也可在导电弹性体部20中形成。
图3是截面图，表示紧临将有灰尘和Si屑等组成的异物40在背面附着的半导体基片(半导体晶圆)30在图2所示的承载台100上装载之前的情形。图4是截面图，表示图3中半导体基片30通过真空吸附装载在承载台100上的情形。如图4所示，异物40被埋入承载台100的导电弹性体部20。从而，即使在承载台100通过真空吸附装载半导体基片30的场合，也可降低由异物40对半导体基片30施加的应力，可使半导体基片30保持平坦，因此，可防止半导体基片30的破损和变形。
图1所示的承载台100中，金属部10a～10b的表面积和导电弹性体部20的表面积之比任意，但是承载台100的表面积中导电弹性体部20的表面积所占比例越高，越可降低半导体基片30的破损率。特别地，导电弹性体部20的表面积占承载台100的表面积的50％以上时，可显著降低半导体基片30的破损率。
图1中表示在承载台100的中心形成圆形的金属部10a，在承载台100的周围形成环状的金属部10b，在金属部10a和金属部10b之间形成导电弹性体部20的情况。通过这样形成、可确保承载台100和半导体基片30间的导电性并提高承载台100的表面积中导电弹性体部20的表面积所占比例，可降低半导体基片30的破损率。
另外，在需要进一步提高导电性时和因半导体基片30翘曲而在承载台100中无法确保导电性时等场合，也可如以下图5～7所示来提高金属部10所占的表面积。
图5表示在图1所示的承载台100中，形成从中心呈放射状向四个方向扩展的金属部10c的承载台101。
另外，图6表示在图1所示的承载台100中，取代金属部10a而形成从中心呈放射状向十二个方向扩展的金属部10d的承载台102。
另外，图7表示在图1所示的承载台100中，在金属部10a和金属部10b之间形成环状的金属部10e的承载台103。
图5～7中分别图示的承载台101～103与图1所示承载台100相比，金属部10所占表面积的比例高。从而，与承载台100相比可提高导电性，因此可在半导体基片30翘曲而在承载台100中无法确保导电性等场合采用。
图8表示在图1所示的承载台100中，在中心取代金属部10a而形成了比金属部10a小的圆形的金属部10f并取代金属部10b而环状形成了8个金属部10f的承载台104。
另外，图9表示十字形地形成了9个金属部10f的承载台105。
图8～9分别图示的承载台104～105与图1所示的承载台100相比，导电弹性体部20所占表面积的比例高。从而，与承载台100相比可进一步降低破损率。
即，通过任意确定金属部10及导电弹性体部20的形状，可调节半导体基片30中的导电性及破损率。
这样，本实施例的承载台100～105具有由导电性硅胶等组成的平坦导电弹性体部20，因此，即使在通过真空吸附和静电吸盘等装载半导体基片30的场合，也可降低在半导体基片30的背面附着的异物40产生的施加到半导体基片30的应力，使半导体基片30保持平坦。从而，可不使加工或检查处理中的操作性降低地防止半导体基片30的破损和变形。
再有，以上说明了导电弹性体部20由导电性硅胶组成的情况但是，导电弹性体部20不限于导电性硅胶，只要是具有导电性的弹性体即可。
(实施例2)
实施例1的承载台100～105中，通过部分地形成导电性硅胶组成的平坦导电弹性体部20，降低埋没异物40对半导体基片30施加的应力。但是，也可取代导电弹性体部20而形成作了疏面处理的金属构成的金属部。
图10是本发明的实施例2的半导体制造装置具有的承载台200的顶面图。另外，图11是图10中的B-B’截面的局部放大图。
图10表示取代图1中的导电弹性体部20而形成进行了疏面处理的金属构成的金属部(第2金属部)50。如图11所示，在金属部50的表面形成极多凹部(凹坑)51及凸部52。金属部10a～10b及凸部52与承载台200上装载的1片半导体基片30密合。再有，承载台200是真空吸附型的场合，在金属部10a～10b形成许多吸附用的孔，图10～11中省略。通过将吸附用的孔不在凹部51形成而仅在金属部10a～10b形成，可防止吸附时在凹部51中以该孔为基点对半导体基片30施加大的应力并使半导体基片30破损或变形的情况。
图12是截面图，表示即将把其背面附着了异物40的半导体基片30装载于图11所示的承载台200之前的情形。图13是截面图，表示将图12中的半导体基片30通过真空吸附装载到了承载台200上的情形。图12中，异物40在凹部51的上方附着到半导体基片30的背面时，如图13所示，异物40进入承载台200的凹部51。从而，与实施例1同样，即使在承载台200通过真空吸附装载半导体基片30时，也可降低由异物40对半导体基片30施加的应力，使半导体基片30保持平坦因此可防止半导体基片30的破损和变形。
另外，图12中即使异物40不在凹部51的上方而在凸部52的上方附着到半导体基片30的背面的场合由于伴随吸附产生的空气流将异物40推向凹部51因此可使异物40进入凹部51
图10所示的承载台200中，金属部10a～10b的表面积和金属部50的表面积之比任意，但是与实施例1同样，承载台200的表面积中金属部50的表面积所占比例越高，越可降低半导体基片30的破损率。特别地，金属部50的表面积占承载台200的表面积的50％以上时，可显著降低半导体基片30的破损率。
图10中，表示在承载台200的中心形成圆形的金属部10a，在承载台200的周围形成环状的金属部10b，在金属部10a和金属部10b之间形成金属部50的情况。通过这样形成，与实施例1同样，可确保承载台200和半导体基片30间的导电性并提高承载台200的表面积中金属部50的表面积所占比例，可降低半导体基片30的破损率。
另外，与实施例1同样，需要进一步提高导电性时和半导体基片30翘曲而在承载台200中无法确保导电性时等，如以下图14～16所示，也可提高金属部10所占表面积。
图14～16表示取代图5～7中的导电弹性体部20而形成金属部50。
图14～16分别图示的承载台201～203与图10所示承载台200相比，金属部10所占表面积的比例高。从而，与承载台200相比可进一步提高导电性，因此可在半导体基片30翘曲而在承载台200中无法确保导电性等场合采用。
图17～18表示取代图8～9中的导电弹性体部20而形成金属部50。
图17～18分别图示的承载台204～205与图10所示承载台200相比，金属部50所占表面积的比例高。从而，与承载台200相比可进一步降低破损率。
即，通过任意确定金属部10及金属部50的形状，可调节半导体基片30中的导电性及破损率。
另外，图11～13中表示了金属部50的凹部51的截面呈矩形的情况，但是如图19所示，可取代矩形的凹部51而形成截面为曲线状的凹部53。或如图20所示，也可形成凹部51、53两者。即，该孔和凸部51、53中，深度、宽度、形状及位置可任意确定。另外，凹部51、53中的宽度为1～10000μm2、深度为1～100μm时，可更显著地降低半导体基片30的破损率。
另外，图11、19～20所示的凹部51、53中，也可如图21～23所示埋入导电弹性体60。即，图21～23分别表示在图11、19～20中的凹部51、53埋入导电弹性体60。通过在凹部51、53埋入导电弹性体60，可降低在半导体基片30的第一主面和第二主面之间或半导体基片30的第一主面上形成的上部电极和承载台200之间施加高电压时的异常放电。
这样，本实施例的承载台200～205，取代实施例1的承载台100～105中的导电弹性体部20而形成进行了疏面处理的金属构成的金属部50。从而，与实施例1同样，可不使加工或检查处理中的操作性降低地防止半导体基片30的破损和变形。
再有，上述说明了金属部50由作了疏面处理的金属构成的情况，但是不限于疏面处理，只要是可在金属部50的表面形成极多凹坑即可。
本发明虽然进行了详细说明，但是上述说明在所有方面中只是例示而并不限定本发明。可以想见未例示的众多变形例并不在本发明范围之外。

Claims (6)

1.一种具有装载半导体基片(30)的承载台(200～205)的半导体制造装置，其中，
所述承载台(200～205)具备：
由在表面未作形成极多凹坑(51，53)的处理的金属构成的、与装载的所述半导体基片(30)触碰的第1金属部(10)；
由在表面作了形成极多凹坑(51，53)的处理的金属构成的与装载的所述半导体基片(30)触碰的第2金属部(50)，
在所述第1金属部(10)上形成吸附用的多个孔，
在第2金属部(50)的所述凹坑(51，53)中未形成吸附用的孔。
2.权利要求1所述的半导体制造装置，其中，
所述第1金属部(10)包含在所述承载台(200，203)的中心形成的圆形金属部(10a)和在所述承载台(200，203)的周围形成的环状金属部(10b)。
3.权利要求1所述的半导体制造装置，其中，
所述第2金属部(50)的表面积占所述承载台(200～205)的表面积的50％以上。
4.权利要求2所述的半导体制造装置，其中，
所述第2金属部(50)的表面积占所述承载台(200～205)的表面积的50％以上。
5.权利要求1所述的半导体制造装置，其中，
所述凹坑(51，53)的开口部面积为1～10000μm2，深度为1～100μm。
6.权利要求1所述的半导体制造装置，其中，
所述承载台(200～205)还具有埋入所述凹坑(51，53)的导电弹性体(60)。
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